1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2021 Ronetix, Ilko Iliev <iliev@ronetix.at> 5 */ 6 7/dts-v1/; 8 9#include "imx8mq.dtsi" 10 11/ { 12 model = "Ronetix iMX8M-CM SoM"; 13 compatible = "ronetix,imx8mq-cm", "fsl,imx8mq"; 14 15 chosen { 16 stdout-path = &uart1; 17 }; 18 19 memory@40000000 { 20 device_type = "memory"; 21 reg = <0x00000000 0x40000000 0 0x40000000>; 22 }; 23 24 pcie0_refclk: pcie0-refclk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <100000000>; 28 }; 29 30 pmic_osc: clock-pmic { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <32768>; 34 clock-output-names = "pmic_osc"; 35 }; 36 37 osc_32k: clock-osc-32k { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32768>; 41 clock-output-names = "osc_32k"; 42 }; 43 44 reg_usdhc2_vmmc: regulator-vsd-3v3 { 45 pinctrl-names = "default"; 46 pinctrl-0 = <&pinctrl_reg_usdhc2>; 47 compatible = "regulator-fixed"; 48 regulator-name = "VSD_3V3"; 49 regulator-min-microvolt = <3300000>; 50 regulator-max-microvolt = <3300000>; 51 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 52 enable-active-high; 53 }; 54}; 55 56&A53_0 { 57 cpu-supply = <&buck2_reg>; 58}; 59 60&A53_1 { 61 cpu-supply = <&buck2_reg>; 62}; 63 64&A53_2 { 65 cpu-supply = <&buck2_reg>; 66}; 67 68&A53_3 { 69 cpu-supply = <&buck2_reg>; 70}; 71 72&ddrc { 73 operating-points-v2 = <&ddrc_opp_table>; 74 75 ddrc_opp_table: opp-table { 76 compatible = "operating-points-v2"; 77 78 opp-25M { 79 opp-hz = /bits/ 64 <25000000>; 80 }; 81 82 opp-100M { 83 opp-hz = /bits/ 64 <100000000>; 84 }; 85 86 /* 87 * On imx8mq B0 PLL can't be bypassed so low bus is 166M 88 */ 89 opp-166M { 90 opp-hz = /bits/ 64 <166935483>; 91 }; 92 93 opp-800M { 94 opp-hz = /bits/ 64 <800000000>; 95 }; 96 }; 97}; 98 99&dphy { 100 status = "okay"; 101}; 102 103&fec1 { 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_fec1>; 106 phy-mode = "rgmii-id"; 107 phy-handle = <ðphy0>; 108 fsl,magic-packet; 109 status = "okay"; 110 111 mdio { 112 #address-cells = <1>; 113 #size-cells = <0>; 114 115 ethphy0: ethernet-phy@0 { 116 compatible = "ethernet-phy-ieee802.3-c22"; 117 reg = <0>; 118 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 119 reset-assert-us = <10000>; 120 }; 121 }; 122}; 123 124&i2c1 { 125 clock-frequency = <100000>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_i2c1>; 128 status = "okay"; 129}; 130 131&i2c2 { 132 clock-frequency = <100000>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_i2c2>; 135 status = "okay"; 136 137 pmic@4b { 138 compatible = "rohm,bd71837"; 139 reg = <0x4b>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_pmic>; 142 interrupt-parent = <&gpio1>; 143 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 144 rohm,reset-snvs-powered; 145 146 #clock-cells = <0>; 147 clocks = <&osc_32k 0>; 148 clock-output-names = "clk-32k-out"; 149 150 regulators { 151 buck1_reg: BUCK1 { 152 regulator-name = "buck1"; 153 regulator-min-microvolt = <700000>; 154 regulator-max-microvolt = <1300000>; 155 regulator-boot-on; 156 regulator-always-on; 157 regulator-ramp-delay = <1250>; 158 }; 159 160 buck2_reg: BUCK2 { 161 regulator-name = "buck2"; 162 regulator-min-microvolt = <700000>; 163 regulator-max-microvolt = <1300000>; 164 regulator-boot-on; 165 regulator-always-on; 166 regulator-ramp-delay = <1250>; 167 rohm,dvs-run-voltage = <1000000>; 168 rohm,dvs-idle-voltage = <900000>; 169 }; 170 171 buck3_reg: BUCK3 { 172 // BUCK5 in datasheet 173 regulator-name = "buck3"; 174 regulator-min-microvolt = <700000>; 175 regulator-max-microvolt = <1350000>; 176 regulator-boot-on; 177 regulator-always-on; 178 }; 179 180 buck4_reg: BUCK4 { 181 // BUCK6 in datasheet 182 regulator-name = "buck4"; 183 regulator-min-microvolt = <3000000>; 184 regulator-max-microvolt = <3300000>; 185 regulator-boot-on; 186 regulator-always-on; 187 }; 188 189 buck5_reg: BUCK5 { 190 // BUCK7 in datasheet 191 regulator-name = "buck5"; 192 regulator-min-microvolt = <1605000>; 193 regulator-max-microvolt = <1995000>; 194 regulator-boot-on; 195 regulator-always-on; 196 }; 197 198 buck6_reg: BUCK6 { 199 // BUCK8 in datasheet 200 regulator-name = "buck6"; 201 regulator-min-microvolt = <800000>; 202 regulator-max-microvolt = <1400000>; 203 regulator-boot-on; 204 regulator-always-on; 205 }; 206 207 buck7_reg: BUCK7 { 208 regulator-name = "buck7"; 209 regulator-min-microvolt = <1605000>; 210 regulator-max-microvolt = <1995000>; 211 regulator-boot-on; 212 }; 213 214 buck8_reg: BUCK8 { 215 regulator-name = "buck8"; 216 regulator-min-microvolt = <800000>; 217 regulator-max-microvolt = <1400000>; 218 regulator-boot-on; 219 }; 220 221 ldo1_reg: LDO1 { 222 regulator-name = "ldo1"; 223 regulator-min-microvolt = <1600000>; 224 regulator-max-microvolt = <3300000>; 225 regulator-boot-on; 226 regulator-always-on; 227 }; 228 229 ldo2_reg: LDO2 { 230 regulator-name = "ldo2"; 231 regulator-min-microvolt = <800000>; 232 regulator-max-microvolt = <900000>; 233 regulator-boot-on; 234 regulator-always-on; 235 }; 236 237 ldo3_reg: LDO3 { 238 regulator-name = "ldo3"; 239 regulator-min-microvolt = <1800000>; 240 regulator-max-microvolt = <3300000>; 241 regulator-boot-on; 242 regulator-always-on; 243 }; 244 245 ldo4_reg: LDO4 { 246 regulator-name = "ldo4"; 247 regulator-min-microvolt = <900000>; 248 regulator-max-microvolt = <1800000>; 249 regulator-boot-on; 250 regulator-always-on; 251 }; 252 253 ldo6_reg: LDO6 { 254 regulator-name = "ldo6"; 255 regulator-min-microvolt = <900000>; 256 regulator-max-microvolt = <1800000>; 257 regulator-boot-on; 258 regulator-always-on; 259 }; 260 }; 261 }; 262 263 i2c_eeprom: i2c_eeprom@50 { 264 compatible = "microchip,24lc512"; 265 reg = <0x50>; 266 pagesize = <128>; 267 }; 268}; 269 270&lcdif { 271 status = "okay"; 272}; 273 274&pcie0 { 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_pcie0>; 277 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; 278 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 279 <&clk IMX8MQ_CLK_PCIE1_AUX>, 280 <&clk IMX8MQ_CLK_PCIE1_PHY>, 281 <&pcie0_refclk>; 282 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; 283 status = "okay"; 284}; 285 286&pgc_gpu { 287 power-supply = <&buck3_reg>; 288}; 289 290&qspi0 { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&pinctrl_qspi>; 293 status = "okay"; 294 295 mx25l51245g: flash@0 { 296 reg = <0>; 297 #address-cells = <1>; 298 #size-cells = <1>; 299 compatible = "jedec,spi-nor"; 300 spi-max-frequency = <29000000>; 301 }; 302}; 303 304&snvs_pwrkey { 305 status = "okay"; 306}; 307 308&uart1 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_uart1>; 311 status = "okay"; 312}; 313 314&usb3_phy1 { 315 status = "okay"; 316}; 317 318&usb_dwc3_1 { 319 dr_mode = "host"; 320 status = "okay"; 321}; 322 323&usdhc1 { 324 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; 325 assigned-clock-rates = <400000000>; 326 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 327 pinctrl-0 = <&pinctrl_usdhc1>; 328 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 329 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 330 vqmmc-supply = <&buck7_reg>; 331 bus-width = <8>; 332 non-removable; 333 no-sd; 334 no-sdio; 335 status = "okay"; 336}; 337 338&usdhc2 { 339 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; 340 assigned-clock-rates = <200000000>; 341 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 342 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 343 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 344 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 345 cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 346 vmmc-supply = <®_usdhc2_vmmc>; 347 status = "okay"; 348}; 349 350&wdog1 { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_wdog>; 353 fsl,ext-reset-output; 354 status = "okay"; 355}; 356 357&iomuxc { 358 pinctrl_buck2: vddarmgrp { 359 fsl,pins = < 360 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 361 >; 362 363 }; 364 365 pinctrl_fec1: fec1grp { 366 fsl,pins = < 367 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 368 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 369 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 370 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 371 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 372 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 373 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 374 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 375 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 376 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 377 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 378 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 379 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 380 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 381 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 382 >; 383 }; 384 385 pinctrl_i2c1: i2c1grp { 386 fsl,pins = < 387 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f 388 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f 389 >; 390 }; 391 392 pinctrl_i2c2: i2c2grp { 393 fsl,pins = < 394 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 395 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 396 >; 397 }; 398 399 pinctrl_pcie0: pcie0grp { 400 fsl,pins = < 401 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 402 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 403 >; 404 }; 405 406 pinctrl_pmic: pmicgrp { 407 fsl,pins = < 408 MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 /* PMIC intr */ 409 >; 410 }; 411 412 pinctrl_qspi: qspigrp { 413 fsl,pins = < 414 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 415 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 416 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 417 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 418 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 419 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 420 421 >; 422 }; 423 424 pinctrl_reg_usdhc2: regusdhc2gpiogrp { 425 fsl,pins = < 426 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 427 >; 428 }; 429 430 pinctrl_uart1: uart1grp { 431 fsl,pins = < 432 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 433 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 434 >; 435 }; 436 437 pinctrl_usdhc1: usdhc1grp { 438 fsl,pins = < 439 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 440 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 441 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 442 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 443 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 444 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 445 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 446 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 447 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 448 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 449 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 450 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 451 >; 452 }; 453 454 pinctrl_usdhc1_100mhz: usdhc1-100grp { 455 fsl,pins = < 456 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d 457 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd 458 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd 459 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd 460 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd 461 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd 462 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd 463 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd 464 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd 465 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd 466 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d 467 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 468 >; 469 }; 470 471 pinctrl_usdhc1_200mhz: usdhc1-200grp { 472 fsl,pins = < 473 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f 474 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf 475 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf 476 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf 477 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf 478 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf 479 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf 480 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf 481 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf 482 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf 483 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f 484 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 485 >; 486 }; 487 488 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { 489 fsl,pins = < 490 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 491 >; 492 }; 493 494 pinctrl_usdhc2: usdhc2grp { 495 fsl,pins = < 496 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 497 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 498 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 499 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 500 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 501 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 502 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 503 >; 504 }; 505 506 pinctrl_usdhc2_100mhz: usdhc2-100grp { 507 fsl,pins = < 508 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85 509 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5 510 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5 511 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5 512 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5 513 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5 514 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 515 >; 516 }; 517 518 pinctrl_usdhc2_200mhz: usdhc2-200grp { 519 fsl,pins = < 520 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87 521 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7 522 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7 523 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7 524 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7 525 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7 526 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 527 >; 528 }; 529 530 pinctrl_wdog: wdog1grp { 531 fsl,pins = < 532 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 533 >; 534 }; 535}; 536