1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x200000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x200000>; 15 16 atf-sram@0 { 17 reg = <0x0 0x1a000>; 18 }; 19 }; 20 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 #interrupt-cells = <3>; 27 interrupt-controller; 28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 29 <0x00 0x01840000 0x00 0xC0000>; /* GICR */ 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 dmss: dmss { 46 compatible = "simple-mfd"; 47 #address-cells = <2>; 48 #size-cells = <2>; 49 dma-ranges; 50 ranges; 51 52 ti,sci-dev-id = <25>; 53 54 secure_proxy_main: mailbox@4d000000 { 55 compatible = "ti,am654-secure-proxy"; 56 #mbox-cells = <1>; 57 reg-names = "target_data", "rt", "scfg"; 58 reg = <0x00 0x4d000000 0x00 0x80000>, 59 <0x00 0x4a600000 0x00 0x80000>, 60 <0x00 0x4a400000 0x00 0x80000>; 61 interrupt-names = "rx_012"; 62 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 63 }; 64 65 inta_main_dmss: interrupt-controller@48000000 { 66 compatible = "ti,sci-inta"; 67 reg = <0x00 0x48000000 0x00 0x100000>; 68 #interrupt-cells = <0>; 69 interrupt-controller; 70 interrupt-parent = <&gic500>; 71 msi-controller; 72 ti,sci = <&dmsc>; 73 ti,sci-dev-id = <28>; 74 ti,interrupt-ranges = <4 68 36>; 75 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 76 }; 77 78 main_bcdma: dma-controller@485c0100 { 79 compatible = "ti,am64-dmss-bcdma"; 80 reg = <0x00 0x485c0100 0x00 0x100>, 81 <0x00 0x4c000000 0x00 0x20000>, 82 <0x00 0x4a820000 0x00 0x20000>, 83 <0x00 0x4aa40000 0x00 0x20000>, 84 <0x00 0x4bc00000 0x00 0x100000>; 85 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 86 msi-parent = <&inta_main_dmss>; 87 #dma-cells = <3>; 88 89 ti,sci = <&dmsc>; 90 ti,sci-dev-id = <26>; 91 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 92 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 93 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 94 }; 95 96 main_pktdma: dma-controller@485c0000 { 97 compatible = "ti,am64-dmss-pktdma"; 98 reg = <0x00 0x485c0000 0x00 0x100>, 99 <0x00 0x4a800000 0x00 0x20000>, 100 <0x00 0x4aa00000 0x00 0x40000>, 101 <0x00 0x4b800000 0x00 0x400000>; 102 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 103 msi-parent = <&inta_main_dmss>; 104 #dma-cells = <2>; 105 106 ti,sci = <&dmsc>; 107 ti,sci-dev-id = <30>; 108 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 109 <0x24>, /* CPSW_TX_CHAN */ 110 <0x25>, /* SAUL_TX_0_CHAN */ 111 <0x26>, /* SAUL_TX_1_CHAN */ 112 <0x27>, /* ICSSG_0_TX_CHAN */ 113 <0x28>; /* ICSSG_1_TX_CHAN */ 114 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 115 <0x11>, /* RING_CPSW_TX_CHAN */ 116 <0x12>, /* RING_SAUL_TX_0_CHAN */ 117 <0x13>, /* RING_SAUL_TX_1_CHAN */ 118 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 119 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 120 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 121 <0x2b>, /* CPSW_RX_CHAN */ 122 <0x2d>, /* SAUL_RX_0_CHAN */ 123 <0x2f>, /* SAUL_RX_1_CHAN */ 124 <0x31>, /* SAUL_RX_2_CHAN */ 125 <0x33>, /* SAUL_RX_3_CHAN */ 126 <0x35>, /* ICSSG_0_RX_CHAN */ 127 <0x37>; /* ICSSG_1_RX_CHAN */ 128 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 129 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 130 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 131 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 132 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 133 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 134 }; 135 }; 136 137 dmsc: dmsc@44043000 { 138 compatible = "ti,k2g-sci"; 139 ti,host-id = <12>; 140 mbox-names = "rx", "tx"; 141 mboxes= <&secure_proxy_main 12>, 142 <&secure_proxy_main 13>; 143 reg-names = "debug_messages"; 144 reg = <0x00 0x44043000 0x00 0xfe0>; 145 146 k3_pds: power-controller { 147 compatible = "ti,sci-pm-domain"; 148 #power-domain-cells = <2>; 149 }; 150 151 k3_clks: clocks { 152 compatible = "ti,k2g-sci-clk"; 153 #clock-cells = <2>; 154 }; 155 156 k3_reset: reset-controller { 157 compatible = "ti,sci-reset"; 158 #reset-cells = <2>; 159 }; 160 }; 161 162 main_pmx0: pinctrl@f4000 { 163 compatible = "pinctrl-single"; 164 reg = <0x00 0xf4000 0x00 0x2d0>; 165 #pinctrl-cells = <1>; 166 pinctrl-single,register-width = <32>; 167 pinctrl-single,function-mask = <0xffffffff>; 168 }; 169 170 main_conf: syscon@43000000 { 171 compatible = "syscon", "simple-mfd"; 172 reg = <0x00 0x43000000 0x00 0x20000>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0x00 0x00 0x43000000 0x20000>; 176 177 chipid@14 { 178 compatible = "ti,am654-chipid"; 179 reg = <0x00000014 0x4>; 180 }; 181 182 phy_gmii_sel: phy@4044 { 183 compatible = "ti,am654-phy-gmii-sel"; 184 reg = <0x4044 0x8>; 185 #phy-cells = <1>; 186 }; 187 }; 188 189 main_uart0: serial@2800000 { 190 compatible = "ti,am64-uart", "ti,am654-uart"; 191 reg = <0x00 0x02800000 0x00 0x100>; 192 reg-shift = <2>; 193 reg-io-width = <4>; 194 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 195 clock-frequency = <48000000>; 196 current-speed = <115200>; 197 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 198 clocks = <&k3_clks 146 0>; 199 clock-names = "fclk"; 200 }; 201 202 main_uart1: serial@2810000 { 203 compatible = "ti,am64-uart", "ti,am654-uart"; 204 reg = <0x00 0x02810000 0x00 0x100>; 205 reg-shift = <2>; 206 reg-io-width = <4>; 207 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 208 clock-frequency = <48000000>; 209 current-speed = <115200>; 210 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 211 clocks = <&k3_clks 152 0>; 212 clock-names = "fclk"; 213 }; 214 215 main_uart2: serial@2820000 { 216 compatible = "ti,am64-uart", "ti,am654-uart"; 217 reg = <0x00 0x02820000 0x00 0x100>; 218 reg-shift = <2>; 219 reg-io-width = <4>; 220 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 221 clock-frequency = <48000000>; 222 current-speed = <115200>; 223 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 224 clocks = <&k3_clks 153 0>; 225 clock-names = "fclk"; 226 }; 227 228 main_uart3: serial@2830000 { 229 compatible = "ti,am64-uart", "ti,am654-uart"; 230 reg = <0x00 0x02830000 0x00 0x100>; 231 reg-shift = <2>; 232 reg-io-width = <4>; 233 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 234 clock-frequency = <48000000>; 235 current-speed = <115200>; 236 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 237 clocks = <&k3_clks 154 0>; 238 clock-names = "fclk"; 239 }; 240 241 main_uart4: serial@2840000 { 242 compatible = "ti,am64-uart", "ti,am654-uart"; 243 reg = <0x00 0x02840000 0x00 0x100>; 244 reg-shift = <2>; 245 reg-io-width = <4>; 246 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 247 clock-frequency = <48000000>; 248 current-speed = <115200>; 249 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 250 clocks = <&k3_clks 155 0>; 251 clock-names = "fclk"; 252 }; 253 254 main_uart5: serial@2850000 { 255 compatible = "ti,am64-uart", "ti,am654-uart"; 256 reg = <0x00 0x02850000 0x00 0x100>; 257 reg-shift = <2>; 258 reg-io-width = <4>; 259 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 260 clock-frequency = <48000000>; 261 current-speed = <115200>; 262 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 263 clocks = <&k3_clks 156 0>; 264 clock-names = "fclk"; 265 }; 266 267 main_uart6: serial@2860000 { 268 compatible = "ti,am64-uart", "ti,am654-uart"; 269 reg = <0x00 0x02860000 0x00 0x100>; 270 reg-shift = <2>; 271 reg-io-width = <4>; 272 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 273 clock-frequency = <48000000>; 274 current-speed = <115200>; 275 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 276 clocks = <&k3_clks 158 0>; 277 clock-names = "fclk"; 278 }; 279 280 main_i2c0: i2c@20000000 { 281 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 282 reg = <0x00 0x20000000 0x00 0x100>; 283 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 287 clocks = <&k3_clks 102 2>; 288 clock-names = "fck"; 289 }; 290 291 main_i2c1: i2c@20010000 { 292 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 293 reg = <0x00 0x20010000 0x00 0x100>; 294 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 298 clocks = <&k3_clks 103 2>; 299 clock-names = "fck"; 300 }; 301 302 main_i2c2: i2c@20020000 { 303 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 304 reg = <0x00 0x20020000 0x00 0x100>; 305 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 309 clocks = <&k3_clks 104 2>; 310 clock-names = "fck"; 311 }; 312 313 main_i2c3: i2c@20030000 { 314 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 315 reg = <0x00 0x20030000 0x00 0x100>; 316 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 320 clocks = <&k3_clks 105 2>; 321 clock-names = "fck"; 322 }; 323 324 main_spi0: spi@20100000 { 325 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 326 reg = <0x00 0x20100000 0x00 0x400>; 327 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 331 clocks = <&k3_clks 141 0>; 332 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 333 dma-names = "tx0", "rx0"; 334 }; 335 336 main_spi1: spi@20110000 { 337 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 338 reg = <0x00 0x20110000 0x00 0x400>; 339 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 343 clocks = <&k3_clks 142 0>; 344 }; 345 346 main_spi2: spi@20120000 { 347 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 348 reg = <0x00 0x20120000 0x00 0x400>; 349 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 353 clocks = <&k3_clks 143 0>; 354 }; 355 356 main_spi3: spi@20130000 { 357 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 358 reg = <0x00 0x20130000 0x00 0x400>; 359 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 144 0>; 364 }; 365 366 main_spi4: spi@20140000 { 367 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 368 reg = <0x00 0x20140000 0x00 0x400>; 369 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 373 clocks = <&k3_clks 145 0>; 374 }; 375 376 sdhci0: mmc@fa10000 { 377 compatible = "ti,am64-sdhci-8bit"; 378 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 379 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 380 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 381 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 382 clock-names = "clk_ahb", "clk_xin"; 383 mmc-ddr-1_8v; 384 mmc-hs200-1_8v; 385 mmc-hs400-1_8v; 386 ti,trm-icp = <0x2>; 387 ti,otap-del-sel-legacy = <0x0>; 388 ti,otap-del-sel-mmc-hs = <0x0>; 389 ti,otap-del-sel-ddr52 = <0x6>; 390 ti,otap-del-sel-hs200 = <0x7>; 391 ti,otap-del-sel-hs400 = <0x4>; 392 }; 393 394 sdhci1: mmc@fa00000 { 395 compatible = "ti,am64-sdhci-4bit"; 396 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 397 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 398 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 399 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 400 clock-names = "clk_ahb", "clk_xin"; 401 ti,trm-icp = <0x2>; 402 ti,otap-del-sel-legacy = <0x0>; 403 ti,otap-del-sel-sd-hs = <0xf>; 404 ti,otap-del-sel-sdr12 = <0xf>; 405 ti,otap-del-sel-sdr25 = <0xf>; 406 ti,otap-del-sel-sdr50 = <0xc>; 407 ti,otap-del-sel-sdr104 = <0x6>; 408 ti,otap-del-sel-ddr50 = <0x9>; 409 ti,clkbuf-sel = <0x7>; 410 }; 411 412 cpsw3g: ethernet@8000000 { 413 compatible = "ti,am642-cpsw-nuss"; 414 #address-cells = <2>; 415 #size-cells = <2>; 416 reg = <0x0 0x8000000 0x0 0x200000>; 417 reg-names = "cpsw_nuss"; 418 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 419 clocks = <&k3_clks 13 0>; 420 assigned-clocks = <&k3_clks 13 1>; 421 assigned-clock-parents = <&k3_clks 13 9>; 422 clock-names = "fck"; 423 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 424 425 dmas = <&main_pktdma 0xC500 15>, 426 <&main_pktdma 0xC501 15>, 427 <&main_pktdma 0xC502 15>, 428 <&main_pktdma 0xC503 15>, 429 <&main_pktdma 0xC504 15>, 430 <&main_pktdma 0xC505 15>, 431 <&main_pktdma 0xC506 15>, 432 <&main_pktdma 0xC507 15>, 433 <&main_pktdma 0x4500 15>; 434 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 435 "tx7", "rx"; 436 437 ethernet-ports { 438 #address-cells = <1>; 439 #size-cells = <0>; 440 441 cpsw_port1: port@1 { 442 reg = <1>; 443 ti,mac-only; 444 label = "port1"; 445 phys = <&phy_gmii_sel 1>; 446 mac-address = [00 00 de ad be ef]; 447 }; 448 449 cpsw_port2: port@2 { 450 reg = <2>; 451 ti,mac-only; 452 label = "port2"; 453 phys = <&phy_gmii_sel 2>; 454 mac-address = [00 01 de ad be ef]; 455 }; 456 }; 457 458 cpsw3g_mdio: mdio@f00 { 459 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 460 reg = <0x0 0xf00 0x0 0x100>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 clocks = <&k3_clks 13 0>; 464 clock-names = "fck"; 465 bus_freq = <1000000>; 466 }; 467 468 cpts@3d000 { 469 compatible = "ti,j721e-cpts"; 470 reg = <0x0 0x3d000 0x0 0x400>; 471 clocks = <&k3_clks 13 1>; 472 clock-names = "cpts"; 473 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 474 interrupt-names = "cpts"; 475 ti,cpts-ext-ts-inputs = <4>; 476 ti,cpts-periodic-outputs = <2>; 477 }; 478 }; 479 480 main_gpio0: gpio@600000 { 481 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 482 reg = <0x00 0x00600000 0x00 0x100>; 483 gpio-controller; 484 #gpio-cells = <2>; 485 interrupts = <77 0 IRQ_TYPE_EDGE_RISING>, 486 <77 1 IRQ_TYPE_EDGE_RISING>, 487 <77 2 IRQ_TYPE_EDGE_RISING>, 488 <77 3 IRQ_TYPE_EDGE_RISING>, 489 <77 4 IRQ_TYPE_EDGE_RISING>, 490 <77 5 IRQ_TYPE_EDGE_RISING>, 491 <77 6 IRQ_TYPE_EDGE_RISING>, 492 <77 7 IRQ_TYPE_EDGE_RISING>; 493 interrupt-controller; 494 #interrupt-cells = <2>; 495 ti,ngpio = <69>; 496 ti,davinci-gpio-unbanked = <0>; 497 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 498 clocks = <&k3_clks 77 0>; 499 clock-names = "gpio"; 500 }; 501 502 main_gpio1: gpio@601000 { 503 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 504 reg = <0x00 0x00601000 0x00 0x100>; 505 gpio-controller; 506 #gpio-cells = <2>; 507 interrupts = <78 0 IRQ_TYPE_EDGE_RISING>, 508 <78 1 IRQ_TYPE_EDGE_RISING>, 509 <78 2 IRQ_TYPE_EDGE_RISING>, 510 <78 3 IRQ_TYPE_EDGE_RISING>, 511 <78 4 IRQ_TYPE_EDGE_RISING>, 512 <78 5 IRQ_TYPE_EDGE_RISING>, 513 <78 6 IRQ_TYPE_EDGE_RISING>, 514 <78 7 IRQ_TYPE_EDGE_RISING>; 515 interrupt-controller; 516 #interrupt-cells = <2>; 517 ti,ngpio = <69>; 518 ti,davinci-gpio-unbanked = <0>; 519 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 520 clocks = <&k3_clks 78 0>; 521 clock-names = "gpio"; 522 }; 523 524 main_i2c0: i2c@20000000 { 525 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 526 reg = <0x0 0x20000000 0x0 0x100>; 527 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clock-names = "fck"; 531 clocks = <&k3_clks 102 2>; 532 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 533 }; 534 535 main_i2c1: i2c@20010000 { 536 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 537 reg = <0x0 0x20010000 0x0 0x100>; 538 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 539 #address-cells = <1>; 540 #size-cells = <0>; 541 clock-names = "fck"; 542 clocks = <&k3_clks 103 2>; 543 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 544 }; 545 546 main_i2c2: i2c@20020000 { 547 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 548 reg = <0x00 0x20020000 0x0 0x100>; 549 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 clock-names = "fck"; 553 clocks = <&k3_clks 104 2>; 554 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 555 }; 556 557 main_i2c3: i2c@20030000 { 558 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 559 reg = <0x00 0x20030000 0x0 0x100>; 560 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 clock-names = "fck"; 564 clocks = <&k3_clks 105 2>; 565 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 566 }; 567}; 568