1/* 2 * Copyright 2017 Chen-Yu Tsai <wens@csie.org> 3 * Copyright 2017 Icenowy Zheng <icenowy@aosc.io> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This file is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This file is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include <dt-bindings/interrupt-controller/arm-gic.h> 45#include <dt-bindings/clock/sun8i-de2.h> 46#include <dt-bindings/clock/sun8i-r40-ccu.h> 47#include <dt-bindings/clock/sun8i-tcon-top.h> 48#include <dt-bindings/reset/sun8i-r40-ccu.h> 49#include <dt-bindings/reset/sun8i-de2.h> 50#include <dt-bindings/thermal/thermal.h> 51 52/ { 53 #address-cells = <1>; 54 #size-cells = <1>; 55 interrupt-parent = <&gic>; 56 57 clocks { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 ranges; 61 62 osc24M: osc24M { 63 #clock-cells = <0>; 64 compatible = "fixed-clock"; 65 clock-frequency = <24000000>; 66 clock-accuracy = <50000>; 67 clock-output-names = "osc24M"; 68 }; 69 70 osc32k: osc32k { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <32768>; 74 clock-accuracy = <20000>; 75 clock-output-names = "ext-osc32k"; 76 }; 77 }; 78 79 cpus { 80 #address-cells = <1>; 81 #size-cells = <0>; 82 83 cpu0: cpu@0 { 84 compatible = "arm,cortex-a7"; 85 device_type = "cpu"; 86 reg = <0>; 87 }; 88 89 cpu1: cpu@1 { 90 compatible = "arm,cortex-a7"; 91 device_type = "cpu"; 92 reg = <1>; 93 }; 94 95 cpu2: cpu@2 { 96 compatible = "arm,cortex-a7"; 97 device_type = "cpu"; 98 reg = <2>; 99 }; 100 101 cpu3: cpu@3 { 102 compatible = "arm,cortex-a7"; 103 device_type = "cpu"; 104 reg = <3>; 105 }; 106 }; 107 108 de: display-engine { 109 compatible = "allwinner,sun8i-r40-display-engine"; 110 allwinner,pipelines = <&mixer0>, <&mixer1>; 111 status = "disabled"; 112 }; 113 114 thermal-zones { 115 cpu_thermal: cpu0-thermal { 116 /* milliseconds */ 117 polling-delay-passive = <0>; 118 polling-delay = <0>; 119 thermal-sensors = <&ths 0>; 120 }; 121 122 gpu_thermal: gpu-thermal { 123 /* milliseconds */ 124 polling-delay-passive = <0>; 125 polling-delay = <0>; 126 thermal-sensors = <&ths 1>; 127 }; 128 }; 129 130 soc { 131 compatible = "simple-bus"; 132 #address-cells = <1>; 133 #size-cells = <1>; 134 ranges; 135 136 display_clocks: clock@1000000 { 137 compatible = "allwinner,sun8i-r40-de2-clk", 138 "allwinner,sun8i-h3-de2-clk"; 139 reg = <0x01000000 0x10000>; 140 clocks = <&ccu CLK_BUS_DE>, 141 <&ccu CLK_DE>; 142 clock-names = "bus", 143 "mod"; 144 resets = <&ccu RST_BUS_DE>; 145 #clock-cells = <1>; 146 #reset-cells = <1>; 147 }; 148 149 mixer0: mixer@1100000 { 150 compatible = "allwinner,sun8i-r40-de2-mixer-0"; 151 reg = <0x01100000 0x100000>; 152 clocks = <&display_clocks CLK_BUS_MIXER0>, 153 <&display_clocks CLK_MIXER0>; 154 clock-names = "bus", 155 "mod"; 156 resets = <&display_clocks RST_MIXER0>; 157 158 ports { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 mixer0_out: port@1 { 163 reg = <1>; 164 mixer0_out_tcon_top: endpoint { 165 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 166 }; 167 }; 168 }; 169 }; 170 171 mixer1: mixer@1200000 { 172 compatible = "allwinner,sun8i-r40-de2-mixer-1"; 173 reg = <0x01200000 0x100000>; 174 clocks = <&display_clocks CLK_BUS_MIXER1>, 175 <&display_clocks CLK_MIXER1>; 176 clock-names = "bus", 177 "mod"; 178 resets = <&display_clocks RST_WB>; 179 180 ports { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 184 mixer1_out: port@1 { 185 reg = <1>; 186 mixer1_out_tcon_top: endpoint { 187 remote-endpoint = <&tcon_top_mixer1_in_mixer1>; 188 }; 189 }; 190 }; 191 }; 192 193 deinterlace: deinterlace@1400000 { 194 compatible = "allwinner,sun8i-r40-deinterlace", 195 "allwinner,sun8i-h3-deinterlace"; 196 reg = <0x01400000 0x20000>; 197 clocks = <&ccu CLK_BUS_DEINTERLACE>, 198 <&ccu CLK_DEINTERLACE>, 199 /* 200 * NOTE: Contrary to what datasheet claims, 201 * DRAM deinterlace gate doesn't exist and 202 * it's shared with CSI1. 203 */ 204 <&ccu CLK_DRAM_CSI1>; 205 clock-names = "bus", "mod", "ram"; 206 resets = <&ccu RST_BUS_DEINTERLACE>; 207 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 208 interconnects = <&mbus 9>; 209 interconnect-names = "dma-mem"; 210 }; 211 212 syscon: system-control@1c00000 { 213 compatible = "allwinner,sun8i-r40-system-control", 214 "allwinner,sun4i-a10-system-control"; 215 reg = <0x01c00000 0x30>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges; 219 220 sram_c: sram@1d00000 { 221 compatible = "mmio-sram"; 222 reg = <0x01d00000 0xd0000>; 223 #address-cells = <1>; 224 #size-cells = <1>; 225 ranges = <0 0x01d00000 0xd0000>; 226 227 ve_sram: sram-section@0 { 228 compatible = "allwinner,sun8i-r40-sram-c1", 229 "allwinner,sun4i-a10-sram-c1"; 230 reg = <0x000000 0x80000>; 231 }; 232 }; 233 }; 234 235 nmi_intc: interrupt-controller@1c00030 { 236 compatible = "allwinner,sun7i-a20-sc-nmi"; 237 interrupt-controller; 238 #interrupt-cells = <2>; 239 reg = <0x01c00030 0x0c>; 240 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 241 }; 242 243 dma: dma-controller@1c02000 { 244 compatible = "allwinner,sun8i-r40-dma", 245 "allwinner,sun50i-a64-dma"; 246 reg = <0x01c02000 0x1000>; 247 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&ccu CLK_BUS_DMA>; 249 dma-channels = <16>; 250 dma-requests = <31>; 251 resets = <&ccu RST_BUS_DMA>; 252 #dma-cells = <1>; 253 }; 254 255 spi0: spi@1c05000 { 256 compatible = "allwinner,sun8i-r40-spi", 257 "allwinner,sun8i-h3-spi"; 258 reg = <0x01c05000 0x1000>; 259 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 260 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 261 clock-names = "ahb", "mod"; 262 resets = <&ccu RST_BUS_SPI0>; 263 status = "disabled"; 264 #address-cells = <1>; 265 #size-cells = <0>; 266 }; 267 268 spi1: spi@1c06000 { 269 compatible = "allwinner,sun8i-r40-spi", 270 "allwinner,sun8i-h3-spi"; 271 reg = <0x01c06000 0x1000>; 272 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 273 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 274 clock-names = "ahb", "mod"; 275 resets = <&ccu RST_BUS_SPI1>; 276 status = "disabled"; 277 #address-cells = <1>; 278 #size-cells = <0>; 279 }; 280 281 csi0: csi@1c09000 { 282 compatible = "allwinner,sun8i-r40-csi0", 283 "allwinner,sun7i-a20-csi0"; 284 reg = <0x01c09000 0x1000>; 285 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, 287 <&ccu CLK_DRAM_CSI0>; 288 clock-names = "bus", "isp", "ram"; 289 resets = <&ccu RST_BUS_CSI0>; 290 interconnects = <&mbus 5>; 291 interconnect-names = "dma-mem"; 292 status = "disabled"; 293 }; 294 295 video-codec@1c0e000 { 296 compatible = "allwinner,sun8i-r40-video-engine"; 297 reg = <0x01c0e000 0x1000>; 298 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 299 <&ccu CLK_DRAM_VE>; 300 clock-names = "ahb", "mod", "ram"; 301 resets = <&ccu RST_BUS_VE>; 302 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 303 allwinner,sram = <&ve_sram 1>; 304 }; 305 306 mmc0: mmc@1c0f000 { 307 compatible = "allwinner,sun8i-r40-mmc", 308 "allwinner,sun50i-a64-mmc"; 309 reg = <0x01c0f000 0x1000>; 310 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 311 clock-names = "ahb", "mmc"; 312 resets = <&ccu RST_BUS_MMC0>; 313 reset-names = "ahb"; 314 pinctrl-0 = <&mmc0_pins>; 315 pinctrl-names = "default"; 316 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 317 status = "disabled"; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 }; 321 322 mmc1: mmc@1c10000 { 323 compatible = "allwinner,sun8i-r40-mmc", 324 "allwinner,sun50i-a64-mmc"; 325 reg = <0x01c10000 0x1000>; 326 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 327 clock-names = "ahb", "mmc"; 328 resets = <&ccu RST_BUS_MMC1>; 329 reset-names = "ahb"; 330 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 331 status = "disabled"; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 }; 335 336 mmc2: mmc@1c11000 { 337 compatible = "allwinner,sun8i-r40-emmc", 338 "allwinner,sun50i-a64-emmc"; 339 reg = <0x01c11000 0x1000>; 340 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 341 clock-names = "ahb", "mmc"; 342 resets = <&ccu RST_BUS_MMC2>; 343 reset-names = "ahb"; 344 pinctrl-0 = <&mmc2_pins>; 345 pinctrl-names = "default"; 346 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 347 status = "disabled"; 348 #address-cells = <1>; 349 #size-cells = <0>; 350 }; 351 352 mmc3: mmc@1c12000 { 353 compatible = "allwinner,sun8i-r40-mmc", 354 "allwinner,sun50i-a64-mmc"; 355 reg = <0x01c12000 0x1000>; 356 clocks = <&ccu CLK_BUS_MMC3>, <&ccu CLK_MMC3>; 357 clock-names = "ahb", "mmc"; 358 resets = <&ccu RST_BUS_MMC3>; 359 reset-names = "ahb"; 360 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 361 status = "disabled"; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 }; 365 366 usbphy: phy@1c13400 { 367 compatible = "allwinner,sun8i-r40-usb-phy"; 368 reg = <0x01c13400 0x14>, 369 <0x01c14800 0x4>, 370 <0x01c19800 0x4>, 371 <0x01c1c800 0x4>; 372 reg-names = "phy_ctrl", 373 "pmu0", 374 "pmu1", 375 "pmu2"; 376 clocks = <&ccu CLK_USB_PHY0>, 377 <&ccu CLK_USB_PHY1>, 378 <&ccu CLK_USB_PHY2>; 379 clock-names = "usb0_phy", 380 "usb1_phy", 381 "usb2_phy"; 382 resets = <&ccu RST_USB_PHY0>, 383 <&ccu RST_USB_PHY1>, 384 <&ccu RST_USB_PHY2>; 385 reset-names = "usb0_reset", 386 "usb1_reset", 387 "usb2_reset"; 388 status = "disabled"; 389 #phy-cells = <1>; 390 }; 391 392 crypto: crypto@1c15000 { 393 compatible = "allwinner,sun8i-r40-crypto"; 394 reg = <0x01c15000 0x1000>; 395 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 397 clock-names = "bus", "mod"; 398 resets = <&ccu RST_BUS_CE>; 399 }; 400 401 spi2: spi@1c17000 { 402 compatible = "allwinner,sun8i-r40-spi", 403 "allwinner,sun8i-h3-spi"; 404 reg = <0x01c17000 0x1000>; 405 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 406 clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; 407 clock-names = "ahb", "mod"; 408 resets = <&ccu RST_BUS_SPI2>; 409 status = "disabled"; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 }; 413 414 ahci: sata@1c18000 { 415 compatible = "allwinner,sun8i-r40-ahci"; 416 reg = <0x01c18000 0x1000>; 417 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; 419 resets = <&ccu RST_BUS_SATA>; 420 reset-names = "ahci"; 421 status = "disabled"; 422 }; 423 424 ehci1: usb@1c19000 { 425 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 426 reg = <0x01c19000 0x100>; 427 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&ccu CLK_BUS_EHCI1>; 429 resets = <&ccu RST_BUS_EHCI1>; 430 phys = <&usbphy 1>; 431 phy-names = "usb"; 432 status = "disabled"; 433 }; 434 435 ohci1: usb@1c19400 { 436 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 437 reg = <0x01c19400 0x100>; 438 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&ccu CLK_BUS_OHCI1>, 440 <&ccu CLK_USB_OHCI1>; 441 resets = <&ccu RST_BUS_OHCI1>; 442 phys = <&usbphy 1>; 443 phy-names = "usb"; 444 status = "disabled"; 445 }; 446 447 ehci2: usb@1c1c000 { 448 compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; 449 reg = <0x01c1c000 0x100>; 450 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&ccu CLK_BUS_EHCI2>; 452 resets = <&ccu RST_BUS_EHCI2>; 453 phys = <&usbphy 2>; 454 phy-names = "usb"; 455 status = "disabled"; 456 }; 457 458 ohci2: usb@1c1c400 { 459 compatible = "allwinner,sun8i-r40-ohci", "generic-ohci"; 460 reg = <0x01c1c400 0x100>; 461 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 462 clocks = <&ccu CLK_BUS_OHCI2>, 463 <&ccu CLK_USB_OHCI2>; 464 resets = <&ccu RST_BUS_OHCI2>; 465 phys = <&usbphy 2>; 466 phy-names = "usb"; 467 status = "disabled"; 468 }; 469 470 spi3: spi@1c1f000 { 471 compatible = "allwinner,sun8i-r40-spi", 472 "allwinner,sun8i-h3-spi"; 473 reg = <0x01c1f000 0x1000>; 474 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 475 clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; 476 clock-names = "ahb", "mod"; 477 resets = <&ccu RST_BUS_SPI3>; 478 status = "disabled"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 }; 482 483 ccu: clock@1c20000 { 484 compatible = "allwinner,sun8i-r40-ccu"; 485 reg = <0x01c20000 0x400>; 486 clocks = <&osc24M>, <&rtc 0>; 487 clock-names = "hosc", "losc"; 488 #clock-cells = <1>; 489 #reset-cells = <1>; 490 }; 491 492 rtc: rtc@1c20400 { 493 compatible = "allwinner,sun8i-r40-rtc"; 494 reg = <0x01c20400 0x400>; 495 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 496 clock-output-names = "osc32k", "osc32k-out"; 497 clocks = <&osc32k>; 498 #clock-cells = <1>; 499 }; 500 501 pio: pinctrl@1c20800 { 502 compatible = "allwinner,sun8i-r40-pinctrl"; 503 reg = <0x01c20800 0x400>; 504 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 506 clock-names = "apb", "hosc", "losc"; 507 gpio-controller; 508 interrupt-controller; 509 #interrupt-cells = <3>; 510 #gpio-cells = <3>; 511 512 clk_out_a_pin: clk-out-a-pin { 513 pins = "PI12"; 514 function = "clk_out_a"; 515 }; 516 517 /omit-if-no-ref/ 518 csi0_8bits_pins: csi0-8bits-pins { 519 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 520 "PE6", "PE7", "PE8", "PE9", "PE10", 521 "PE11"; 522 function = "csi0"; 523 }; 524 525 /omit-if-no-ref/ 526 csi0_mclk_pin: csi0-mclk-pin { 527 pins = "PE1"; 528 function = "csi0"; 529 }; 530 531 gmac_rgmii_pins: gmac-rgmii-pins { 532 pins = "PA0", "PA1", "PA2", "PA3", 533 "PA4", "PA5", "PA6", "PA7", 534 "PA8", "PA10", "PA11", "PA12", 535 "PA13", "PA15", "PA16"; 536 function = "gmac"; 537 /* 538 * data lines in RGMII mode use DDR mode 539 * and need a higher signal drive strength 540 */ 541 drive-strength = <40>; 542 }; 543 544 i2c0_pins: i2c0-pins { 545 pins = "PB0", "PB1"; 546 function = "i2c0"; 547 }; 548 549 i2c1_pins: i2c1-pins { 550 pins = "PB18", "PB19"; 551 function = "i2c1"; 552 }; 553 554 i2c2_pins: i2c2-pins { 555 pins = "PB20", "PB21"; 556 function = "i2c2"; 557 }; 558 559 i2c3_pins: i2c3-pins { 560 pins = "PI0", "PI1"; 561 function = "i2c3"; 562 }; 563 564 i2c4_pins: i2c4-pins { 565 pins = "PI2", "PI3"; 566 function = "i2c4"; 567 }; 568 569 ir0_pins: ir0-pins { 570 pins = "PB4"; 571 function = "ir0"; 572 }; 573 574 ir1_pins: ir1-pins { 575 pins = "PB23"; 576 function = "ir1"; 577 }; 578 579 mmc0_pins: mmc0-pins { 580 pins = "PF0", "PF1", "PF2", 581 "PF3", "PF4", "PF5"; 582 function = "mmc0"; 583 drive-strength = <30>; 584 bias-pull-up; 585 }; 586 587 mmc1_pg_pins: mmc1-pg-pins { 588 pins = "PG0", "PG1", "PG2", 589 "PG3", "PG4", "PG5"; 590 function = "mmc1"; 591 drive-strength = <30>; 592 bias-pull-up; 593 }; 594 595 mmc2_pins: mmc2-pins { 596 pins = "PC5", "PC6", "PC7", "PC8", "PC9", 597 "PC10", "PC11", "PC12", "PC13", "PC14", 598 "PC15", "PC24"; 599 function = "mmc2"; 600 drive-strength = <30>; 601 bias-pull-up; 602 }; 603 604 /omit-if-no-ref/ 605 spi0_pc_pins: spi0-pc-pins { 606 pins = "PC0", "PC1", "PC2"; 607 function = "spi0"; 608 }; 609 610 /omit-if-no-ref/ 611 spi0_cs0_pc_pin: spi0-cs0-pc-pin { 612 pins = "PC23"; 613 function = "spi0"; 614 }; 615 616 /omit-if-no-ref/ 617 spi1_pi_pins: spi1-pi-pins { 618 pins = "PI17", "PI18", "PI19"; 619 function = "spi1"; 620 }; 621 622 /omit-if-no-ref/ 623 spi1_cs0_pi_pin: spi1-cs0-pi-pin { 624 pins = "PI16"; 625 function = "spi1"; 626 }; 627 628 /omit-if-no-ref/ 629 spi1_cs1_pi_pin: spi1-cs1-pi-pin { 630 pins = "PI15"; 631 function = "spi1"; 632 }; 633 634 uart0_pb_pins: uart0-pb-pins { 635 pins = "PB22", "PB23"; 636 function = "uart0"; 637 }; 638 639 uart3_pg_pins: uart3-pg-pins { 640 pins = "PG6", "PG7"; 641 function = "uart3"; 642 }; 643 644 uart3_rts_cts_pg_pins: uart3-rts-cts-pg-pins { 645 pins = "PG8", "PG9"; 646 function = "uart3"; 647 }; 648 }; 649 650 wdt: watchdog@1c20c90 { 651 compatible = "allwinner,sun4i-a10-wdt"; 652 reg = <0x01c20c90 0x10>; 653 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&osc24M>; 655 }; 656 657 ir0: ir@1c21800 { 658 compatible = "allwinner,sun8i-r40-ir", 659 "allwinner,sun6i-a31-ir"; 660 reg = <0x01c21800 0x400>; 661 pinctrl-0 = <&ir0_pins>; 662 pinctrl-names = "default"; 663 clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; 664 clock-names = "apb", "ir"; 665 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 666 resets = <&ccu RST_BUS_IR0>; 667 status = "disabled"; 668 }; 669 670 ir1: ir@1c21c00 { 671 compatible = "allwinner,sun8i-r40-ir", 672 "allwinner,sun6i-a31-ir"; 673 reg = <0x01c21c00 0x400>; 674 pinctrl-0 = <&ir1_pins>; 675 pinctrl-names = "default"; 676 clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; 677 clock-names = "apb", "ir"; 678 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 679 resets = <&ccu RST_BUS_IR1>; 680 status = "disabled"; 681 }; 682 683 ths: thermal-sensor@1c24c00 { 684 compatible = "allwinner,sun8i-r40-ths"; 685 reg = <0x01c24c00 0x100>; 686 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 687 clock-names = "bus", "mod"; 688 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 689 resets = <&ccu RST_BUS_THS>; 690 /* TODO: add nvmem-cells for calibration */ 691 #thermal-sensor-cells = <1>; 692 }; 693 694 uart0: serial@1c28000 { 695 compatible = "snps,dw-apb-uart"; 696 reg = <0x01c28000 0x400>; 697 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 698 reg-shift = <2>; 699 reg-io-width = <4>; 700 clocks = <&ccu CLK_BUS_UART0>; 701 resets = <&ccu RST_BUS_UART0>; 702 status = "disabled"; 703 }; 704 705 uart1: serial@1c28400 { 706 compatible = "snps,dw-apb-uart"; 707 reg = <0x01c28400 0x400>; 708 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 709 reg-shift = <2>; 710 reg-io-width = <4>; 711 clocks = <&ccu CLK_BUS_UART1>; 712 resets = <&ccu RST_BUS_UART1>; 713 status = "disabled"; 714 }; 715 716 uart2: serial@1c28800 { 717 compatible = "snps,dw-apb-uart"; 718 reg = <0x01c28800 0x400>; 719 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 720 reg-shift = <2>; 721 reg-io-width = <4>; 722 clocks = <&ccu CLK_BUS_UART2>; 723 resets = <&ccu RST_BUS_UART2>; 724 status = "disabled"; 725 }; 726 727 uart3: serial@1c28c00 { 728 compatible = "snps,dw-apb-uart"; 729 reg = <0x01c28c00 0x400>; 730 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 731 reg-shift = <2>; 732 reg-io-width = <4>; 733 clocks = <&ccu CLK_BUS_UART3>; 734 resets = <&ccu RST_BUS_UART3>; 735 status = "disabled"; 736 }; 737 738 uart4: serial@1c29000 { 739 compatible = "snps,dw-apb-uart"; 740 reg = <0x01c29000 0x400>; 741 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 742 reg-shift = <2>; 743 reg-io-width = <4>; 744 clocks = <&ccu CLK_BUS_UART4>; 745 resets = <&ccu RST_BUS_UART4>; 746 status = "disabled"; 747 }; 748 749 uart5: serial@1c29400 { 750 compatible = "snps,dw-apb-uart"; 751 reg = <0x01c29400 0x400>; 752 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 753 reg-shift = <2>; 754 reg-io-width = <4>; 755 clocks = <&ccu CLK_BUS_UART5>; 756 resets = <&ccu RST_BUS_UART5>; 757 status = "disabled"; 758 }; 759 760 uart6: serial@1c29800 { 761 compatible = "snps,dw-apb-uart"; 762 reg = <0x01c29800 0x400>; 763 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 764 reg-shift = <2>; 765 reg-io-width = <4>; 766 clocks = <&ccu CLK_BUS_UART6>; 767 resets = <&ccu RST_BUS_UART6>; 768 status = "disabled"; 769 }; 770 771 uart7: serial@1c29c00 { 772 compatible = "snps,dw-apb-uart"; 773 reg = <0x01c29c00 0x400>; 774 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 775 reg-shift = <2>; 776 reg-io-width = <4>; 777 clocks = <&ccu CLK_BUS_UART7>; 778 resets = <&ccu RST_BUS_UART7>; 779 status = "disabled"; 780 }; 781 782 i2c0: i2c@1c2ac00 { 783 compatible = "allwinner,sun6i-a31-i2c"; 784 reg = <0x01c2ac00 0x400>; 785 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&ccu CLK_BUS_I2C0>; 787 resets = <&ccu RST_BUS_I2C0>; 788 pinctrl-0 = <&i2c0_pins>; 789 pinctrl-names = "default"; 790 status = "disabled"; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 }; 794 795 i2c1: i2c@1c2b000 { 796 compatible = "allwinner,sun6i-a31-i2c"; 797 reg = <0x01c2b000 0x400>; 798 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&ccu CLK_BUS_I2C1>; 800 resets = <&ccu RST_BUS_I2C1>; 801 pinctrl-0 = <&i2c1_pins>; 802 pinctrl-names = "default"; 803 status = "disabled"; 804 #address-cells = <1>; 805 #size-cells = <0>; 806 }; 807 808 i2c2: i2c@1c2b400 { 809 compatible = "allwinner,sun6i-a31-i2c"; 810 reg = <0x01c2b400 0x400>; 811 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&ccu CLK_BUS_I2C2>; 813 resets = <&ccu RST_BUS_I2C2>; 814 pinctrl-0 = <&i2c2_pins>; 815 pinctrl-names = "default"; 816 status = "disabled"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 }; 820 821 i2c3: i2c@1c2b800 { 822 compatible = "allwinner,sun6i-a31-i2c"; 823 reg = <0x01c2b800 0x400>; 824 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&ccu CLK_BUS_I2C3>; 826 resets = <&ccu RST_BUS_I2C3>; 827 pinctrl-0 = <&i2c3_pins>; 828 pinctrl-names = "default"; 829 status = "disabled"; 830 #address-cells = <1>; 831 #size-cells = <0>; 832 }; 833 834 i2c4: i2c@1c2c000 { 835 compatible = "allwinner,sun6i-a31-i2c"; 836 reg = <0x01c2c000 0x400>; 837 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&ccu CLK_BUS_I2C4>; 839 resets = <&ccu RST_BUS_I2C4>; 840 pinctrl-0 = <&i2c4_pins>; 841 pinctrl-names = "default"; 842 status = "disabled"; 843 #address-cells = <1>; 844 #size-cells = <0>; 845 }; 846 847 mali: gpu@1c40000 { 848 compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; 849 reg = <0x01c40000 0x10000>; 850 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 851 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 853 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 854 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 855 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 857 interrupt-names = "gp", 858 "gpmmu", 859 "pp0", 860 "ppmmu0", 861 "pp1", 862 "ppmmu1", 863 "pmu"; 864 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 865 clock-names = "bus", "core"; 866 resets = <&ccu RST_BUS_GPU>; 867 }; 868 869 gmac: ethernet@1c50000 { 870 compatible = "allwinner,sun8i-r40-gmac"; 871 syscon = <&ccu>; 872 reg = <0x01c50000 0x10000>; 873 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 874 interrupt-names = "macirq"; 875 resets = <&ccu RST_BUS_GMAC>; 876 reset-names = "stmmaceth"; 877 clocks = <&ccu CLK_BUS_GMAC>; 878 clock-names = "stmmaceth"; 879 status = "disabled"; 880 881 gmac_mdio: mdio { 882 compatible = "snps,dwmac-mdio"; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 }; 886 }; 887 888 mbus: dram-controller@1c62000 { 889 compatible = "allwinner,sun8i-r40-mbus"; 890 reg = <0x01c62000 0x1000>; 891 clocks = <&ccu 155>; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 dma-ranges = <0x00000000 0x40000000 0x80000000>; 895 #interconnect-cells = <1>; 896 }; 897 898 tcon_top: tcon-top@1c70000 { 899 compatible = "allwinner,sun8i-r40-tcon-top"; 900 reg = <0x01c70000 0x1000>; 901 clocks = <&ccu CLK_BUS_TCON_TOP>, 902 <&ccu CLK_TCON_TV0>, 903 <&ccu CLK_TVE0>, 904 <&ccu CLK_TCON_TV1>, 905 <&ccu CLK_TVE1>, 906 <&ccu CLK_DSI_DPHY>; 907 clock-names = "bus", 908 "tcon-tv0", 909 "tve0", 910 "tcon-tv1", 911 "tve1", 912 "dsi"; 913 clock-output-names = "tcon-top-tv0", 914 "tcon-top-tv1", 915 "tcon-top-dsi"; 916 resets = <&ccu RST_BUS_TCON_TOP>; 917 #clock-cells = <1>; 918 919 ports { 920 #address-cells = <1>; 921 #size-cells = <0>; 922 923 tcon_top_mixer0_in: port@0 { 924 reg = <0>; 925 926 tcon_top_mixer0_in_mixer0: endpoint { 927 remote-endpoint = <&mixer0_out_tcon_top>; 928 }; 929 }; 930 931 tcon_top_mixer0_out: port@1 { 932 #address-cells = <1>; 933 #size-cells = <0>; 934 reg = <1>; 935 936 tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { 937 reg = <0>; 938 }; 939 940 tcon_top_mixer0_out_tcon_lcd1: endpoint@1 { 941 reg = <1>; 942 }; 943 944 tcon_top_mixer0_out_tcon_tv0: endpoint@2 { 945 reg = <2>; 946 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; 947 }; 948 949 tcon_top_mixer0_out_tcon_tv1: endpoint@3 { 950 reg = <3>; 951 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer0>; 952 }; 953 }; 954 955 tcon_top_mixer1_in: port@2 { 956 #address-cells = <1>; 957 #size-cells = <0>; 958 reg = <2>; 959 960 tcon_top_mixer1_in_mixer1: endpoint@1 { 961 reg = <1>; 962 remote-endpoint = <&mixer1_out_tcon_top>; 963 }; 964 }; 965 966 tcon_top_mixer1_out: port@3 { 967 #address-cells = <1>; 968 #size-cells = <0>; 969 reg = <3>; 970 971 tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { 972 reg = <0>; 973 }; 974 975 tcon_top_mixer1_out_tcon_lcd1: endpoint@1 { 976 reg = <1>; 977 }; 978 979 tcon_top_mixer1_out_tcon_tv0: endpoint@2 { 980 reg = <2>; 981 remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; 982 }; 983 984 tcon_top_mixer1_out_tcon_tv1: endpoint@3 { 985 reg = <3>; 986 remote-endpoint = <&tcon_tv1_in_tcon_top_mixer1>; 987 }; 988 }; 989 990 tcon_top_hdmi_in: port@4 { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 reg = <4>; 994 995 tcon_top_hdmi_in_tcon_tv0: endpoint@0 { 996 reg = <0>; 997 remote-endpoint = <&tcon_tv0_out_tcon_top>; 998 }; 999 1000 tcon_top_hdmi_in_tcon_tv1: endpoint@1 { 1001 reg = <1>; 1002 remote-endpoint = <&tcon_tv1_out_tcon_top>; 1003 }; 1004 }; 1005 1006 tcon_top_hdmi_out: port@5 { 1007 reg = <5>; 1008 1009 tcon_top_hdmi_out_hdmi: endpoint { 1010 remote-endpoint = <&hdmi_in_tcon_top>; 1011 }; 1012 }; 1013 }; 1014 }; 1015 1016 tcon_tv0: lcd-controller@1c73000 { 1017 compatible = "allwinner,sun8i-r40-tcon-tv"; 1018 reg = <0x01c73000 0x1000>; 1019 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; 1021 clock-names = "ahb", "tcon-ch1"; 1022 resets = <&ccu RST_BUS_TCON_TV0>; 1023 reset-names = "lcd"; 1024 status = "disabled"; 1025 1026 ports { 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 1030 tcon_tv0_in: port@0 { 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 reg = <0>; 1034 1035 tcon_tv0_in_tcon_top_mixer0: endpoint@0 { 1036 reg = <0>; 1037 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; 1038 }; 1039 1040 tcon_tv0_in_tcon_top_mixer1: endpoint@1 { 1041 reg = <1>; 1042 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; 1043 }; 1044 }; 1045 1046 tcon_tv0_out: port@1 { 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 reg = <1>; 1050 1051 tcon_tv0_out_tcon_top: endpoint@1 { 1052 reg = <1>; 1053 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; 1054 }; 1055 }; 1056 }; 1057 }; 1058 1059 tcon_tv1: lcd-controller@1c74000 { 1060 compatible = "allwinner,sun8i-r40-tcon-tv"; 1061 reg = <0x01c74000 0x1000>; 1062 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; 1064 clock-names = "ahb", "tcon-ch1"; 1065 resets = <&ccu RST_BUS_TCON_TV1>; 1066 reset-names = "lcd"; 1067 status = "disabled"; 1068 1069 ports { 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 1073 tcon_tv1_in: port@0 { 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 reg = <0>; 1077 1078 tcon_tv1_in_tcon_top_mixer0: endpoint@0 { 1079 reg = <0>; 1080 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv1>; 1081 }; 1082 1083 tcon_tv1_in_tcon_top_mixer1: endpoint@1 { 1084 reg = <1>; 1085 remote-endpoint = <&tcon_top_mixer1_out_tcon_tv1>; 1086 }; 1087 }; 1088 1089 tcon_tv1_out: port@1 { 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 reg = <1>; 1093 1094 tcon_tv1_out_tcon_top: endpoint@1 { 1095 reg = <1>; 1096 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv1>; 1097 }; 1098 }; 1099 }; 1100 }; 1101 1102 gic: interrupt-controller@1c81000 { 1103 compatible = "arm,gic-400"; 1104 reg = <0x01c81000 0x1000>, 1105 <0x01c82000 0x2000>, 1106 <0x01c84000 0x2000>, 1107 <0x01c86000 0x2000>; 1108 interrupt-controller; 1109 #interrupt-cells = <3>; 1110 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1111 }; 1112 1113 hdmi: hdmi@1ee0000 { 1114 compatible = "allwinner,sun8i-r40-dw-hdmi", 1115 "allwinner,sun8i-a83t-dw-hdmi"; 1116 reg = <0x01ee0000 0x10000>; 1117 reg-io-width = <1>; 1118 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1119 clocks = <&ccu CLK_BUS_HDMI0>, <&ccu CLK_HDMI_SLOW>, 1120 <&ccu CLK_HDMI>; 1121 clock-names = "iahb", "isfr", "tmds"; 1122 resets = <&ccu RST_BUS_HDMI1>; 1123 reset-names = "ctrl"; 1124 phys = <&hdmi_phy>; 1125 phy-names = "phy"; 1126 status = "disabled"; 1127 1128 ports { 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 1132 hdmi_in: port@0 { 1133 reg = <0>; 1134 1135 hdmi_in_tcon_top: endpoint { 1136 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 1137 }; 1138 }; 1139 1140 hdmi_out: port@1 { 1141 reg = <1>; 1142 }; 1143 }; 1144 }; 1145 1146 hdmi_phy: hdmi-phy@1ef0000 { 1147 compatible = "allwinner,sun8i-r40-hdmi-phy"; 1148 reg = <0x01ef0000 0x10000>; 1149 clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, 1150 <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; 1151 clock-names = "bus", "mod", "pll-0", "pll-1"; 1152 resets = <&ccu RST_BUS_HDMI0>; 1153 reset-names = "phy"; 1154 #phy-cells = <0>; 1155 }; 1156 }; 1157 1158 pmu { 1159 compatible = "arm,cortex-a7-pmu"; 1160 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1164 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1165 }; 1166 1167 timer { 1168 compatible = "arm,armv7-timer"; 1169 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1170 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1171 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1172 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1173 }; 1174}; 1175