1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
4 * Copyright (C) 1995, 1996 Paul M. Antoine
5 * Copyright (C) 1998 Ulf Carlsson
6 * Copyright (C) 1999 Silicon Graphics, Inc.
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
9 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved.
10 * Copyright (C) 2014, Imagination Technologies Ltd.
11 */
12
13 #include <common.h>
14 #include <asm/global_data.h>
15 #include <asm/ptrace.h>
16 #include <cpu_func.h>
17 #include <hang.h>
18 #include <init.h>
19 #include <log.h>
20 #include <asm/mipsregs.h>
21 #include <asm/addrspace.h>
22 #include <asm/system.h>
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 static unsigned long saved_ebase;
27
show_regs(const struct pt_regs * regs)28 static void show_regs(const struct pt_regs *regs)
29 {
30 const int field = 2 * sizeof(unsigned long);
31 unsigned int cause = regs->cp0_cause;
32 unsigned int exccode;
33 int i;
34
35 /*
36 * Saved main processor registers
37 */
38 for (i = 0; i < 32; ) {
39 if ((i % 4) == 0)
40 printf("$%2d :", i);
41 if (i == 0)
42 printf(" %0*lx", field, 0UL);
43 else if (i == 26 || i == 27)
44 printf(" %*s", field, "");
45 else
46 printf(" %0*lx", field, regs->regs[i]);
47
48 i++;
49 if ((i % 4) == 0)
50 puts("\n");
51 }
52
53 printf("Hi : %0*lx\n", field, regs->hi);
54 printf("Lo : %0*lx\n", field, regs->lo);
55
56 /*
57 * Saved cp0 registers
58 */
59 printf("epc : %0*lx (text %0*lx)\n", field, regs->cp0_epc,
60 field, regs->cp0_epc - gd->reloc_off);
61 printf("ra : %0*lx (text %0*lx)\n", field, regs->regs[31],
62 field, regs->regs[31] - gd->reloc_off);
63
64 printf("Status: %08x\n", (uint32_t) regs->cp0_status);
65
66 exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
67 printf("Cause : %08x (ExcCode %02x)\n", cause, exccode);
68
69 if (1 <= exccode && exccode <= 5)
70 printf("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
71
72 printf("PrId : %08x\n", read_c0_prid());
73 }
74
do_reserved(const struct pt_regs * regs)75 void do_reserved(const struct pt_regs *regs)
76 {
77 puts("\nOoops:\n");
78 show_regs(regs);
79 hang();
80 }
81
do_ejtag_debug(const struct pt_regs * regs)82 void do_ejtag_debug(const struct pt_regs *regs)
83 {
84 const int field = 2 * sizeof(unsigned long);
85 unsigned long depc;
86 unsigned int debug;
87
88 depc = read_c0_depc();
89 debug = read_c0_debug();
90
91 printf("SDBBP EJTAG debug exception: c0_depc = %0*lx, DEBUG = %08x\n",
92 field, depc, debug);
93 }
94
set_handler(unsigned long offset,void * addr,unsigned long size)95 static void set_handler(unsigned long offset, void *addr, unsigned long size)
96 {
97 unsigned long ebase = gd->irq_sp;
98
99 memcpy((void *)(ebase + offset), addr, size);
100 flush_cache(ebase + offset, size);
101 }
102
trap_init(ulong reloc_addr)103 static void trap_init(ulong reloc_addr)
104 {
105 unsigned long ebase = gd->irq_sp;
106
107 set_handler(0x180, &except_vec3_generic, 0x80);
108 set_handler(0x280, &except_vec_ejtag_debug, 0x80);
109
110 saved_ebase = read_c0_ebase() & 0xfffff000;
111
112 /* Set WG bit on Octeon to enable writing to bits 63:30 */
113 if (IS_ENABLED(CONFIG_ARCH_OCTEON))
114 ebase |= MIPS_EBASE_WG;
115
116 write_c0_ebase(ebase);
117 clear_c0_status(ST0_BEV);
118 execution_hazard_barrier();
119 }
120
trap_restore(void)121 void trap_restore(void)
122 {
123 set_c0_status(ST0_BEV);
124 execution_hazard_barrier();
125
126 #ifdef CONFIG_OVERRIDE_EXCEPTION_VECTOR_BASE
127 write_c0_ebase(CONFIG_NEW_EXCEPTION_VECTOR_BASE & 0xfffff000);
128 #else
129 write_c0_ebase(saved_ebase);
130 #endif
131
132 clear_c0_status(ST0_BEV);
133 execution_hazard_barrier();
134 }
135
arch_initr_trap(void)136 int arch_initr_trap(void)
137 {
138 trap_init(CONFIG_SYS_SDRAM_BASE);
139
140 return 0;
141 }
142