1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for Compulab CM-T335 board
4 *
5 * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
6 *
7 * Author: Ilya Ledvich <ilya@compulab.co.il>
8 */
9
10 #include <common.h>
11 #include <env.h>
12 #include <errno.h>
13 #include <miiphy.h>
14 #include <net.h>
15 #include <status_led.h>
16 #include <cpsw.h>
17 #include <asm/global_data.h>
18 #include <linux/delay.h>
19
20 #include <asm/arch/sys_proto.h>
21 #include <asm/arch/hardware_am33xx.h>
22 #include <asm/io.h>
23 #include <asm/gpio.h>
24
25 #include "../common/eeprom.h"
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 /*
30 * Basic board specific setup. Pinmux has been handled already.
31 */
board_init(void)32 int board_init(void)
33 {
34 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
35
36 gpmc_init();
37
38 #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
39 status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
40 #endif
41 return 0;
42 }
43
44 #if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
cpsw_control(int enabled)45 static void cpsw_control(int enabled)
46 {
47 /* VTP can be added here */
48 return;
49 }
50
51 static struct cpsw_slave_data cpsw_slave = {
52 .slave_reg_ofs = 0x208,
53 .sliver_reg_ofs = 0xd80,
54 .phy_addr = 0,
55 .phy_if = PHY_INTERFACE_MODE_RGMII,
56 };
57
58 static struct cpsw_platform_data cpsw_data = {
59 .mdio_base = CPSW_MDIO_BASE,
60 .cpsw_base = CPSW_BASE,
61 .mdio_div = 0xff,
62 .channels = 8,
63 .cpdma_reg_ofs = 0x800,
64 .slaves = 1,
65 .slave_data = &cpsw_slave,
66 .ale_reg_ofs = 0xd00,
67 .ale_entries = 1024,
68 .host_port_reg_ofs = 0x108,
69 .hw_stats_reg_ofs = 0x900,
70 .bd_ram_ofs = 0x2000,
71 .mac_control = (1 << 5),
72 .control = cpsw_control,
73 .host_port_num = 0,
74 .version = CPSW_CTRL_VERSION_2,
75 };
76
77 /* PHY reset GPIO */
78 #define GPIO_PHY_RST GPIO_PIN(3, 7)
79
board_phy_init(void)80 static void board_phy_init(void)
81 {
82 gpio_request(GPIO_PHY_RST, "phy_rst");
83 gpio_direction_output(GPIO_PHY_RST, 0);
84 mdelay(2);
85 gpio_set_value(GPIO_PHY_RST, 1);
86 mdelay(2);
87 }
88
get_efuse_mac_addr(uchar * enetaddr)89 static void get_efuse_mac_addr(uchar *enetaddr)
90 {
91 uint32_t mac_hi, mac_lo;
92 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
93
94 mac_lo = readl(&cdev->macid0l);
95 mac_hi = readl(&cdev->macid0h);
96 enetaddr[0] = mac_hi & 0xFF;
97 enetaddr[1] = (mac_hi & 0xFF00) >> 8;
98 enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
99 enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
100 enetaddr[4] = mac_lo & 0xFF;
101 enetaddr[5] = (mac_lo & 0xFF00) >> 8;
102 }
103
104 /*
105 * Routine: handle_mac_address
106 * Description: prepare MAC address for on-board Ethernet.
107 */
handle_mac_address(void)108 static int handle_mac_address(void)
109 {
110 uchar enetaddr[6];
111 int rv;
112
113 rv = eth_env_get_enetaddr("ethaddr", enetaddr);
114 if (rv)
115 return 0;
116
117 rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
118 if (rv)
119 get_efuse_mac_addr(enetaddr);
120
121 if (!is_valid_ethaddr(enetaddr))
122 return -1;
123
124 return eth_env_set_enetaddr("ethaddr", enetaddr);
125 }
126
127 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
128 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
129 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
130 #define AR8051_RGMII_TX_CLK_DLY 0x100
131
board_eth_init(struct bd_info * bis)132 int board_eth_init(struct bd_info *bis)
133 {
134 int rv, n = 0;
135 const char *devname;
136 struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
137
138 rv = handle_mac_address();
139 if (rv)
140 printf("No MAC address found!\n");
141
142 writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
143
144 board_phy_init();
145
146 rv = cpsw_register(&cpsw_data);
147 if (rv < 0)
148 printf("Error %d registering CPSW switch\n", rv);
149 else
150 n += rv;
151
152 /*
153 * CPSW RGMII Internal Delay Mode is not supported in all PVT
154 * operating points. So we must set the TX clock delay feature
155 * in the AR8051 PHY. Since we only support a single ethernet
156 * device, we only do this for the first instance.
157 */
158 devname = miiphy_get_current_dev();
159
160 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
161 AR8051_DEBUG_RGMII_CLK_DLY_REG);
162 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
163 AR8051_RGMII_TX_CLK_DLY);
164 return n;
165 }
166 #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
167