1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <dm/device-internal.h>
10 #include <linux/clk-provider.h>
11
clk_fixed_rate_get_rate(struct clk * clk)12 static ulong clk_fixed_rate_get_rate(struct clk *clk)
13 {
14 return to_clk_fixed_rate(clk->dev)->fixed_rate;
15 }
16
17 /* avoid clk_enable() return -ENOSYS */
dummy_enable(struct clk * clk)18 static int dummy_enable(struct clk *clk)
19 {
20 return 0;
21 }
22
23 const struct clk_ops clk_fixed_rate_ops = {
24 .get_rate = clk_fixed_rate_get_rate,
25 .enable = dummy_enable,
26 };
27
clk_fixed_rate_ofdata_to_plat_(struct udevice * dev,struct clk_fixed_rate * plat)28 void clk_fixed_rate_ofdata_to_plat_(struct udevice *dev,
29 struct clk_fixed_rate *plat)
30 {
31 struct clk *clk = &plat->clk;
32 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
33 plat->fixed_rate = dev_read_u32_default(dev, "clock-frequency", 0);
34 #endif
35 /* Make fixed rate clock accessible from higher level struct clk */
36 /* FIXME: This is not allowed */
37 dev_set_uclass_priv(dev, clk);
38
39 clk->dev = dev;
40 clk->enable_count = 0;
41 }
42
clk_fixed_rate_of_to_plat(struct udevice * dev)43 static int clk_fixed_rate_of_to_plat(struct udevice *dev)
44 {
45 clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
46
47 return 0;
48 }
49
50 static const struct udevice_id clk_fixed_rate_match[] = {
51 {
52 .compatible = "fixed-clock",
53 },
54 { /* sentinel */ }
55 };
56
57 U_BOOT_DRIVER(fixed_clock) = {
58 .name = "fixed_clock",
59 .id = UCLASS_CLK,
60 .of_match = clk_fixed_rate_match,
61 .of_to_plat = clk_fixed_rate_of_to_plat,
62 .plat_auto = sizeof(struct clk_fixed_rate),
63 .ops = &clk_fixed_rate_ops,
64 .flags = DM_FLAG_PRE_RELOC,
65 };
66