1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2010-2016 Freescale Semiconductor, Inc.
4 * Copyright 2017-2018 NXP Semiconductor
5 */
6
7 /*
8 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
9 * Based on code from spd_sdram.c
10 * Author: James Yang [at freescale.com]
11 * York Sun [at freescale.com]
12 */
13
14 #include <common.h>
15 #include <cli.h>
16 #include <command.h>
17 #include <env.h>
18 #include <log.h>
19 #include <asm/bitops.h>
20 #include <linux/ctype.h>
21 #include <asm/types.h>
22 #include <asm/io.h>
23
24 #include <fsl_ddr_sdram.h>
25 #include <fsl_ddr.h>
26
27 /* Option parameter Structures */
28 struct options_string {
29 const char *option_name;
30 size_t offset;
31 unsigned int size;
32 const char printhex;
33 };
34
picos_to_mhz(unsigned int picos)35 static unsigned int picos_to_mhz(unsigned int picos)
36 {
37 return 1000000 / picos;
38 }
39
print_option_table(const struct options_string * table,int table_size,const void * base)40 static void print_option_table(const struct options_string *table,
41 int table_size,
42 const void *base)
43 {
44 unsigned int i;
45 unsigned int *ptr;
46 unsigned long long *ptr_l;
47
48 for (i = 0; i < table_size; i++) {
49 switch (table[i].size) {
50 case 4:
51 ptr = (unsigned int *) (base + table[i].offset);
52 if (table[i].printhex) {
53 printf("%s = 0x%08X\n",
54 table[i].option_name, *ptr);
55 } else {
56 printf("%s = %u\n",
57 table[i].option_name, *ptr);
58 }
59 break;
60 case 8:
61 ptr_l = (unsigned long long *) (base + table[i].offset);
62 printf("%s = %llu\n",
63 table[i].option_name, *ptr_l);
64 break;
65 default:
66 printf("Unrecognized size!\n");
67 break;
68 }
69 }
70 }
71
handle_option_table(const struct options_string * table,int table_size,void * base,const char * opt,const char * val)72 static int handle_option_table(const struct options_string *table,
73 int table_size,
74 void *base,
75 const char *opt,
76 const char *val)
77 {
78 unsigned int i;
79 unsigned int value, *ptr;
80 unsigned long long value_l, *ptr_l;
81
82 for (i = 0; i < table_size; i++) {
83 if (strcmp(table[i].option_name, opt) != 0)
84 continue;
85 switch (table[i].size) {
86 case 4:
87 value = simple_strtoul(val, NULL, 0);
88 ptr = base + table[i].offset;
89 *ptr = value;
90 break;
91 case 8:
92 value_l = simple_strtoull(val, NULL, 0);
93 ptr_l = base + table[i].offset;
94 *ptr_l = value_l;
95 break;
96 default:
97 printf("Unrecognized size!\n");
98 break;
99 }
100 return 1;
101 }
102
103 return 0;
104 }
105
fsl_ddr_generic_edit(void * pdata,void * pend,unsigned int element_size,unsigned int element_num,unsigned int value)106 static void fsl_ddr_generic_edit(void *pdata,
107 void *pend,
108 unsigned int element_size,
109 unsigned int element_num,
110 unsigned int value)
111 {
112 char *pcdata = (char *)pdata; /* BIG ENDIAN ONLY */
113
114 pcdata += element_num * element_size;
115 if ((pcdata + element_size) > (char *) pend) {
116 printf("trying to write past end of data\n");
117 return;
118 }
119
120 switch (element_size) {
121 case 1:
122 __raw_writeb(value, pcdata);
123 break;
124 case 2:
125 __raw_writew(value, pcdata);
126 break;
127 case 4:
128 __raw_writel(value, pcdata);
129 break;
130 default:
131 printf("unexpected element size %u\n", element_size);
132 break;
133 }
134 }
135
fsl_ddr_spd_edit(fsl_ddr_info_t * pinfo,unsigned int ctrl_num,unsigned int dimm_num,unsigned int element_num,unsigned int value)136 static void fsl_ddr_spd_edit(fsl_ddr_info_t *pinfo,
137 unsigned int ctrl_num,
138 unsigned int dimm_num,
139 unsigned int element_num,
140 unsigned int value)
141 {
142 generic_spd_eeprom_t *pspd;
143
144 pspd = &(pinfo->spd_installed_dimms[ctrl_num][dimm_num]);
145 fsl_ddr_generic_edit(pspd, pspd + 1, 1, element_num, value);
146 }
147
148 #define COMMON_TIMING(x) {#x, offsetof(common_timing_params_t, x), \
149 sizeof((common_timing_params_t *)0)->x, 0}
150
lowest_common_dimm_parameters_edit(fsl_ddr_info_t * pinfo,unsigned int ctrl_num,const char * optname_str,const char * value_str)151 static void lowest_common_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
152 unsigned int ctrl_num,
153 const char *optname_str,
154 const char *value_str)
155 {
156 common_timing_params_t *p = &pinfo->common_timing_params[ctrl_num];
157
158 static const struct options_string options[] = {
159 COMMON_TIMING(tckmin_x_ps),
160 COMMON_TIMING(tckmax_ps),
161 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
162 COMMON_TIMING(taamin_ps),
163 #endif
164 COMMON_TIMING(trcd_ps),
165 COMMON_TIMING(trp_ps),
166 COMMON_TIMING(tras_ps),
167
168 #ifdef CONFIG_SYS_FSL_DDR4
169 COMMON_TIMING(trfc1_ps),
170 COMMON_TIMING(trfc2_ps),
171 COMMON_TIMING(trfc4_ps),
172 COMMON_TIMING(trrds_ps),
173 COMMON_TIMING(trrdl_ps),
174 COMMON_TIMING(tccdl_ps),
175 COMMON_TIMING(trfc_slr_ps),
176 #else
177 COMMON_TIMING(twtr_ps),
178 COMMON_TIMING(trfc_ps),
179 COMMON_TIMING(trrd_ps),
180 COMMON_TIMING(trtp_ps),
181 #endif
182 COMMON_TIMING(twr_ps),
183 COMMON_TIMING(trc_ps),
184 COMMON_TIMING(refresh_rate_ps),
185 COMMON_TIMING(extended_op_srt),
186 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
187 COMMON_TIMING(tis_ps),
188 COMMON_TIMING(tih_ps),
189 COMMON_TIMING(tds_ps),
190 COMMON_TIMING(tdh_ps),
191 COMMON_TIMING(tdqsq_max_ps),
192 COMMON_TIMING(tqhs_ps),
193 #endif
194 COMMON_TIMING(ndimms_present),
195 COMMON_TIMING(lowest_common_spd_caslat),
196 COMMON_TIMING(highest_common_derated_caslat),
197 COMMON_TIMING(additive_latency),
198 COMMON_TIMING(all_dimms_burst_lengths_bitmask),
199 COMMON_TIMING(all_dimms_registered),
200 COMMON_TIMING(all_dimms_unbuffered),
201 COMMON_TIMING(all_dimms_ecc_capable),
202 COMMON_TIMING(total_mem),
203 COMMON_TIMING(base_address),
204 };
205 static const unsigned int n_opts = ARRAY_SIZE(options);
206
207 if (handle_option_table(options, n_opts, p, optname_str, value_str))
208 return;
209
210 printf("Error: couldn't find option string %s\n", optname_str);
211 }
212
213 #define DIMM_PARM(x) {#x, offsetof(dimm_params_t, x), \
214 sizeof((dimm_params_t *)0)->x, 0}
215 #define DIMM_PARM_HEX(x) {#x, offsetof(dimm_params_t, x), \
216 sizeof((dimm_params_t *)0)->x, 1}
217
fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t * pinfo,unsigned int ctrl_num,unsigned int dimm_num,const char * optname_str,const char * value_str)218 static void fsl_ddr_dimm_parameters_edit(fsl_ddr_info_t *pinfo,
219 unsigned int ctrl_num,
220 unsigned int dimm_num,
221 const char *optname_str,
222 const char *value_str)
223 {
224 dimm_params_t *p = &(pinfo->dimm_params[ctrl_num][dimm_num]);
225
226 static const struct options_string options[] = {
227 DIMM_PARM(n_ranks),
228 DIMM_PARM(data_width),
229 DIMM_PARM(primary_sdram_width),
230 DIMM_PARM(ec_sdram_width),
231 DIMM_PARM(package_3ds),
232 DIMM_PARM(registered_dimm),
233 DIMM_PARM(mirrored_dimm),
234 DIMM_PARM(device_width),
235
236 DIMM_PARM(n_row_addr),
237 DIMM_PARM(n_col_addr),
238 DIMM_PARM(edc_config),
239 #ifdef CONFIG_SYS_FSL_DDR4
240 DIMM_PARM(bank_addr_bits),
241 DIMM_PARM(bank_group_bits),
242 DIMM_PARM_HEX(die_density),
243 #else
244 DIMM_PARM(n_banks_per_sdram_device),
245 #endif
246 DIMM_PARM(burst_lengths_bitmask),
247
248 DIMM_PARM(tckmin_x_ps),
249 DIMM_PARM(tckmin_x_minus_1_ps),
250 DIMM_PARM(tckmin_x_minus_2_ps),
251 DIMM_PARM(tckmax_ps),
252
253 DIMM_PARM(caslat_x),
254 DIMM_PARM(caslat_x_minus_1),
255 DIMM_PARM(caslat_x_minus_2),
256
257 DIMM_PARM(caslat_lowest_derated),
258
259 DIMM_PARM(trcd_ps),
260 DIMM_PARM(trp_ps),
261 DIMM_PARM(tras_ps),
262 #ifdef CONFIG_SYS_FSL_DDR4
263 DIMM_PARM(trfc1_ps),
264 DIMM_PARM(trfc2_ps),
265 DIMM_PARM(trfc4_ps),
266 DIMM_PARM(trrds_ps),
267 DIMM_PARM(trrdl_ps),
268 DIMM_PARM(tccdl_ps),
269 DIMM_PARM(trfc_slr_ps),
270 #else
271 DIMM_PARM(twr_ps),
272 DIMM_PARM(twtr_ps),
273 DIMM_PARM(trfc_ps),
274 DIMM_PARM(trrd_ps),
275 DIMM_PARM(trtp_ps),
276 #endif
277 DIMM_PARM(trc_ps),
278 DIMM_PARM(refresh_rate_ps),
279 DIMM_PARM(extended_op_srt),
280
281 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
282 DIMM_PARM(tis_ps),
283 DIMM_PARM(tih_ps),
284 DIMM_PARM(tds_ps),
285 DIMM_PARM(tdh_ps),
286 DIMM_PARM(tdqsq_max_ps),
287 DIMM_PARM(tqhs_ps),
288 #endif
289 #ifdef CONFIG_SYS_FSL_DDR4
290 DIMM_PARM_HEX(dq_mapping[0]),
291 DIMM_PARM_HEX(dq_mapping[1]),
292 DIMM_PARM_HEX(dq_mapping[2]),
293 DIMM_PARM_HEX(dq_mapping[3]),
294 DIMM_PARM_HEX(dq_mapping[4]),
295 DIMM_PARM_HEX(dq_mapping[5]),
296 DIMM_PARM_HEX(dq_mapping[6]),
297 DIMM_PARM_HEX(dq_mapping[7]),
298 DIMM_PARM_HEX(dq_mapping[8]),
299 DIMM_PARM_HEX(dq_mapping[9]),
300 DIMM_PARM_HEX(dq_mapping[10]),
301 DIMM_PARM_HEX(dq_mapping[11]),
302 DIMM_PARM_HEX(dq_mapping[12]),
303 DIMM_PARM_HEX(dq_mapping[13]),
304 DIMM_PARM_HEX(dq_mapping[14]),
305 DIMM_PARM_HEX(dq_mapping[15]),
306 DIMM_PARM_HEX(dq_mapping[16]),
307 DIMM_PARM_HEX(dq_mapping[17]),
308 DIMM_PARM(dq_mapping_ors),
309 #endif
310 DIMM_PARM(rank_density),
311 DIMM_PARM(capacity),
312 DIMM_PARM(base_address),
313 };
314
315 static const unsigned int n_opts = ARRAY_SIZE(options);
316
317 if (handle_option_table(options, n_opts, p, optname_str, value_str))
318 return;
319
320 printf("couldn't find option string %s\n", optname_str);
321 }
322
print_dimm_parameters(const dimm_params_t * pdimm)323 static void print_dimm_parameters(const dimm_params_t *pdimm)
324 {
325 static const struct options_string options[] = {
326 DIMM_PARM(n_ranks),
327 DIMM_PARM(data_width),
328 DIMM_PARM(primary_sdram_width),
329 DIMM_PARM(ec_sdram_width),
330 DIMM_PARM(package_3ds),
331 DIMM_PARM(registered_dimm),
332 DIMM_PARM(mirrored_dimm),
333 DIMM_PARM(device_width),
334
335 DIMM_PARM(n_row_addr),
336 DIMM_PARM(n_col_addr),
337 DIMM_PARM(edc_config),
338 #ifdef CONFIG_SYS_FSL_DDR4
339 DIMM_PARM(bank_addr_bits),
340 DIMM_PARM(bank_group_bits),
341 DIMM_PARM_HEX(die_density),
342 #else
343 DIMM_PARM(n_banks_per_sdram_device),
344 #endif
345
346 DIMM_PARM(tckmin_x_ps),
347 DIMM_PARM(tckmin_x_minus_1_ps),
348 DIMM_PARM(tckmin_x_minus_2_ps),
349 DIMM_PARM(tckmax_ps),
350
351 DIMM_PARM(caslat_x),
352 DIMM_PARM_HEX(caslat_x),
353 DIMM_PARM(taa_ps),
354 DIMM_PARM(caslat_x_minus_1),
355 DIMM_PARM(caslat_x_minus_2),
356 DIMM_PARM(caslat_lowest_derated),
357
358 DIMM_PARM(trcd_ps),
359 DIMM_PARM(trp_ps),
360 DIMM_PARM(tras_ps),
361 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
362 DIMM_PARM(tfaw_ps),
363 #endif
364 #ifdef CONFIG_SYS_FSL_DDR4
365 DIMM_PARM(trfc1_ps),
366 DIMM_PARM(trfc2_ps),
367 DIMM_PARM(trfc4_ps),
368 DIMM_PARM(trrds_ps),
369 DIMM_PARM(trrdl_ps),
370 DIMM_PARM(tccdl_ps),
371 DIMM_PARM(trfc_slr_ps),
372 #else
373 DIMM_PARM(twr_ps),
374 DIMM_PARM(twtr_ps),
375 DIMM_PARM(trfc_ps),
376 DIMM_PARM(trrd_ps),
377 DIMM_PARM(trtp_ps),
378 #endif
379 DIMM_PARM(trc_ps),
380 DIMM_PARM(refresh_rate_ps),
381
382 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
383 DIMM_PARM(tis_ps),
384 DIMM_PARM(tih_ps),
385 DIMM_PARM(tds_ps),
386 DIMM_PARM(tdh_ps),
387 DIMM_PARM(tdqsq_max_ps),
388 DIMM_PARM(tqhs_ps),
389 #endif
390 #ifdef CONFIG_SYS_FSL_DDR4
391 DIMM_PARM_HEX(dq_mapping[0]),
392 DIMM_PARM_HEX(dq_mapping[1]),
393 DIMM_PARM_HEX(dq_mapping[2]),
394 DIMM_PARM_HEX(dq_mapping[3]),
395 DIMM_PARM_HEX(dq_mapping[4]),
396 DIMM_PARM_HEX(dq_mapping[5]),
397 DIMM_PARM_HEX(dq_mapping[6]),
398 DIMM_PARM_HEX(dq_mapping[7]),
399 DIMM_PARM_HEX(dq_mapping[8]),
400 DIMM_PARM_HEX(dq_mapping[9]),
401 DIMM_PARM_HEX(dq_mapping[10]),
402 DIMM_PARM_HEX(dq_mapping[11]),
403 DIMM_PARM_HEX(dq_mapping[12]),
404 DIMM_PARM_HEX(dq_mapping[13]),
405 DIMM_PARM_HEX(dq_mapping[14]),
406 DIMM_PARM_HEX(dq_mapping[15]),
407 DIMM_PARM_HEX(dq_mapping[16]),
408 DIMM_PARM_HEX(dq_mapping[17]),
409 DIMM_PARM(dq_mapping_ors),
410 #endif
411 };
412 static const unsigned int n_opts = ARRAY_SIZE(options);
413
414 if (pdimm->n_ranks == 0) {
415 printf("DIMM not present\n");
416 return;
417 }
418 printf("DIMM organization parameters:\n");
419 printf("module part name = %s\n", pdimm->mpart);
420 printf("rank_density = %llu bytes (%llu megabytes)\n",
421 pdimm->rank_density, pdimm->rank_density / 0x100000);
422 printf("capacity = %llu bytes (%llu megabytes)\n",
423 pdimm->capacity, pdimm->capacity / 0x100000);
424 printf("burst_lengths_bitmask = %02X\n",
425 pdimm->burst_lengths_bitmask);
426 printf("base_addresss = %llu (%08llX %08llX)\n",
427 pdimm->base_address,
428 (pdimm->base_address >> 32),
429 pdimm->base_address & 0xFFFFFFFF);
430 print_option_table(options, n_opts, pdimm);
431 }
432
print_lowest_common_dimm_parameters(const common_timing_params_t * plcd_dimm_params)433 static void print_lowest_common_dimm_parameters(
434 const common_timing_params_t *plcd_dimm_params)
435 {
436 static const struct options_string options[] = {
437 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
438 COMMON_TIMING(taamin_ps),
439 #endif
440 COMMON_TIMING(trcd_ps),
441 COMMON_TIMING(trp_ps),
442 COMMON_TIMING(tras_ps),
443 #ifdef CONFIG_SYS_FSL_DDR4
444 COMMON_TIMING(trfc1_ps),
445 COMMON_TIMING(trfc2_ps),
446 COMMON_TIMING(trfc4_ps),
447 COMMON_TIMING(trrds_ps),
448 COMMON_TIMING(trrdl_ps),
449 COMMON_TIMING(tccdl_ps),
450 COMMON_TIMING(trfc_slr_ps),
451 #else
452 COMMON_TIMING(twtr_ps),
453 COMMON_TIMING(trfc_ps),
454 COMMON_TIMING(trrd_ps),
455 COMMON_TIMING(trtp_ps),
456 #endif
457 COMMON_TIMING(twr_ps),
458 COMMON_TIMING(trc_ps),
459 COMMON_TIMING(refresh_rate_ps),
460 COMMON_TIMING(extended_op_srt),
461 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
462 COMMON_TIMING(tis_ps),
463 COMMON_TIMING(tih_ps),
464 COMMON_TIMING(tds_ps),
465 COMMON_TIMING(tdh_ps),
466 COMMON_TIMING(tdqsq_max_ps),
467 COMMON_TIMING(tqhs_ps),
468 #endif
469 COMMON_TIMING(lowest_common_spd_caslat),
470 COMMON_TIMING(highest_common_derated_caslat),
471 COMMON_TIMING(additive_latency),
472 COMMON_TIMING(ndimms_present),
473 COMMON_TIMING(all_dimms_registered),
474 COMMON_TIMING(all_dimms_unbuffered),
475 COMMON_TIMING(all_dimms_ecc_capable),
476 };
477 static const unsigned int n_opts = ARRAY_SIZE(options);
478
479 /* Clock frequencies */
480 printf("tckmin_x_ps = %u (%u MHz)\n",
481 plcd_dimm_params->tckmin_x_ps,
482 picos_to_mhz(plcd_dimm_params->tckmin_x_ps));
483 printf("tckmax_ps = %u (%u MHz)\n",
484 plcd_dimm_params->tckmax_ps,
485 picos_to_mhz(plcd_dimm_params->tckmax_ps));
486 printf("all_dimms_burst_lengths_bitmask = %02X\n",
487 plcd_dimm_params->all_dimms_burst_lengths_bitmask);
488
489 print_option_table(options, n_opts, plcd_dimm_params);
490
491 printf("total_mem = %llu (%llu megabytes)\n",
492 plcd_dimm_params->total_mem,
493 plcd_dimm_params->total_mem / 0x100000);
494 printf("base_address = %llu (%llu megabytes)\n",
495 plcd_dimm_params->base_address,
496 plcd_dimm_params->base_address / 0x100000);
497 }
498
499 #define CTRL_OPTIONS(x) {#x, offsetof(memctl_options_t, x), \
500 sizeof((memctl_options_t *)0)->x, 0}
501 #define CTRL_OPTIONS_CS(x, y) {"cs" #x "_" #y, \
502 offsetof(memctl_options_t, cs_local_opts[x].y), \
503 sizeof((memctl_options_t *)0)->cs_local_opts[x].y, 0}
504
fsl_ddr_options_edit(fsl_ddr_info_t * pinfo,unsigned int ctl_num,const char * optname_str,const char * value_str)505 static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo,
506 unsigned int ctl_num,
507 const char *optname_str,
508 const char *value_str)
509 {
510 memctl_options_t *p = &(pinfo->memctl_opts[ctl_num]);
511 /*
512 * This array all on the stack and *computed* each time this
513 * function is rung.
514 */
515 static const struct options_string options[] = {
516 CTRL_OPTIONS_CS(0, odt_rd_cfg),
517 CTRL_OPTIONS_CS(0, odt_wr_cfg),
518 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
519 CTRL_OPTIONS_CS(1, odt_rd_cfg),
520 CTRL_OPTIONS_CS(1, odt_wr_cfg),
521 #endif
522 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
523 CTRL_OPTIONS_CS(2, odt_rd_cfg),
524 CTRL_OPTIONS_CS(2, odt_wr_cfg),
525 #endif
526 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
527 CTRL_OPTIONS_CS(3, odt_rd_cfg),
528 CTRL_OPTIONS_CS(3, odt_wr_cfg),
529 #endif
530 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
531 CTRL_OPTIONS_CS(0, odt_rtt_norm),
532 CTRL_OPTIONS_CS(0, odt_rtt_wr),
533 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
534 CTRL_OPTIONS_CS(1, odt_rtt_norm),
535 CTRL_OPTIONS_CS(1, odt_rtt_wr),
536 #endif
537 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
538 CTRL_OPTIONS_CS(2, odt_rtt_norm),
539 CTRL_OPTIONS_CS(2, odt_rtt_wr),
540 #endif
541 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
542 CTRL_OPTIONS_CS(3, odt_rtt_norm),
543 CTRL_OPTIONS_CS(3, odt_rtt_wr),
544 #endif
545 #endif
546 CTRL_OPTIONS(memctl_interleaving),
547 CTRL_OPTIONS(memctl_interleaving_mode),
548 CTRL_OPTIONS(ba_intlv_ctl),
549 CTRL_OPTIONS(ecc_mode),
550 CTRL_OPTIONS(ecc_init_using_memctl),
551 CTRL_OPTIONS(dqs_config),
552 CTRL_OPTIONS(self_refresh_in_sleep),
553 CTRL_OPTIONS(dynamic_power),
554 CTRL_OPTIONS(data_bus_width),
555 CTRL_OPTIONS(burst_length),
556 CTRL_OPTIONS(cas_latency_override),
557 CTRL_OPTIONS(cas_latency_override_value),
558 CTRL_OPTIONS(use_derated_caslat),
559 CTRL_OPTIONS(additive_latency_override),
560 CTRL_OPTIONS(additive_latency_override_value),
561 CTRL_OPTIONS(clk_adjust),
562 CTRL_OPTIONS(cpo_override),
563 CTRL_OPTIONS(write_data_delay),
564 CTRL_OPTIONS(half_strength_driver_enable),
565
566 /*
567 * These can probably be changed to 2T_EN and 3T_EN
568 * (using a leading numerical character) without problem
569 */
570 CTRL_OPTIONS(twot_en),
571 CTRL_OPTIONS(threet_en),
572 CTRL_OPTIONS(mirrored_dimm),
573 CTRL_OPTIONS(ap_en),
574 CTRL_OPTIONS(x4_en),
575 CTRL_OPTIONS(package_3ds),
576 CTRL_OPTIONS(bstopre),
577 CTRL_OPTIONS(wrlvl_override),
578 CTRL_OPTIONS(wrlvl_sample),
579 CTRL_OPTIONS(wrlvl_start),
580 CTRL_OPTIONS(cswl_override),
581 CTRL_OPTIONS(rcw_override),
582 CTRL_OPTIONS(rcw_1),
583 CTRL_OPTIONS(rcw_2),
584 CTRL_OPTIONS(rcw_3),
585 CTRL_OPTIONS(ddr_cdr1),
586 CTRL_OPTIONS(ddr_cdr2),
587 CTRL_OPTIONS(tfaw_window_four_activates_ps),
588 CTRL_OPTIONS(trwt_override),
589 CTRL_OPTIONS(trwt),
590 CTRL_OPTIONS(rtt_override),
591 CTRL_OPTIONS(rtt_override_value),
592 CTRL_OPTIONS(rtt_wr_override_value),
593 };
594
595 static const unsigned int n_opts = ARRAY_SIZE(options);
596
597 if (handle_option_table(options, n_opts, p,
598 optname_str, value_str))
599 return;
600
601 printf("couldn't find option string %s\n", optname_str);
602 }
603
604 #define CFG_REGS(x) {#x, offsetof(fsl_ddr_cfg_regs_t, x), \
605 sizeof((fsl_ddr_cfg_regs_t *)0)->x, 1}
606 #define CFG_REGS_CS(x, y) {"cs" #x "_" #y, \
607 offsetof(fsl_ddr_cfg_regs_t, cs[x].y), \
608 sizeof((fsl_ddr_cfg_regs_t *)0)->cs[x].y, 1}
609
print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t * ddr)610 static void print_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
611 {
612 unsigned int i;
613 static const struct options_string options[] = {
614 CFG_REGS_CS(0, bnds),
615 CFG_REGS_CS(0, config),
616 CFG_REGS_CS(0, config_2),
617 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
618 CFG_REGS_CS(1, bnds),
619 CFG_REGS_CS(1, config),
620 CFG_REGS_CS(1, config_2),
621 #endif
622 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
623 CFG_REGS_CS(2, bnds),
624 CFG_REGS_CS(2, config),
625 CFG_REGS_CS(2, config_2),
626 #endif
627 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
628 CFG_REGS_CS(3, bnds),
629 CFG_REGS_CS(3, config),
630 CFG_REGS_CS(3, config_2),
631 #endif
632 CFG_REGS(timing_cfg_3),
633 CFG_REGS(timing_cfg_0),
634 CFG_REGS(timing_cfg_1),
635 CFG_REGS(timing_cfg_2),
636 CFG_REGS(ddr_sdram_cfg),
637 CFG_REGS(ddr_sdram_cfg_2),
638 CFG_REGS(ddr_sdram_cfg_3),
639 CFG_REGS(ddr_sdram_mode),
640 CFG_REGS(ddr_sdram_mode_2),
641 CFG_REGS(ddr_sdram_mode_3),
642 CFG_REGS(ddr_sdram_mode_4),
643 CFG_REGS(ddr_sdram_mode_5),
644 CFG_REGS(ddr_sdram_mode_6),
645 CFG_REGS(ddr_sdram_mode_7),
646 CFG_REGS(ddr_sdram_mode_8),
647 #ifdef CONFIG_SYS_FSL_DDR4
648 CFG_REGS(ddr_sdram_mode_9),
649 CFG_REGS(ddr_sdram_mode_10),
650 CFG_REGS(ddr_sdram_mode_11),
651 CFG_REGS(ddr_sdram_mode_12),
652 CFG_REGS(ddr_sdram_mode_13),
653 CFG_REGS(ddr_sdram_mode_14),
654 CFG_REGS(ddr_sdram_mode_15),
655 CFG_REGS(ddr_sdram_mode_16),
656 #endif
657 CFG_REGS(ddr_sdram_interval),
658 CFG_REGS(ddr_data_init),
659 CFG_REGS(ddr_sdram_clk_cntl),
660 CFG_REGS(ddr_init_addr),
661 CFG_REGS(ddr_init_ext_addr),
662 CFG_REGS(timing_cfg_4),
663 CFG_REGS(timing_cfg_5),
664 #ifdef CONFIG_SYS_FSL_DDR4
665 CFG_REGS(timing_cfg_6),
666 CFG_REGS(timing_cfg_7),
667 CFG_REGS(timing_cfg_8),
668 CFG_REGS(timing_cfg_9),
669 #endif
670 CFG_REGS(ddr_zq_cntl),
671 CFG_REGS(ddr_wrlvl_cntl),
672 CFG_REGS(ddr_wrlvl_cntl_2),
673 CFG_REGS(ddr_wrlvl_cntl_3),
674 CFG_REGS(ddr_sr_cntr),
675 CFG_REGS(ddr_sdram_rcw_1),
676 CFG_REGS(ddr_sdram_rcw_2),
677 CFG_REGS(ddr_sdram_rcw_3),
678 CFG_REGS(ddr_cdr1),
679 CFG_REGS(ddr_cdr2),
680 CFG_REGS(dq_map_0),
681 CFG_REGS(dq_map_1),
682 CFG_REGS(dq_map_2),
683 CFG_REGS(dq_map_3),
684 CFG_REGS(err_disable),
685 CFG_REGS(err_int_en),
686 CFG_REGS(ddr_eor),
687 };
688 static const unsigned int n_opts = ARRAY_SIZE(options);
689
690 print_option_table(options, n_opts, ddr);
691
692 for (i = 0; i < 64; i++)
693 printf("debug_%02d = 0x%08X\n", i+1, ddr->debug[i]);
694 }
695
fsl_ddr_regs_edit(fsl_ddr_info_t * pinfo,unsigned int ctrl_num,const char * regname,const char * value_str)696 static void fsl_ddr_regs_edit(fsl_ddr_info_t *pinfo,
697 unsigned int ctrl_num,
698 const char *regname,
699 const char *value_str)
700 {
701 unsigned int i;
702 fsl_ddr_cfg_regs_t *ddr;
703 char buf[20];
704 static const struct options_string options[] = {
705 CFG_REGS_CS(0, bnds),
706 CFG_REGS_CS(0, config),
707 CFG_REGS_CS(0, config_2),
708 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
709 CFG_REGS_CS(1, bnds),
710 CFG_REGS_CS(1, config),
711 CFG_REGS_CS(1, config_2),
712 #endif
713 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
714 CFG_REGS_CS(2, bnds),
715 CFG_REGS_CS(2, config),
716 CFG_REGS_CS(2, config_2),
717 #endif
718 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
719 CFG_REGS_CS(3, bnds),
720 CFG_REGS_CS(3, config),
721 CFG_REGS_CS(3, config_2),
722 #endif
723 CFG_REGS(timing_cfg_3),
724 CFG_REGS(timing_cfg_0),
725 CFG_REGS(timing_cfg_1),
726 CFG_REGS(timing_cfg_2),
727 CFG_REGS(ddr_sdram_cfg),
728 CFG_REGS(ddr_sdram_cfg_2),
729 CFG_REGS(ddr_sdram_cfg_3),
730 CFG_REGS(ddr_sdram_mode),
731 CFG_REGS(ddr_sdram_mode_2),
732 CFG_REGS(ddr_sdram_mode_3),
733 CFG_REGS(ddr_sdram_mode_4),
734 CFG_REGS(ddr_sdram_mode_5),
735 CFG_REGS(ddr_sdram_mode_6),
736 CFG_REGS(ddr_sdram_mode_7),
737 CFG_REGS(ddr_sdram_mode_8),
738 #ifdef CONFIG_SYS_FSL_DDR4
739 CFG_REGS(ddr_sdram_mode_9),
740 CFG_REGS(ddr_sdram_mode_10),
741 CFG_REGS(ddr_sdram_mode_11),
742 CFG_REGS(ddr_sdram_mode_12),
743 CFG_REGS(ddr_sdram_mode_13),
744 CFG_REGS(ddr_sdram_mode_14),
745 CFG_REGS(ddr_sdram_mode_15),
746 CFG_REGS(ddr_sdram_mode_16),
747 #endif
748 CFG_REGS(ddr_sdram_interval),
749 CFG_REGS(ddr_data_init),
750 CFG_REGS(ddr_sdram_clk_cntl),
751 CFG_REGS(ddr_init_addr),
752 CFG_REGS(ddr_init_ext_addr),
753 CFG_REGS(timing_cfg_4),
754 CFG_REGS(timing_cfg_5),
755 #ifdef CONFIG_SYS_FSL_DDR4
756 CFG_REGS(timing_cfg_6),
757 CFG_REGS(timing_cfg_7),
758 CFG_REGS(timing_cfg_8),
759 CFG_REGS(timing_cfg_9),
760 #endif
761 CFG_REGS(ddr_zq_cntl),
762 CFG_REGS(ddr_wrlvl_cntl),
763 CFG_REGS(ddr_wrlvl_cntl_2),
764 CFG_REGS(ddr_wrlvl_cntl_3),
765 CFG_REGS(ddr_sr_cntr),
766 CFG_REGS(ddr_sdram_rcw_1),
767 CFG_REGS(ddr_sdram_rcw_2),
768 CFG_REGS(ddr_sdram_rcw_3),
769 CFG_REGS(ddr_cdr1),
770 CFG_REGS(ddr_cdr2),
771 CFG_REGS(dq_map_0),
772 CFG_REGS(dq_map_1),
773 CFG_REGS(dq_map_2),
774 CFG_REGS(dq_map_3),
775 CFG_REGS(err_disable),
776 CFG_REGS(err_int_en),
777 CFG_REGS(ddr_sdram_rcw_2),
778 CFG_REGS(ddr_sdram_rcw_2),
779 CFG_REGS(ddr_eor),
780 };
781 static const unsigned int n_opts = ARRAY_SIZE(options);
782
783 debug("fsl_ddr_regs_edit: ctrl_num = %u, "
784 "regname = %s, value = %s\n",
785 ctrl_num, regname, value_str);
786 if (ctrl_num > CONFIG_SYS_NUM_DDR_CTLRS)
787 return;
788
789 ddr = &(pinfo->fsl_ddr_config_reg[ctrl_num]);
790
791 if (handle_option_table(options, n_opts, ddr, regname, value_str))
792 return;
793
794 for (i = 0; i < 64; i++) {
795 unsigned int value = simple_strtoul(value_str, NULL, 0);
796 sprintf(buf, "debug_%u", i + 1);
797 if (strcmp(buf, regname) == 0) {
798 ddr->debug[i] = value;
799 return;
800 }
801 }
802 printf("Error: couldn't find register string %s\n", regname);
803 }
804
805 #define CTRL_OPTIONS_HEX(x) {#x, offsetof(memctl_options_t, x), \
806 sizeof((memctl_options_t *)0)->x, 1}
807
print_memctl_options(const memctl_options_t * popts)808 static void print_memctl_options(const memctl_options_t *popts)
809 {
810 static const struct options_string options[] = {
811 CTRL_OPTIONS_CS(0, odt_rd_cfg),
812 CTRL_OPTIONS_CS(0, odt_wr_cfg),
813 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
814 CTRL_OPTIONS_CS(1, odt_rd_cfg),
815 CTRL_OPTIONS_CS(1, odt_wr_cfg),
816 #endif
817 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
818 CTRL_OPTIONS_CS(2, odt_rd_cfg),
819 CTRL_OPTIONS_CS(2, odt_wr_cfg),
820 #endif
821 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
822 CTRL_OPTIONS_CS(3, odt_rd_cfg),
823 CTRL_OPTIONS_CS(3, odt_wr_cfg),
824 #endif
825 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
826 CTRL_OPTIONS_CS(0, odt_rtt_norm),
827 CTRL_OPTIONS_CS(0, odt_rtt_wr),
828 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 1)
829 CTRL_OPTIONS_CS(1, odt_rtt_norm),
830 CTRL_OPTIONS_CS(1, odt_rtt_wr),
831 #endif
832 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 2)
833 CTRL_OPTIONS_CS(2, odt_rtt_norm),
834 CTRL_OPTIONS_CS(2, odt_rtt_wr),
835 #endif
836 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 3)
837 CTRL_OPTIONS_CS(3, odt_rtt_norm),
838 CTRL_OPTIONS_CS(3, odt_rtt_wr),
839 #endif
840 #endif
841 CTRL_OPTIONS(memctl_interleaving),
842 CTRL_OPTIONS(memctl_interleaving_mode),
843 CTRL_OPTIONS_HEX(ba_intlv_ctl),
844 CTRL_OPTIONS(ecc_mode),
845 CTRL_OPTIONS(ecc_init_using_memctl),
846 CTRL_OPTIONS(dqs_config),
847 CTRL_OPTIONS(self_refresh_in_sleep),
848 CTRL_OPTIONS(dynamic_power),
849 CTRL_OPTIONS(data_bus_width),
850 CTRL_OPTIONS(burst_length),
851 CTRL_OPTIONS(cas_latency_override),
852 CTRL_OPTIONS(cas_latency_override_value),
853 CTRL_OPTIONS(use_derated_caslat),
854 CTRL_OPTIONS(additive_latency_override),
855 CTRL_OPTIONS(additive_latency_override_value),
856 CTRL_OPTIONS(clk_adjust),
857 CTRL_OPTIONS(cpo_override),
858 CTRL_OPTIONS(write_data_delay),
859 CTRL_OPTIONS(half_strength_driver_enable),
860 /*
861 * These can probably be changed to 2T_EN and 3T_EN
862 * (using a leading numerical character) without problem
863 */
864 CTRL_OPTIONS(twot_en),
865 CTRL_OPTIONS(threet_en),
866 CTRL_OPTIONS(registered_dimm_en),
867 CTRL_OPTIONS(mirrored_dimm),
868 CTRL_OPTIONS(ap_en),
869 CTRL_OPTIONS(x4_en),
870 CTRL_OPTIONS(package_3ds),
871 CTRL_OPTIONS(bstopre),
872 CTRL_OPTIONS(wrlvl_override),
873 CTRL_OPTIONS(wrlvl_sample),
874 CTRL_OPTIONS(wrlvl_start),
875 CTRL_OPTIONS_HEX(cswl_override),
876 CTRL_OPTIONS(rcw_override),
877 CTRL_OPTIONS_HEX(rcw_1),
878 CTRL_OPTIONS_HEX(rcw_2),
879 CTRL_OPTIONS_HEX(rcw_3),
880 CTRL_OPTIONS_HEX(ddr_cdr1),
881 CTRL_OPTIONS_HEX(ddr_cdr2),
882 CTRL_OPTIONS(tfaw_window_four_activates_ps),
883 CTRL_OPTIONS(trwt_override),
884 CTRL_OPTIONS(trwt),
885 CTRL_OPTIONS(rtt_override),
886 CTRL_OPTIONS(rtt_override_value),
887 CTRL_OPTIONS(rtt_wr_override_value),
888 };
889 static const unsigned int n_opts = ARRAY_SIZE(options);
890
891 print_option_table(options, n_opts, popts);
892 }
893
894 #ifdef CONFIG_SYS_FSL_DDR1
ddr1_spd_dump(const ddr1_spd_eeprom_t * spd)895 void ddr1_spd_dump(const ddr1_spd_eeprom_t *spd)
896 {
897 unsigned int i;
898
899 printf("%-3d : %02x %s\n", 0, spd->info_size,
900 " spd->info_size, * 0 # bytes written into serial memory *");
901 printf("%-3d : %02x %s\n", 1, spd->chip_size,
902 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
903 printf("%-3d : %02x %s\n", 2, spd->mem_type,
904 " spd->mem_type, * 2 Fundamental memory type *");
905 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
906 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
907 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
908 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
909 printf("%-3d : %02x %s\n", 5, spd->nrows,
910 " spd->nrows * 5 # of DIMM Banks *");
911 printf("%-3d : %02x %s\n", 6, spd->dataw_lsb,
912 " spd->dataw_lsb, * 6 Data Width lsb of this assembly *");
913 printf("%-3d : %02x %s\n", 7, spd->dataw_msb,
914 " spd->dataw_msb, * 7 Data Width msb of this assembly *");
915 printf("%-3d : %02x %s\n", 8, spd->voltage,
916 " spd->voltage, * 8 Voltage intf std of this assembly *");
917 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
918 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
919 printf("%-3d : %02x %s\n", 10, spd->clk_access,
920 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
921 printf("%-3d : %02x %s\n", 11, spd->config,
922 " spd->config, * 11 DIMM Configuration type *");
923 printf("%-3d : %02x %s\n", 12, spd->refresh,
924 " spd->refresh, * 12 Refresh Rate/Type *");
925 printf("%-3d : %02x %s\n", 13, spd->primw,
926 " spd->primw, * 13 Primary SDRAM Width *");
927 printf("%-3d : %02x %s\n", 14, spd->ecw,
928 " spd->ecw, * 14 Error Checking SDRAM width *");
929 printf("%-3d : %02x %s\n", 15, spd->min_delay,
930 " spd->min_delay, * 15 Back to Back Random Access *");
931 printf("%-3d : %02x %s\n", 16, spd->burstl,
932 " spd->burstl, * 16 Burst Lengths Supported *");
933 printf("%-3d : %02x %s\n", 17, spd->nbanks,
934 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
935 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
936 " spd->cas_lat, * 18 CAS# Latencies Supported *");
937 printf("%-3d : %02x %s\n", 19, spd->cs_lat,
938 " spd->cs_lat, * 19 Chip Select Latency *");
939 printf("%-3d : %02x %s\n", 20, spd->write_lat,
940 " spd->write_lat, * 20 Write Latency/Recovery *");
941 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
942 " spd->mod_attr, * 21 SDRAM Module Attributes *");
943 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
944 " spd->dev_attr, * 22 SDRAM Device Attributes *");
945 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
946 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
947 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
948 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
949 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
950 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
951 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
952 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
953 printf("%-3d : %02x %s\n", 27, spd->trp,
954 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
955 printf("%-3d : %02x %s\n", 28, spd->trrd,
956 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
957 printf("%-3d : %02x %s\n", 29, spd->trcd,
958 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
959 printf("%-3d : %02x %s\n", 30, spd->tras,
960 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
961 printf("%-3d : %02x %s\n", 31, spd->bank_dens,
962 " spd->bank_dens, * 31 Density of each bank on module *");
963 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
964 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
965 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
966 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
967 printf("%-3d : %02x %s\n", 34, spd->data_setup,
968 " spd->data_setup, * 34 Data signal input setup time *");
969 printf("%-3d : %02x %s\n", 35, spd->data_hold,
970 " spd->data_hold, * 35 Data signal input hold time *");
971 printf("%-3d : %02x %s\n", 36, spd->res_36_40[0],
972 " spd->res_36_40[0], * 36 Reserved / tWR *");
973 printf("%-3d : %02x %s\n", 37, spd->res_36_40[1],
974 " spd->res_36_40[1], * 37 Reserved / tWTR *");
975 printf("%-3d : %02x %s\n", 38, spd->res_36_40[2],
976 " spd->res_36_40[2], * 38 Reserved / tRTP *");
977 printf("%-3d : %02x %s\n", 39, spd->res_36_40[3],
978 " spd->res_36_40[3], * 39 Reserved / mem_probe *");
979 printf("%-3d : %02x %s\n", 40, spd->res_36_40[4],
980 " spd->res_36_40[4], * 40 Reserved / trc,trfc extensions *");
981 printf("%-3d : %02x %s\n", 41, spd->trc,
982 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
983 printf("%-3d : %02x %s\n", 42, spd->trfc,
984 " spd->trfc, * 42 Min Auto to Active period tRFC *");
985 printf("%-3d : %02x %s\n", 43, spd->tckmax,
986 " spd->tckmax, * 43 Max device cycle time tCKmax *");
987 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
988 " spd->tdqsq, * 44 Max DQS to DQ skew *");
989 printf("%-3d : %02x %s\n", 45, spd->tqhs,
990 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
991 printf("%-3d : %02x %s\n", 46, spd->res_46,
992 " spd->res_46, * 46 Reserved/ PLL Relock time *");
993 printf("%-3d : %02x %s\n", 47, spd->dimm_height,
994 " spd->dimm_height * 47 SDRAM DIMM Height *");
995
996 printf("%-3d-%3d: ", 48, 61);
997
998 for (i = 0; i < 14; i++)
999 printf("%02x", spd->res_48_61[i]);
1000
1001 printf(" * 48-61 IDD in SPD and Reserved space *\n");
1002
1003 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
1004 " spd->spd_rev, * 62 SPD Data Revision Code *");
1005 printf("%-3d : %02x %s\n", 63, spd->cksum,
1006 " spd->cksum, * 63 Checksum for bytes 0-62 *");
1007 printf("%-3d-%3d: ", 64, 71);
1008
1009 for (i = 0; i < 8; i++)
1010 printf("%02x", spd->mid[i]);
1011
1012 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1013 printf("%-3d : %02x %s\n", 72, spd->mloc,
1014 " spd->mloc, * 72 Manufacturing Location *");
1015
1016 printf("%-3d-%3d: >>", 73, 90);
1017
1018 for (i = 0; i < 18; i++)
1019 printf("%c", spd->mpart[i]);
1020
1021 printf("<<* 73 Manufacturer's Part Number *\n");
1022
1023 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1024 "* 91 Revision Code *");
1025 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1026 "* 93 Manufacturing Date *");
1027 printf("%-3d-%3d: ", 95, 98);
1028
1029 for (i = 0; i < 4; i++)
1030 printf("%02x", spd->sernum[i]);
1031
1032 printf("* 95 Assembly Serial Number *\n");
1033
1034 printf("%-3d-%3d: ", 99, 127);
1035
1036 for (i = 0; i < 27; i++)
1037 printf("%02x", spd->mspec[i]);
1038
1039 printf("* 99 Manufacturer Specific Data *\n");
1040 }
1041 #endif
1042
1043 #ifdef CONFIG_SYS_FSL_DDR2
ddr2_spd_dump(const ddr2_spd_eeprom_t * spd)1044 void ddr2_spd_dump(const ddr2_spd_eeprom_t *spd)
1045 {
1046 unsigned int i;
1047
1048 printf("%-3d : %02x %s\n", 0, spd->info_size,
1049 " spd->info_size, * 0 # bytes written into serial memory *");
1050 printf("%-3d : %02x %s\n", 1, spd->chip_size,
1051 " spd->chip_size, * 1 Total # bytes of SPD memory device *");
1052 printf("%-3d : %02x %s\n", 2, spd->mem_type,
1053 " spd->mem_type, * 2 Fundamental memory type *");
1054 printf("%-3d : %02x %s\n", 3, spd->nrow_addr,
1055 " spd->nrow_addr, * 3 # of Row Addresses on this assembly *");
1056 printf("%-3d : %02x %s\n", 4, spd->ncol_addr,
1057 " spd->ncol_addr, * 4 # of Column Addrs on this assembly *");
1058 printf("%-3d : %02x %s\n", 5, spd->mod_ranks,
1059 " spd->mod_ranks * 5 # of Module Rows on this assembly *");
1060 printf("%-3d : %02x %s\n", 6, spd->dataw,
1061 " spd->dataw, * 6 Data Width of this assembly *");
1062 printf("%-3d : %02x %s\n", 7, spd->res_7,
1063 " spd->res_7, * 7 Reserved *");
1064 printf("%-3d : %02x %s\n", 8, spd->voltage,
1065 " spd->voltage, * 8 Voltage intf std of this assembly *");
1066 printf("%-3d : %02x %s\n", 9, spd->clk_cycle,
1067 " spd->clk_cycle, * 9 SDRAM Cycle time at CL=X *");
1068 printf("%-3d : %02x %s\n", 10, spd->clk_access,
1069 " spd->clk_access, * 10 SDRAM Access from Clock at CL=X *");
1070 printf("%-3d : %02x %s\n", 11, spd->config,
1071 " spd->config, * 11 DIMM Configuration type *");
1072 printf("%-3d : %02x %s\n", 12, spd->refresh,
1073 " spd->refresh, * 12 Refresh Rate/Type *");
1074 printf("%-3d : %02x %s\n", 13, spd->primw,
1075 " spd->primw, * 13 Primary SDRAM Width *");
1076 printf("%-3d : %02x %s\n", 14, spd->ecw,
1077 " spd->ecw, * 14 Error Checking SDRAM width *");
1078 printf("%-3d : %02x %s\n", 15, spd->res_15,
1079 " spd->res_15, * 15 Reserved *");
1080 printf("%-3d : %02x %s\n", 16, spd->burstl,
1081 " spd->burstl, * 16 Burst Lengths Supported *");
1082 printf("%-3d : %02x %s\n", 17, spd->nbanks,
1083 " spd->nbanks, * 17 # of Banks on Each SDRAM Device *");
1084 printf("%-3d : %02x %s\n", 18, spd->cas_lat,
1085 " spd->cas_lat, * 18 CAS# Latencies Supported *");
1086 printf("%-3d : %02x %s\n", 19, spd->mech_char,
1087 " spd->mech_char, * 19 Mechanical Characteristics *");
1088 printf("%-3d : %02x %s\n", 20, spd->dimm_type,
1089 " spd->dimm_type, * 20 DIMM type *");
1090 printf("%-3d : %02x %s\n", 21, spd->mod_attr,
1091 " spd->mod_attr, * 21 SDRAM Module Attributes *");
1092 printf("%-3d : %02x %s\n", 22, spd->dev_attr,
1093 " spd->dev_attr, * 22 SDRAM Device Attributes *");
1094 printf("%-3d : %02x %s\n", 23, spd->clk_cycle2,
1095 " spd->clk_cycle2, * 23 Min SDRAM Cycle time at CL=X-1 *");
1096 printf("%-3d : %02x %s\n", 24, spd->clk_access2,
1097 " spd->clk_access2, * 24 SDRAM Access from Clock at CL=X-1 *");
1098 printf("%-3d : %02x %s\n", 25, spd->clk_cycle3,
1099 " spd->clk_cycle3, * 25 Min SDRAM Cycle time at CL=X-2 *");
1100 printf("%-3d : %02x %s\n", 26, spd->clk_access3,
1101 " spd->clk_access3, * 26 Max Access from Clock at CL=X-2 *");
1102 printf("%-3d : %02x %s\n", 27, spd->trp,
1103 " spd->trp, * 27 Min Row Precharge Time (tRP)*");
1104 printf("%-3d : %02x %s\n", 28, spd->trrd,
1105 " spd->trrd, * 28 Min Row Active to Row Active (tRRD) *");
1106 printf("%-3d : %02x %s\n", 29, spd->trcd,
1107 " spd->trcd, * 29 Min RAS to CAS Delay (tRCD) *");
1108 printf("%-3d : %02x %s\n", 30, spd->tras,
1109 " spd->tras, * 30 Minimum RAS Pulse Width (tRAS) *");
1110 printf("%-3d : %02x %s\n", 31, spd->rank_dens,
1111 " spd->rank_dens, * 31 Density of each rank on module *");
1112 printf("%-3d : %02x %s\n", 32, spd->ca_setup,
1113 " spd->ca_setup, * 32 Cmd + Addr signal input setup time *");
1114 printf("%-3d : %02x %s\n", 33, spd->ca_hold,
1115 " spd->ca_hold, * 33 Cmd and Addr signal input hold time *");
1116 printf("%-3d : %02x %s\n", 34, spd->data_setup,
1117 " spd->data_setup, * 34 Data signal input setup time *");
1118 printf("%-3d : %02x %s\n", 35, spd->data_hold,
1119 " spd->data_hold, * 35 Data signal input hold time *");
1120 printf("%-3d : %02x %s\n", 36, spd->twr,
1121 " spd->twr, * 36 Write Recovery time tWR *");
1122 printf("%-3d : %02x %s\n", 37, spd->twtr,
1123 " spd->twtr, * 37 Int write to read delay tWTR *");
1124 printf("%-3d : %02x %s\n", 38, spd->trtp,
1125 " spd->trtp, * 38 Int read to precharge delay tRTP *");
1126 printf("%-3d : %02x %s\n", 39, spd->mem_probe,
1127 " spd->mem_probe, * 39 Mem analysis probe characteristics *");
1128 printf("%-3d : %02x %s\n", 40, spd->trctrfc_ext,
1129 " spd->trctrfc_ext, * 40 Extensions to trc and trfc *");
1130 printf("%-3d : %02x %s\n", 41, spd->trc,
1131 " spd->trc, * 41 Min Active to Auto refresh time tRC *");
1132 printf("%-3d : %02x %s\n", 42, spd->trfc,
1133 " spd->trfc, * 42 Min Auto to Active period tRFC *");
1134 printf("%-3d : %02x %s\n", 43, spd->tckmax,
1135 " spd->tckmax, * 43 Max device cycle time tCKmax *");
1136 printf("%-3d : %02x %s\n", 44, spd->tdqsq,
1137 " spd->tdqsq, * 44 Max DQS to DQ skew *");
1138 printf("%-3d : %02x %s\n", 45, spd->tqhs,
1139 " spd->tqhs, * 45 Max Read DataHold skew tQHS *");
1140 printf("%-3d : %02x %s\n", 46, spd->pll_relock,
1141 " spd->pll_relock, * 46 PLL Relock time *");
1142 printf("%-3d : %02x %s\n", 47, spd->t_casemax,
1143 " spd->t_casemax, * 47 t_casemax *");
1144 printf("%-3d : %02x %s\n", 48, spd->psi_ta_dram,
1145 " spd->psi_ta_dram, * 48 Thermal Resistance of DRAM Package "
1146 "from Top (Case) to Ambient (Psi T-A DRAM) *");
1147 printf("%-3d : %02x %s\n", 49, spd->dt0_mode,
1148 " spd->dt0_mode, * 49 DRAM Case Temperature Rise from "
1149 "Ambient due to Activate-Precharge/Mode Bits "
1150 "(DT0/Mode Bits) *)");
1151 printf("%-3d : %02x %s\n", 50, spd->dt2n_dt2q,
1152 " spd->dt2n_dt2q, * 50 DRAM Case Temperature Rise from "
1153 "Ambient due to Precharge/Quiet Standby "
1154 "(DT2N/DT2Q) *");
1155 printf("%-3d : %02x %s\n", 51, spd->dt2p,
1156 " spd->dt2p, * 51 DRAM Case Temperature Rise from "
1157 "Ambient due to Precharge Power-Down (DT2P) *");
1158 printf("%-3d : %02x %s\n", 52, spd->dt3n,
1159 " spd->dt3n, * 52 DRAM Case Temperature Rise from "
1160 "Ambient due to Active Standby (DT3N) *");
1161 printf("%-3d : %02x %s\n", 53, spd->dt3pfast,
1162 " spd->dt3pfast, * 53 DRAM Case Temperature Rise from "
1163 "Ambient due to Active Power-Down with Fast PDN Exit "
1164 "(DT3Pfast) *");
1165 printf("%-3d : %02x %s\n", 54, spd->dt3pslow,
1166 " spd->dt3pslow, * 54 DRAM Case Temperature Rise from "
1167 "Ambient due to Active Power-Down with Slow PDN Exit "
1168 "(DT3Pslow) *");
1169 printf("%-3d : %02x %s\n", 55, spd->dt4r_dt4r4w,
1170 " spd->dt4r_dt4r4w, * 55 DRAM Case Temperature Rise from "
1171 "Ambient due to Page Open Burst Read/DT4R4W Mode Bit "
1172 "(DT4R/DT4R4W Mode Bit) *");
1173 printf("%-3d : %02x %s\n", 56, spd->dt5b,
1174 " spd->dt5b, * 56 DRAM Case Temperature Rise from "
1175 "Ambient due to Burst Refresh (DT5B) *");
1176 printf("%-3d : %02x %s\n", 57, spd->dt7,
1177 " spd->dt7, * 57 DRAM Case Temperature Rise from "
1178 "Ambient due to Bank Interleave Reads with "
1179 "Auto-Precharge (DT7) *");
1180 printf("%-3d : %02x %s\n", 58, spd->psi_ta_pll,
1181 " spd->psi_ta_pll, * 58 Thermal Resistance of PLL Package form"
1182 " Top (Case) to Ambient (Psi T-A PLL) *");
1183 printf("%-3d : %02x %s\n", 59, spd->psi_ta_reg,
1184 " spd->psi_ta_reg, * 59 Thermal Reisitance of Register Package"
1185 " from Top (Case) to Ambient (Psi T-A Register) *");
1186 printf("%-3d : %02x %s\n", 60, spd->dtpllactive,
1187 " spd->dtpllactive, * 60 PLL Case Temperature Rise from "
1188 "Ambient due to PLL Active (DT PLL Active) *");
1189 printf("%-3d : %02x %s\n", 61, spd->dtregact,
1190 " spd->dtregact, "
1191 "* 61 Register Case Temperature Rise from Ambient due to "
1192 "Register Active/Mode Bit (DT Register Active/Mode Bit) *");
1193 printf("%-3d : %02x %s\n", 62, spd->spd_rev,
1194 " spd->spd_rev, * 62 SPD Data Revision Code *");
1195 printf("%-3d : %02x %s\n", 63, spd->cksum,
1196 " spd->cksum, * 63 Checksum for bytes 0-62 *");
1197
1198 printf("%-3d-%3d: ", 64, 71);
1199
1200 for (i = 0; i < 8; i++)
1201 printf("%02x", spd->mid[i]);
1202
1203 printf("* 64 Mfr's JEDEC ID code per JEP-108E *\n");
1204
1205 printf("%-3d : %02x %s\n", 72, spd->mloc,
1206 " spd->mloc, * 72 Manufacturing Location *");
1207
1208 printf("%-3d-%3d: >>", 73, 90);
1209 for (i = 0; i < 18; i++)
1210 printf("%c", spd->mpart[i]);
1211
1212
1213 printf("<<* 73 Manufacturer's Part Number *\n");
1214
1215 printf("%-3d-%3d: %02x %02x %s\n", 91, 92, spd->rev[0], spd->rev[1],
1216 "* 91 Revision Code *");
1217 printf("%-3d-%3d: %02x %02x %s\n", 93, 94, spd->mdate[0], spd->mdate[1],
1218 "* 93 Manufacturing Date *");
1219 printf("%-3d-%3d: ", 95, 98);
1220
1221 for (i = 0; i < 4; i++)
1222 printf("%02x", spd->sernum[i]);
1223
1224 printf("* 95 Assembly Serial Number *\n");
1225
1226 printf("%-3d-%3d: ", 99, 127);
1227 for (i = 0; i < 27; i++)
1228 printf("%02x", spd->mspec[i]);
1229
1230
1231 printf("* 99 Manufacturer Specific Data *\n");
1232 }
1233 #endif
1234
1235 #ifdef CONFIG_SYS_FSL_DDR3
ddr3_spd_dump(const ddr3_spd_eeprom_t * spd)1236 void ddr3_spd_dump(const ddr3_spd_eeprom_t *spd)
1237 {
1238 unsigned int i;
1239
1240 /* General Section: Bytes 0-59 */
1241
1242 #define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
1243 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1244 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1245
1246 PRINT_NXS(0, spd->info_size_crc,
1247 "info_size_crc bytes written into serial memory, "
1248 "CRC coverage");
1249 PRINT_NXS(1, spd->spd_rev,
1250 "spd_rev SPD Revision");
1251 PRINT_NXS(2, spd->mem_type,
1252 "mem_type Key Byte / DRAM Device Type");
1253 PRINT_NXS(3, spd->module_type,
1254 "module_type Key Byte / Module Type");
1255 PRINT_NXS(4, spd->density_banks,
1256 "density_banks SDRAM Density and Banks");
1257 PRINT_NXS(5, spd->addressing,
1258 "addressing SDRAM Addressing");
1259 PRINT_NXS(6, spd->module_vdd,
1260 "module_vdd Module Nominal Voltage, VDD");
1261 PRINT_NXS(7, spd->organization,
1262 "organization Module Organization");
1263 PRINT_NXS(8, spd->bus_width,
1264 "bus_width Module Memory Bus Width");
1265 PRINT_NXS(9, spd->ftb_div,
1266 "ftb_div Fine Timebase (FTB) Dividend / Divisor");
1267 PRINT_NXS(10, spd->mtb_dividend,
1268 "mtb_dividend Medium Timebase (MTB) Dividend");
1269 PRINT_NXS(11, spd->mtb_divisor,
1270 "mtb_divisor Medium Timebase (MTB) Divisor");
1271 PRINT_NXS(12, spd->tck_min,
1272 "tck_min SDRAM Minimum Cycle Time");
1273 PRINT_NXS(13, spd->res_13,
1274 "res_13 Reserved");
1275 PRINT_NXS(14, spd->caslat_lsb,
1276 "caslat_lsb CAS Latencies Supported, LSB");
1277 PRINT_NXS(15, spd->caslat_msb,
1278 "caslat_msb CAS Latencies Supported, MSB");
1279 PRINT_NXS(16, spd->taa_min,
1280 "taa_min Min CAS Latency Time");
1281 PRINT_NXS(17, spd->twr_min,
1282 "twr_min Min Write REcovery Time");
1283 PRINT_NXS(18, spd->trcd_min,
1284 "trcd_min Min RAS# to CAS# Delay Time");
1285 PRINT_NXS(19, spd->trrd_min,
1286 "trrd_min Min Row Active to Row Active Delay Time");
1287 PRINT_NXS(20, spd->trp_min,
1288 "trp_min Min Row Precharge Delay Time");
1289 PRINT_NXS(21, spd->tras_trc_ext,
1290 "tras_trc_ext Upper Nibbles for tRAS and tRC");
1291 PRINT_NXS(22, spd->tras_min_lsb,
1292 "tras_min_lsb Min Active to Precharge Delay Time, LSB");
1293 PRINT_NXS(23, spd->trc_min_lsb,
1294 "trc_min_lsb Min Active to Active/Refresh Delay Time, LSB");
1295 PRINT_NXS(24, spd->trfc_min_lsb,
1296 "trfc_min_lsb Min Refresh Recovery Delay Time LSB");
1297 PRINT_NXS(25, spd->trfc_min_msb,
1298 "trfc_min_msb Min Refresh Recovery Delay Time MSB");
1299 PRINT_NXS(26, spd->twtr_min,
1300 "twtr_min Min Internal Write to Read Command Delay Time");
1301 PRINT_NXS(27, spd->trtp_min,
1302 "trtp_min "
1303 "Min Internal Read to Precharge Command Delay Time");
1304 PRINT_NXS(28, spd->tfaw_msb,
1305 "tfaw_msb Upper Nibble for tFAW");
1306 PRINT_NXS(29, spd->tfaw_min,
1307 "tfaw_min Min Four Activate Window Delay Time");
1308 PRINT_NXS(30, spd->opt_features,
1309 "opt_features SDRAM Optional Features");
1310 PRINT_NXS(31, spd->therm_ref_opt,
1311 "therm_ref_opt SDRAM Thermal and Refresh Opts");
1312 PRINT_NXS(32, spd->therm_sensor,
1313 "therm_sensor SDRAM Thermal Sensor");
1314 PRINT_NXS(33, spd->device_type,
1315 "device_type SDRAM Device Type");
1316 PRINT_NXS(34, spd->fine_tck_min,
1317 "fine_tck_min Fine offset for tCKmin");
1318 PRINT_NXS(35, spd->fine_taa_min,
1319 "fine_taa_min Fine offset for tAAmin");
1320 PRINT_NXS(36, spd->fine_trcd_min,
1321 "fine_trcd_min Fine offset for tRCDmin");
1322 PRINT_NXS(37, spd->fine_trp_min,
1323 "fine_trp_min Fine offset for tRPmin");
1324 PRINT_NXS(38, spd->fine_trc_min,
1325 "fine_trc_min Fine offset for tRCmin");
1326
1327 printf("%-3d-%3d: ", 39, 59); /* Reserved, General Section */
1328
1329 for (i = 39; i <= 59; i++)
1330 printf("%02x ", spd->res_39_59[i - 39]);
1331
1332 puts("\n");
1333
1334 switch (spd->module_type) {
1335 case 0x02: /* UDIMM */
1336 case 0x03: /* SO-DIMM */
1337 case 0x04: /* Micro-DIMM */
1338 case 0x06: /* Mini-UDIMM */
1339 PRINT_NXS(60, spd->mod_section.unbuffered.mod_height,
1340 "mod_height (Unbuffered) Module Nominal Height");
1341 PRINT_NXS(61, spd->mod_section.unbuffered.mod_thickness,
1342 "mod_thickness (Unbuffered) Module Maximum Thickness");
1343 PRINT_NXS(62, spd->mod_section.unbuffered.ref_raw_card,
1344 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1345 PRINT_NXS(63, spd->mod_section.unbuffered.addr_mapping,
1346 "addr_mapping (Unbuffered) Address mapping from "
1347 "Edge Connector to DRAM");
1348 break;
1349 case 0x01: /* RDIMM */
1350 case 0x05: /* Mini-RDIMM */
1351 PRINT_NXS(60, spd->mod_section.registered.mod_height,
1352 "mod_height (Registered) Module Nominal Height");
1353 PRINT_NXS(61, spd->mod_section.registered.mod_thickness,
1354 "mod_thickness (Registered) Module Maximum Thickness");
1355 PRINT_NXS(62, spd->mod_section.registered.ref_raw_card,
1356 "ref_raw_card (Registered) Reference Raw Card Used");
1357 PRINT_NXS(63, spd->mod_section.registered.modu_attr,
1358 "modu_attr (Registered) DIMM Module Attributes");
1359 PRINT_NXS(64, spd->mod_section.registered.thermal,
1360 "thermal (Registered) Thermal Heat "
1361 "Spreader Solution");
1362 PRINT_NXS(65, spd->mod_section.registered.reg_id_lo,
1363 "reg_id_lo (Registered) Register Manufacturer ID "
1364 "Code, LSB");
1365 PRINT_NXS(66, spd->mod_section.registered.reg_id_hi,
1366 "reg_id_hi (Registered) Register Manufacturer ID "
1367 "Code, MSB");
1368 PRINT_NXS(67, spd->mod_section.registered.reg_rev,
1369 "reg_rev (Registered) Register "
1370 "Revision Number");
1371 PRINT_NXS(68, spd->mod_section.registered.reg_type,
1372 "reg_type (Registered) Register Type");
1373 for (i = 69; i <= 76; i++) {
1374 printf("%-3d : %02x rcw[%d]\n", i,
1375 spd->mod_section.registered.rcw[i-69], i-69);
1376 }
1377 break;
1378 default:
1379 /* Module-specific Section, Unsupported Module Type */
1380 printf("%-3d-%3d: ", 60, 116);
1381
1382 for (i = 60; i <= 116; i++)
1383 printf("%02x", spd->mod_section.uc[i - 60]);
1384
1385 break;
1386 }
1387
1388 /* Unique Module ID: Bytes 117-125 */
1389 PRINT_NXS(117, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1390 PRINT_NXS(118, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1391 PRINT_NXS(119, spd->mloc, "Mfg Location");
1392 PRINT_NNXXS(120, 121, spd->mdate[0], spd->mdate[1], "Mfg Date");
1393
1394 printf("%-3d-%3d: ", 122, 125);
1395
1396 for (i = 122; i <= 125; i++)
1397 printf("%02x ", spd->sernum[i - 122]);
1398 printf(" Module Serial Number\n");
1399
1400 /* CRC: Bytes 126-127 */
1401 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1402
1403 /* Other Manufacturer Fields and User Space: Bytes 128-255 */
1404 printf("%-3d-%3d: ", 128, 145);
1405 for (i = 128; i <= 145; i++)
1406 printf("%02x ", spd->mpart[i - 128]);
1407 printf(" Mfg's Module Part Number\n");
1408
1409 PRINT_NNXXS(146, 147, spd->mrev[0], spd->mrev[1],
1410 "Module Revision code");
1411
1412 PRINT_NXS(148, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1413 PRINT_NXS(149, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1414
1415 printf("%-3d-%3d: ", 150, 175);
1416 for (i = 150; i <= 175; i++)
1417 printf("%02x ", spd->msd[i - 150]);
1418 printf(" Mfg's Specific Data\n");
1419
1420 printf("%-3d-%3d: ", 176, 255);
1421 for (i = 176; i <= 255; i++)
1422 printf("%02x", spd->cust[i - 176]);
1423 printf(" Mfg's Specific Data\n");
1424
1425 }
1426 #endif
1427
1428 #ifdef CONFIG_SYS_FSL_DDR4
ddr4_spd_dump(const struct ddr4_spd_eeprom_s * spd)1429 void ddr4_spd_dump(const struct ddr4_spd_eeprom_s *spd)
1430 {
1431 unsigned int i;
1432
1433 /* General Section: Bytes 0-127 */
1434
1435 #define PRINT_NXS(x, y, z...) printf("%-3d : %02x " z "\n", x, (u8)y);
1436 #define PRINT_NNXXS(n0, n1, x0, x1, s) \
1437 printf("%-3d-%3d: %02x %02x " s "\n", n0, n1, x0, x1);
1438
1439 PRINT_NXS(0, spd->info_size_crc,
1440 "info_size_crc bytes written into serial memory, CRC coverage");
1441 PRINT_NXS(1, spd->spd_rev,
1442 "spd_rev SPD Revision");
1443 PRINT_NXS(2, spd->mem_type,
1444 "mem_type Key Byte / DRAM Device Type");
1445 PRINT_NXS(3, spd->module_type,
1446 "module_type Key Byte / Module Type");
1447 PRINT_NXS(4, spd->density_banks,
1448 "density_banks SDRAM Density and Banks");
1449 PRINT_NXS(5, spd->addressing,
1450 "addressing SDRAM Addressing");
1451 PRINT_NXS(6, spd->package_type,
1452 "package_type Package type");
1453 PRINT_NXS(7, spd->opt_feature,
1454 "opt_feature Optional features");
1455 PRINT_NXS(8, spd->thermal_ref,
1456 "thermal_ref Thermal and Refresh options");
1457 PRINT_NXS(9, spd->oth_opt_features,
1458 "oth_opt_features Other SDRAM optional features");
1459 PRINT_NXS(10, spd->res_10,
1460 "res_10 Reserved");
1461 PRINT_NXS(11, spd->module_vdd,
1462 "module_vdd Module Nominal Voltage, VDD");
1463 PRINT_NXS(12, spd->organization,
1464 "organization Module Organization");
1465 PRINT_NXS(13, spd->bus_width,
1466 "bus_width Module Memory Bus Width");
1467 PRINT_NXS(14, spd->therm_sensor,
1468 "therm_sensor Module Thermal Sensor");
1469 PRINT_NXS(15, spd->ext_type,
1470 "ext_type Extended module type");
1471 PRINT_NXS(16, spd->res_16,
1472 "res_16 Reserved");
1473 PRINT_NXS(17, spd->timebases,
1474 "timebases MTb and FTB");
1475 PRINT_NXS(18, spd->tck_min,
1476 "tck_min tCKAVGmin");
1477 PRINT_NXS(19, spd->tck_max,
1478 "tck_max TCKAVGmax");
1479 PRINT_NXS(20, spd->caslat_b1,
1480 "caslat_b1 CAS latencies, 1st byte");
1481 PRINT_NXS(21, spd->caslat_b2,
1482 "caslat_b2 CAS latencies, 2nd byte");
1483 PRINT_NXS(22, spd->caslat_b3,
1484 "caslat_b3 CAS latencies, 3rd byte ");
1485 PRINT_NXS(23, spd->caslat_b4,
1486 "caslat_b4 CAS latencies, 4th byte");
1487 PRINT_NXS(24, spd->taa_min,
1488 "taa_min Min CAS Latency Time");
1489 PRINT_NXS(25, spd->trcd_min,
1490 "trcd_min Min RAS# to CAS# Delay Time");
1491 PRINT_NXS(26, spd->trp_min,
1492 "trp_min Min Row Precharge Delay Time");
1493 PRINT_NXS(27, spd->tras_trc_ext,
1494 "tras_trc_ext Upper Nibbles for tRAS and tRC");
1495 PRINT_NXS(28, spd->tras_min_lsb,
1496 "tras_min_lsb tRASmin, lsb");
1497 PRINT_NXS(29, spd->trc_min_lsb,
1498 "trc_min_lsb tRCmin, lsb");
1499 PRINT_NXS(30, spd->trfc1_min_lsb,
1500 "trfc1_min_lsb Min Refresh Recovery Delay Time, LSB");
1501 PRINT_NXS(31, spd->trfc1_min_msb,
1502 "trfc1_min_msb Min Refresh Recovery Delay Time, MSB ");
1503 PRINT_NXS(32, spd->trfc2_min_lsb,
1504 "trfc2_min_lsb Min Refresh Recovery Delay Time, LSB");
1505 PRINT_NXS(33, spd->trfc2_min_msb,
1506 "trfc2_min_msb Min Refresh Recovery Delay Time, MSB");
1507 PRINT_NXS(34, spd->trfc4_min_lsb,
1508 "trfc4_min_lsb Min Refresh Recovery Delay Time, LSB");
1509 PRINT_NXS(35, spd->trfc4_min_msb,
1510 "trfc4_min_msb Min Refresh Recovery Delay Time, MSB");
1511 PRINT_NXS(36, spd->tfaw_msb,
1512 "tfaw_msb Upper Nibble for tFAW");
1513 PRINT_NXS(37, spd->tfaw_min,
1514 "tfaw_min tFAW, lsb");
1515 PRINT_NXS(38, spd->trrds_min,
1516 "trrds_min tRRD_Smin, MTB");
1517 PRINT_NXS(39, spd->trrdl_min,
1518 "trrdl_min tRRD_Lmin, MTB");
1519 PRINT_NXS(40, spd->tccdl_min,
1520 "tccdl_min tCCS_Lmin, MTB");
1521
1522 printf("%-3d-%3d: ", 41, 59); /* Reserved, General Section */
1523 for (i = 41; i <= 59; i++)
1524 printf("%02x ", spd->res_41[i - 41]);
1525
1526 puts("\n");
1527 printf("%-3d-%3d: ", 60, 77);
1528 for (i = 60; i <= 77; i++)
1529 printf("%02x ", spd->mapping[i - 60]);
1530 puts(" mapping[] Connector to SDRAM bit map\n");
1531
1532 PRINT_NXS(117, spd->fine_tccdl_min,
1533 "fine_tccdl_min Fine offset for tCCD_Lmin");
1534 PRINT_NXS(118, spd->fine_trrdl_min,
1535 "fine_trrdl_min Fine offset for tRRD_Lmin");
1536 PRINT_NXS(119, spd->fine_trrds_min,
1537 "fine_trrds_min Fine offset for tRRD_Smin");
1538 PRINT_NXS(120, spd->fine_trc_min,
1539 "fine_trc_min Fine offset for tRCmin");
1540 PRINT_NXS(121, spd->fine_trp_min,
1541 "fine_trp_min Fine offset for tRPmin");
1542 PRINT_NXS(122, spd->fine_trcd_min,
1543 "fine_trcd_min Fine offset for tRCDmin");
1544 PRINT_NXS(123, spd->fine_taa_min,
1545 "fine_taa_min Fine offset for tAAmin");
1546 PRINT_NXS(124, spd->fine_tck_max,
1547 "fine_tck_max Fine offset for tCKAVGmax");
1548 PRINT_NXS(125, spd->fine_tck_min,
1549 "fine_tck_min Fine offset for tCKAVGmin");
1550
1551 /* CRC: Bytes 126-127 */
1552 PRINT_NNXXS(126, 127, spd->crc[0], spd->crc[1], " SPD CRC");
1553
1554 switch (spd->module_type) {
1555 case 0x02: /* UDIMM */
1556 case 0x03: /* SO-DIMM */
1557 PRINT_NXS(128, spd->mod_section.unbuffered.mod_height,
1558 "mod_height (Unbuffered) Module Nominal Height");
1559 PRINT_NXS(129, spd->mod_section.unbuffered.mod_thickness,
1560 "mod_thickness (Unbuffered) Module Maximum Thickness");
1561 PRINT_NXS(130, spd->mod_section.unbuffered.ref_raw_card,
1562 "ref_raw_card (Unbuffered) Reference Raw Card Used");
1563 PRINT_NXS(131, spd->mod_section.unbuffered.addr_mapping,
1564 "addr_mapping (Unbuffered) Address mapping from Edge Connector to DRAM");
1565 PRINT_NNXXS(254, 255, spd->mod_section.unbuffered.crc[0],
1566 spd->mod_section.unbuffered.crc[1], " Module CRC");
1567 break;
1568 case 0x01: /* RDIMM */
1569 PRINT_NXS(128, spd->mod_section.registered.mod_height,
1570 "mod_height (Registered) Module Nominal Height");
1571 PRINT_NXS(129, spd->mod_section.registered.mod_thickness,
1572 "mod_thickness (Registered) Module Maximum Thickness");
1573 PRINT_NXS(130, spd->mod_section.registered.ref_raw_card,
1574 "ref_raw_card (Registered) Reference Raw Card Used");
1575 PRINT_NXS(131, spd->mod_section.registered.modu_attr,
1576 "modu_attr (Registered) DIMM Module Attributes");
1577 PRINT_NXS(132, spd->mod_section.registered.thermal,
1578 "thermal (Registered) Thermal Heat Spreader Solution");
1579 PRINT_NXS(133, spd->mod_section.registered.reg_id_lo,
1580 "reg_id_lo (Registered) Register Manufacturer ID Code, LSB");
1581 PRINT_NXS(134, spd->mod_section.registered.reg_id_hi,
1582 "reg_id_hi (Registered) Register Manufacturer ID Code, MSB");
1583 PRINT_NXS(135, spd->mod_section.registered.reg_rev,
1584 "reg_rev (Registered) Register Revision Number");
1585 PRINT_NXS(136, spd->mod_section.registered.reg_map,
1586 "reg_map (Registered) Address mapping");
1587 PRINT_NNXXS(254, 255, spd->mod_section.registered.crc[0],
1588 spd->mod_section.registered.crc[1], " Module CRC");
1589 break;
1590 case 0x04: /* LRDIMM */
1591 PRINT_NXS(128, spd->mod_section.loadreduced.mod_height,
1592 "mod_height (Loadreduced) Module Nominal Height");
1593 PRINT_NXS(129, spd->mod_section.loadreduced.mod_thickness,
1594 "mod_thickness (Loadreduced) Module Maximum Thickness");
1595 PRINT_NXS(130, spd->mod_section.loadreduced.ref_raw_card,
1596 "ref_raw_card (Loadreduced) Reference Raw Card Used");
1597 PRINT_NXS(131, spd->mod_section.loadreduced.modu_attr,
1598 "modu_attr (Loadreduced) DIMM Module Attributes");
1599 PRINT_NXS(132, spd->mod_section.loadreduced.thermal,
1600 "thermal (Loadreduced) Thermal Heat Spreader Solution");
1601 PRINT_NXS(133, spd->mod_section.loadreduced.reg_id_lo,
1602 "reg_id_lo (Loadreduced) Register Manufacturer ID Code, LSB");
1603 PRINT_NXS(134, spd->mod_section.loadreduced.reg_id_hi,
1604 "reg_id_hi (Loadreduced) Register Manufacturer ID Code, MSB");
1605 PRINT_NXS(135, spd->mod_section.loadreduced.reg_rev,
1606 "reg_rev (Loadreduced) Register Revision Number");
1607 PRINT_NXS(136, spd->mod_section.loadreduced.reg_map,
1608 "reg_map (Loadreduced) Address mapping");
1609 PRINT_NXS(137, spd->mod_section.loadreduced.reg_drv,
1610 "reg_drv (Loadreduced) Reg output drive strength");
1611 PRINT_NXS(138, spd->mod_section.loadreduced.reg_drv_ck,
1612 "reg_drv_ck (Loadreduced) Reg output drive strength for CK");
1613 PRINT_NXS(139, spd->mod_section.loadreduced.data_buf_rev,
1614 "data_buf_rev (Loadreduced) Data Buffer Revision Numbe");
1615 PRINT_NXS(140, spd->mod_section.loadreduced.vrefqe_r0,
1616 "vrefqe_r0 (Loadreduced) DRAM VrefDQ for Package Rank 0");
1617 PRINT_NXS(141, spd->mod_section.loadreduced.vrefqe_r1,
1618 "vrefqe_r1 (Loadreduced) DRAM VrefDQ for Package Rank 1");
1619 PRINT_NXS(142, spd->mod_section.loadreduced.vrefqe_r2,
1620 "vrefqe_r2 (Loadreduced) DRAM VrefDQ for Package Rank 2");
1621 PRINT_NXS(143, spd->mod_section.loadreduced.vrefqe_r3,
1622 "vrefqe_r3 (Loadreduced) DRAM VrefDQ for Package Rank 3");
1623 PRINT_NXS(144, spd->mod_section.loadreduced.data_intf,
1624 "data_intf (Loadreduced) Data Buffer VrefDQ for DRAM Interface");
1625 PRINT_NXS(145, spd->mod_section.loadreduced.data_drv_1866,
1626 "data_drv_1866 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1627 PRINT_NXS(146, spd->mod_section.loadreduced.data_drv_2400,
1628 "data_drv_2400 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1629 PRINT_NXS(147, spd->mod_section.loadreduced.data_drv_3200,
1630 "data_drv_3200 (Loadreduced) Data Buffer MDQ Drive Strength and RTT");
1631 PRINT_NXS(148, spd->mod_section.loadreduced.dram_drv,
1632 "dram_drv (Loadreduced) DRAM Drive Strength");
1633 PRINT_NXS(149, spd->mod_section.loadreduced.dram_odt_1866,
1634 "dram_odt_1866 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1635 PRINT_NXS(150, spd->mod_section.loadreduced.dram_odt_2400,
1636 "dram_odt_2400 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1637 PRINT_NXS(151, spd->mod_section.loadreduced.dram_odt_3200,
1638 "dram_odt_3200 (Loadreduced) DRAM ODT (RTT_WR, RTT_NOM)");
1639 PRINT_NXS(152, spd->mod_section.loadreduced.dram_odt_park_1866,
1640 "dram_odt_park_1866 (Loadreduced) DRAM ODT (RTT_PARK)");
1641 PRINT_NXS(153, spd->mod_section.loadreduced.dram_odt_park_2400,
1642 "dram_odt_park_2400 (Loadreduced) DRAM ODT (RTT_PARK)");
1643 PRINT_NXS(154, spd->mod_section.loadreduced.dram_odt_park_3200,
1644 "dram_odt_park_3200 (Loadreduced) DRAM ODT (RTT_PARK)");
1645 PRINT_NNXXS(254, 255, spd->mod_section.loadreduced.crc[0],
1646 spd->mod_section.loadreduced.crc[1],
1647 " Module CRC");
1648 break;
1649 default:
1650 /* Module-specific Section, Unsupported Module Type */
1651 printf("%-3d-%3d: ", 128, 255);
1652
1653 for (i = 128; i <= 255; i++)
1654 printf("%02x", spd->mod_section.uc[i - 128]);
1655
1656 break;
1657 }
1658
1659 /* Unique Module ID: Bytes 320-383 */
1660 PRINT_NXS(320, spd->mmid_lsb, "Module MfgID Code LSB - JEP-106");
1661 PRINT_NXS(321, spd->mmid_msb, "Module MfgID Code MSB - JEP-106");
1662 PRINT_NXS(322, spd->mloc, "Mfg Location");
1663 PRINT_NNXXS(323, 324, spd->mdate[0], spd->mdate[1], "Mfg Date");
1664
1665 printf("%-3d-%3d: ", 325, 328);
1666
1667 for (i = 325; i <= 328; i++)
1668 printf("%02x ", spd->sernum[i - 325]);
1669 printf(" Module Serial Number\n");
1670
1671 printf("%-3d-%3d: ", 329, 348);
1672 for (i = 329; i <= 348; i++)
1673 printf("%02x ", spd->mpart[i - 329]);
1674 printf(" Mfg's Module Part Number\n");
1675
1676 PRINT_NXS(349, spd->mrev, "Module Revision code");
1677 PRINT_NXS(350, spd->dmid_lsb, "DRAM MfgID Code LSB - JEP-106");
1678 PRINT_NXS(351, spd->dmid_msb, "DRAM MfgID Code MSB - JEP-106");
1679 PRINT_NXS(352, spd->stepping, "DRAM stepping");
1680
1681 printf("%-3d-%3d: ", 353, 381);
1682 for (i = 353; i <= 381; i++)
1683 printf("%02x ", spd->msd[i - 353]);
1684 printf(" Mfg's Specific Data\n");
1685 }
1686 #endif
1687
generic_spd_dump(const generic_spd_eeprom_t * spd)1688 static inline void generic_spd_dump(const generic_spd_eeprom_t *spd)
1689 {
1690 #if defined(CONFIG_SYS_FSL_DDR1)
1691 ddr1_spd_dump(spd);
1692 #elif defined(CONFIG_SYS_FSL_DDR2)
1693 ddr2_spd_dump(spd);
1694 #elif defined(CONFIG_SYS_FSL_DDR3)
1695 ddr3_spd_dump(spd);
1696 #elif defined(CONFIG_SYS_FSL_DDR4)
1697 ddr4_spd_dump(spd);
1698 #endif
1699 }
1700
fsl_ddr_printinfo(const fsl_ddr_info_t * pinfo,unsigned int ctrl_mask,unsigned int dimm_mask,unsigned int do_mask)1701 static void fsl_ddr_printinfo(const fsl_ddr_info_t *pinfo,
1702 unsigned int ctrl_mask,
1703 unsigned int dimm_mask,
1704 unsigned int do_mask)
1705 {
1706 unsigned int i, j, retval;
1707
1708 /* STEP 1: DIMM SPD data */
1709 if (do_mask & STEP_GET_SPD) {
1710 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1711 if (!(ctrl_mask & (1 << i)))
1712 continue;
1713
1714 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1715 if (!(dimm_mask & (1 << j)))
1716 continue;
1717
1718 printf("SPD info: Controller=%u "
1719 "DIMM=%u\n", i, j);
1720 generic_spd_dump(
1721 &(pinfo->spd_installed_dimms[i][j]));
1722 printf("\n");
1723 }
1724 printf("\n");
1725 }
1726 printf("\n");
1727 }
1728
1729 /* STEP 2: DIMM Parameters */
1730 if (do_mask & STEP_COMPUTE_DIMM_PARMS) {
1731 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1732 if (!(ctrl_mask & (1 << i)))
1733 continue;
1734 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1735 if (!(dimm_mask & (1 << j)))
1736 continue;
1737 printf("DIMM parameters: Controller=%u "
1738 "DIMM=%u\n", i, j);
1739 print_dimm_parameters(
1740 &(pinfo->dimm_params[i][j]));
1741 printf("\n");
1742 }
1743 printf("\n");
1744 }
1745 printf("\n");
1746 }
1747
1748 /* STEP 3: Common Parameters */
1749 if (do_mask & STEP_COMPUTE_COMMON_PARMS) {
1750 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1751 if (!(ctrl_mask & (1 << i)))
1752 continue;
1753 printf("\"lowest common\" DIMM parameters: "
1754 "Controller=%u\n", i);
1755 print_lowest_common_dimm_parameters(
1756 &pinfo->common_timing_params[i]);
1757 printf("\n");
1758 }
1759 printf("\n");
1760 }
1761
1762 /* STEP 4: User Configuration Options */
1763 if (do_mask & STEP_GATHER_OPTS) {
1764 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1765 if (!(ctrl_mask & (1 << i)))
1766 continue;
1767 printf("User Config Options: Controller=%u\n", i);
1768 print_memctl_options(&pinfo->memctl_opts[i]);
1769 printf("\n");
1770 }
1771 printf("\n");
1772 }
1773
1774 /* STEP 5: Address assignment */
1775 if (do_mask & STEP_ASSIGN_ADDRESSES) {
1776 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1777 if (!(ctrl_mask & (1 << i)))
1778 continue;
1779 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
1780 printf("Address Assignment: Controller=%u "
1781 "DIMM=%u\n", i, j);
1782 printf("Don't have this functionality yet\n");
1783 }
1784 printf("\n");
1785 }
1786 printf("\n");
1787 }
1788
1789 /* STEP 6: computed controller register values */
1790 if (do_mask & STEP_COMPUTE_REGS) {
1791 for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
1792 if (!(ctrl_mask & (1 << i)))
1793 continue;
1794 printf("Computed Register Values: Controller=%u\n", i);
1795 print_fsl_memctl_config_regs(
1796 &pinfo->fsl_ddr_config_reg[i]);
1797 retval = check_fsl_memctl_config_regs(
1798 &pinfo->fsl_ddr_config_reg[i]);
1799 if (retval) {
1800 printf("check_fsl_memctl_config_regs "
1801 "result = %u\n", retval);
1802 }
1803 printf("\n");
1804 }
1805 printf("\n");
1806 }
1807 }
1808
1809 struct data_strings {
1810 const char *data_name;
1811 unsigned int step_mask;
1812 unsigned int dimm_number_required;
1813 };
1814
1815 #define DATA_OPTIONS(name, step, dimm) {#name, step, dimm}
1816
fsl_ddr_parse_interactive_cmd(char ** argv,int argc,unsigned int * pstep_mask,unsigned int * pctlr_mask,unsigned int * pdimm_mask,unsigned int * pdimm_number_required)1817 static unsigned int fsl_ddr_parse_interactive_cmd(
1818 char **argv,
1819 int argc,
1820 unsigned int *pstep_mask,
1821 unsigned int *pctlr_mask,
1822 unsigned int *pdimm_mask,
1823 unsigned int *pdimm_number_required
1824 ) {
1825
1826 static const struct data_strings options[] = {
1827 DATA_OPTIONS(spd, STEP_GET_SPD, 1),
1828 DATA_OPTIONS(dimmparms, STEP_COMPUTE_DIMM_PARMS, 1),
1829 DATA_OPTIONS(commonparms, STEP_COMPUTE_COMMON_PARMS, 0),
1830 DATA_OPTIONS(opts, STEP_GATHER_OPTS, 0),
1831 DATA_OPTIONS(addresses, STEP_ASSIGN_ADDRESSES, 0),
1832 DATA_OPTIONS(regs, STEP_COMPUTE_REGS, 0),
1833 };
1834 static const unsigned int n_opts = ARRAY_SIZE(options);
1835
1836 unsigned int i, j;
1837 unsigned int error = 0;
1838
1839 for (i = 1; i < argc; i++) {
1840 unsigned int matched = 0;
1841
1842 for (j = 0; j < n_opts; j++) {
1843 if (strcmp(options[j].data_name, argv[i]) != 0)
1844 continue;
1845 *pstep_mask |= options[j].step_mask;
1846 *pdimm_number_required =
1847 options[j].dimm_number_required;
1848 matched = 1;
1849 break;
1850 }
1851
1852 if (matched)
1853 continue;
1854
1855 if (argv[i][0] == 'c') {
1856 char c = argv[i][1];
1857 if (isdigit(c))
1858 *pctlr_mask |= 1 << (c - '0');
1859 continue;
1860 }
1861
1862 if (argv[i][0] == 'd') {
1863 char c = argv[i][1];
1864 if (isdigit(c))
1865 *pdimm_mask |= 1 << (c - '0');
1866 continue;
1867 }
1868
1869 printf("unknown arg %s\n", argv[i]);
1870 *pstep_mask = 0;
1871 error = 1;
1872 break;
1873 }
1874
1875 return error;
1876 }
1877
fsl_ddr_interactive_env_var_exists(void)1878 int fsl_ddr_interactive_env_var_exists(void)
1879 {
1880 char buffer[CONFIG_SYS_CBSIZE];
1881
1882 if (env_get_f("ddr_interactive", buffer, CONFIG_SYS_CBSIZE) >= 0)
1883 return 1;
1884
1885 return 0;
1886 }
1887
fsl_ddr_interactive(fsl_ddr_info_t * pinfo,int var_is_set)1888 unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set)
1889 {
1890 unsigned long long ddrsize;
1891 const char *prompt = "FSL DDR>";
1892 char buffer[CONFIG_SYS_CBSIZE];
1893 char buffer2[CONFIG_SYS_CBSIZE];
1894 char *p = NULL;
1895 char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
1896 int argc;
1897 unsigned int next_step = STEP_GET_SPD;
1898 const char *usage = {
1899 "commands:\n"
1900 "print print SPD and intermediate computed data\n"
1901 "reset reboot machine\n"
1902 "recompute reload SPD and options to default and recompute regs\n"
1903 "edit modify spd, parameter, or option\n"
1904 "compute recompute registers from current next_step to end\n"
1905 "copy copy parameters\n"
1906 "next_step shows current next_step\n"
1907 "help this message\n"
1908 "go program the memory controller and continue with u-boot\n"
1909 };
1910
1911 if (var_is_set) {
1912 if (env_get_f("ddr_interactive", buffer2,
1913 CONFIG_SYS_CBSIZE) > 0)
1914 p = buffer2;
1915 else
1916 var_is_set = 0;
1917 }
1918
1919 /*
1920 * The strategy for next_step is that it points to the next
1921 * step in the computation process that needs to be done.
1922 */
1923 while (1) {
1924 if (var_is_set) {
1925 char *pend = strchr(p, ';');
1926 if (pend) {
1927 /* found command separator, copy sub-command */
1928 *pend = '\0';
1929 strcpy(buffer, p);
1930 p = pend + 1;
1931 } else {
1932 /* separator not found, copy whole string */
1933 strcpy(buffer, p);
1934 p = NULL;
1935 var_is_set = 0;
1936 }
1937 } else {
1938 /*
1939 * No need to worry for buffer overflow here in
1940 * this function; cli_readline() maxes out at
1941 * CFG_CBSIZE
1942 */
1943 cli_readline_into_buffer(prompt, buffer, 0);
1944 }
1945 argc = cli_simple_parse_line(buffer, argv);
1946 if (argc == 0)
1947 continue;
1948
1949
1950 if (strcmp(argv[0], "help") == 0) {
1951 puts(usage);
1952 continue;
1953 }
1954
1955 if (strcmp(argv[0], "next_step") == 0) {
1956 printf("next_step = 0x%02X (%s)\n",
1957 next_step,
1958 step_to_string(next_step));
1959 continue;
1960 }
1961
1962 if (strcmp(argv[0], "copy") == 0) {
1963 unsigned int error = 0;
1964 unsigned int step_mask = 0;
1965 unsigned int src_ctlr_mask = 0;
1966 unsigned int src_dimm_mask = 0;
1967 unsigned int dimm_number_required = 0;
1968 unsigned int src_ctlr_num = 0;
1969 unsigned int src_dimm_num = 0;
1970 unsigned int dst_ctlr_num = -1;
1971 unsigned int dst_dimm_num = -1;
1972 unsigned int i, num_dest_parms;
1973
1974 if (argc == 1) {
1975 printf("copy <src c#> <src d#> <spd|dimmparms|commonparms|opts|addresses|regs> <dst c#> <dst d#>\n");
1976 continue;
1977 }
1978
1979 error = fsl_ddr_parse_interactive_cmd(
1980 argv, argc,
1981 &step_mask,
1982 &src_ctlr_mask,
1983 &src_dimm_mask,
1984 &dimm_number_required
1985 );
1986
1987 /* XXX: only dimm_number_required and step_mask will
1988 be used by this function. Parse the controller and
1989 DIMM number separately because it is easier. */
1990
1991 if (error)
1992 continue;
1993
1994 /* parse source destination controller / DIMM */
1995
1996 num_dest_parms = dimm_number_required ? 2 : 1;
1997
1998 for (i = 0; i < argc; i++) {
1999 if (argv[i][0] == 'c') {
2000 char c = argv[i][1];
2001 if (isdigit(c)) {
2002 src_ctlr_num = (c - '0');
2003 break;
2004 }
2005 }
2006 }
2007
2008 for (i = 0; i < argc; i++) {
2009 if (argv[i][0] == 'd') {
2010 char c = argv[i][1];
2011 if (isdigit(c)) {
2012 src_dimm_num = (c - '0');
2013 break;
2014 }
2015 }
2016 }
2017
2018 /* parse destination controller / DIMM */
2019
2020 for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2021 if (argv[i][0] == 'c') {
2022 char c = argv[i][1];
2023 if (isdigit(c)) {
2024 dst_ctlr_num = (c - '0');
2025 break;
2026 }
2027 }
2028 }
2029
2030 for (i = argc - 1; i >= argc - num_dest_parms; i--) {
2031 if (argv[i][0] == 'd') {
2032 char c = argv[i][1];
2033 if (isdigit(c)) {
2034 dst_dimm_num = (c - '0');
2035 break;
2036 }
2037 }
2038 }
2039
2040 /* TODO: validate inputs */
2041
2042 debug("src_ctlr_num = %u, src_dimm_num = %u, dst_ctlr_num = %u, dst_dimm_num = %u, step_mask = %x\n",
2043 src_ctlr_num, src_dimm_num, dst_ctlr_num, dst_dimm_num, step_mask);
2044
2045
2046 switch (step_mask) {
2047
2048 case STEP_GET_SPD:
2049 memcpy(&(pinfo->spd_installed_dimms[dst_ctlr_num][dst_dimm_num]),
2050 &(pinfo->spd_installed_dimms[src_ctlr_num][src_dimm_num]),
2051 sizeof(pinfo->spd_installed_dimms[0][0]));
2052 break;
2053
2054 case STEP_COMPUTE_DIMM_PARMS:
2055 memcpy(&(pinfo->dimm_params[dst_ctlr_num][dst_dimm_num]),
2056 &(pinfo->dimm_params[src_ctlr_num][src_dimm_num]),
2057 sizeof(pinfo->dimm_params[0][0]));
2058 break;
2059
2060 case STEP_COMPUTE_COMMON_PARMS:
2061 memcpy(&(pinfo->common_timing_params[dst_ctlr_num]),
2062 &(pinfo->common_timing_params[src_ctlr_num]),
2063 sizeof(pinfo->common_timing_params[0]));
2064 break;
2065
2066 case STEP_GATHER_OPTS:
2067 memcpy(&(pinfo->memctl_opts[dst_ctlr_num]),
2068 &(pinfo->memctl_opts[src_ctlr_num]),
2069 sizeof(pinfo->memctl_opts[0]));
2070 break;
2071
2072 /* someday be able to have addresses to copy addresses... */
2073
2074 case STEP_COMPUTE_REGS:
2075 memcpy(&(pinfo->fsl_ddr_config_reg[dst_ctlr_num]),
2076 &(pinfo->fsl_ddr_config_reg[src_ctlr_num]),
2077 sizeof(pinfo->memctl_opts[0]));
2078 break;
2079
2080 default:
2081 printf("unexpected step_mask value\n");
2082 }
2083
2084 continue;
2085
2086 }
2087
2088 if (strcmp(argv[0], "edit") == 0) {
2089 unsigned int error = 0;
2090 unsigned int step_mask = 0;
2091 unsigned int ctlr_mask = 0;
2092 unsigned int dimm_mask = 0;
2093 char *p_element = NULL;
2094 char *p_value = NULL;
2095 unsigned int dimm_number_required = 0;
2096 unsigned int ctrl_num;
2097 unsigned int dimm_num;
2098
2099 if (argc == 1) {
2100 /* Only the element and value must be last */
2101 printf("edit <c#> <d#> "
2102 "<spd|dimmparms|commonparms|opts|"
2103 "addresses|regs> <element> <value>\n");
2104 printf("for spd, specify byte number for "
2105 "element\n");
2106 continue;
2107 }
2108
2109 error = fsl_ddr_parse_interactive_cmd(
2110 argv, argc - 2,
2111 &step_mask,
2112 &ctlr_mask,
2113 &dimm_mask,
2114 &dimm_number_required
2115 );
2116
2117 if (error)
2118 continue;
2119
2120
2121 /* Check arguments */
2122
2123 /* ERROR: If no steps were found */
2124 if (step_mask == 0) {
2125 printf("Error: No valid steps were specified "
2126 "in argument.\n");
2127 continue;
2128 }
2129
2130 /* ERROR: If multiple steps were found */
2131 if (step_mask & (step_mask - 1)) {
2132 printf("Error: Multiple steps specified in "
2133 "argument.\n");
2134 continue;
2135 }
2136
2137 /* ERROR: Controller not specified */
2138 if (ctlr_mask == 0) {
2139 printf("Error: controller number not "
2140 "specified or no element and "
2141 "value specified\n");
2142 continue;
2143 }
2144
2145 if (ctlr_mask & (ctlr_mask - 1)) {
2146 printf("Error: multiple controllers "
2147 "specified, %X\n", ctlr_mask);
2148 continue;
2149 }
2150
2151 /* ERROR: DIMM number not specified */
2152 if (dimm_number_required && dimm_mask == 0) {
2153 printf("Error: DIMM number number not "
2154 "specified or no element and "
2155 "value specified\n");
2156 continue;
2157 }
2158
2159 if (dimm_mask & (dimm_mask - 1)) {
2160 printf("Error: multipled DIMMs specified\n");
2161 continue;
2162 }
2163
2164 p_element = argv[argc - 2];
2165 p_value = argv[argc - 1];
2166
2167 ctrl_num = __ilog2(ctlr_mask);
2168 dimm_num = __ilog2(dimm_mask);
2169
2170 switch (step_mask) {
2171 case STEP_GET_SPD:
2172 {
2173 unsigned int element_num;
2174 unsigned int value;
2175
2176 element_num = simple_strtoul(p_element,
2177 NULL, 0);
2178 value = simple_strtoul(p_value,
2179 NULL, 0);
2180 fsl_ddr_spd_edit(pinfo,
2181 ctrl_num,
2182 dimm_num,
2183 element_num,
2184 value);
2185 next_step = STEP_COMPUTE_DIMM_PARMS;
2186 }
2187 break;
2188
2189 case STEP_COMPUTE_DIMM_PARMS:
2190 fsl_ddr_dimm_parameters_edit(
2191 pinfo, ctrl_num, dimm_num,
2192 p_element, p_value);
2193 next_step = STEP_COMPUTE_COMMON_PARMS;
2194 break;
2195
2196 case STEP_COMPUTE_COMMON_PARMS:
2197 lowest_common_dimm_parameters_edit(pinfo,
2198 ctrl_num, p_element, p_value);
2199 next_step = STEP_GATHER_OPTS;
2200 break;
2201
2202 case STEP_GATHER_OPTS:
2203 fsl_ddr_options_edit(pinfo, ctrl_num,
2204 p_element, p_value);
2205 next_step = STEP_ASSIGN_ADDRESSES;
2206 break;
2207
2208 case STEP_ASSIGN_ADDRESSES:
2209 printf("editing of address assignment "
2210 "not yet implemented\n");
2211 break;
2212
2213 case STEP_COMPUTE_REGS:
2214 {
2215 fsl_ddr_regs_edit(pinfo,
2216 ctrl_num,
2217 p_element,
2218 p_value);
2219 next_step = STEP_PROGRAM_REGS;
2220 }
2221 break;
2222
2223 default:
2224 printf("programming error\n");
2225 while (1)
2226 ;
2227 break;
2228 }
2229 continue;
2230 }
2231
2232 if (strcmp(argv[0], "reset") == 0) {
2233 /*
2234 * Reboot machine.
2235 * Args don't seem to matter because this
2236 * doesn't return
2237 */
2238 do_reset(NULL, 0, 0, NULL);
2239 printf("Reset didn't work\n");
2240 }
2241
2242 if (strcmp(argv[0], "recompute") == 0) {
2243 /*
2244 * Recalculate everything, starting with
2245 * loading SPD EEPROM from DIMMs
2246 */
2247 next_step = STEP_GET_SPD;
2248 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2249 continue;
2250 }
2251
2252 if (strcmp(argv[0], "compute") == 0) {
2253 /*
2254 * Compute rest of steps starting at
2255 * the current next_step/
2256 */
2257 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2258 continue;
2259 }
2260
2261 if (strcmp(argv[0], "print") == 0) {
2262 unsigned int error = 0;
2263 unsigned int step_mask = 0;
2264 unsigned int ctlr_mask = 0;
2265 unsigned int dimm_mask = 0;
2266 unsigned int dimm_number_required = 0;
2267
2268 if (argc == 1) {
2269 printf("print [c<n>] [d<n>] [spd] [dimmparms] "
2270 "[commonparms] [opts] [addresses] [regs]\n");
2271 continue;
2272 }
2273
2274 error = fsl_ddr_parse_interactive_cmd(
2275 argv, argc,
2276 &step_mask,
2277 &ctlr_mask,
2278 &dimm_mask,
2279 &dimm_number_required
2280 );
2281
2282 if (error)
2283 continue;
2284
2285 /* If no particular controller was found, print all */
2286 if (ctlr_mask == 0)
2287 ctlr_mask = 0xFF;
2288
2289 /* If no particular dimm was found, print all dimms. */
2290 if (dimm_mask == 0)
2291 dimm_mask = 0xFF;
2292
2293 /* If no steps were found, print all steps. */
2294 if (step_mask == 0)
2295 step_mask = STEP_ALL;
2296
2297 fsl_ddr_printinfo(pinfo, ctlr_mask,
2298 dimm_mask, step_mask);
2299 continue;
2300 }
2301
2302 if (strcmp(argv[0], "go") == 0) {
2303 if (next_step)
2304 ddrsize = fsl_ddr_compute(pinfo, next_step, 0);
2305 break;
2306 }
2307
2308 printf("unknown command %s\n", argv[0]);
2309 }
2310
2311 debug("end of memory = %llu\n", (u64)ddrsize);
2312
2313 return ddrsize;
2314 }
2315