1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. 4 * 5 * Dave Liu <daveliu@freescale.com> 6 * based on source code of Shlomi Gridish 7 */ 8 9 #ifndef __UEC_H__ 10 #define __UEC_H__ 11 12 #include "uccf.h" 13 #include <fsl_qe.h> 14 #include <phy.h> 15 16 #define MAX_TX_THREADS 8 17 #define MAX_RX_THREADS 8 18 #define MAX_TX_QUEUES 8 19 #define MAX_RX_QUEUES 8 20 #define MAX_PREFETCHED_BDS 4 21 #define MAX_IPH_OFFSET_ENTRY 8 22 #define MAX_ENET_INIT_PARAM_ENTRIES_RX 9 23 #define MAX_ENET_INIT_PARAM_ENTRIES_TX 8 24 25 /* UEC UPSMR (Protocol Specific Mode Register) 26 */ 27 #define UPSMR_ECM 0x04000000 /* Enable CAM Miss */ 28 #define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */ 29 #define UPSMR_PRO 0x00400000 /* Promiscuous */ 30 #define UPSMR_CAP 0x00200000 /* CAM polarity */ 31 #define UPSMR_RSH 0x00100000 /* Receive Short Frames */ 32 #define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */ 33 #define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */ 34 #define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */ 35 #define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */ 36 #define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */ 37 #define UPSMR_CAM 0x00000400 /* CAM Address Matching */ 38 #define UPSMR_BRO 0x00000200 /* Broadcast Address */ 39 #define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */ 40 #define UPSMR_SGMM 0x00000020 /* SGMII mode */ 41 42 #define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1) 43 44 /* UEC MACCFG1 (MAC Configuration 1 Register) 45 */ 46 #define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */ 47 #define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */ 48 #define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */ 49 #define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */ 50 #define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */ 51 #define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */ 52 53 #define MACCFG1_INIT_VALUE (0) 54 55 /* UEC MACCFG2 (MAC Configuration 2 Register) 56 */ 57 #define MACCFG2_PREL 0x00007000 58 #define MACCFG2_PREL_SHIFT (31 - 19) 59 #define MACCFG2_PREL_MASK 0x0000f000 60 #define MACCFG2_SRP 0x00000080 61 #define MACCFG2_STP 0x00000040 62 #define MACCFG2_RESERVED_1 0x00000020 /* must be set */ 63 #define MACCFG2_LC 0x00000010 /* Length Check */ 64 #define MACCFG2_MPE 0x00000008 65 #define MACCFG2_FDX 0x00000001 /* Full Duplex */ 66 #define MACCFG2_FDX_MASK 0x00000001 67 #define MACCFG2_PAD_CRC 0x00000004 68 #define MACCFG2_CRC_EN 0x00000002 69 #define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000 70 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002 71 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004 72 #define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100 73 #define MACCFG2_INTERFACE_MODE_BYTE 0x00000200 74 #define MACCFG2_INTERFACE_MODE_MASK 0x00000300 75 76 #define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \ 77 MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX) 78 79 /* UEC Event Register */ 80 #define UCCE_MPD 0x80000000 81 #define UCCE_SCAR 0x40000000 82 #define UCCE_GRA 0x20000000 83 #define UCCE_CBPR 0x10000000 84 #define UCCE_BSY 0x08000000 85 #define UCCE_RXC 0x04000000 86 #define UCCE_TXC 0x02000000 87 #define UCCE_TXE 0x01000000 88 #define UCCE_TXB7 0x00800000 89 #define UCCE_TXB6 0x00400000 90 #define UCCE_TXB5 0x00200000 91 #define UCCE_TXB4 0x00100000 92 #define UCCE_TXB3 0x00080000 93 #define UCCE_TXB2 0x00040000 94 #define UCCE_TXB1 0x00020000 95 #define UCCE_TXB0 0x00010000 96 #define UCCE_RXB7 0x00008000 97 #define UCCE_RXB6 0x00004000 98 #define UCCE_RXB5 0x00002000 99 #define UCCE_RXB4 0x00001000 100 #define UCCE_RXB3 0x00000800 101 #define UCCE_RXB2 0x00000400 102 #define UCCE_RXB1 0x00000200 103 #define UCCE_RXB0 0x00000100 104 #define UCCE_RXF7 0x00000080 105 #define UCCE_RXF6 0x00000040 106 #define UCCE_RXF5 0x00000020 107 #define UCCE_RXF4 0x00000010 108 #define UCCE_RXF3 0x00000008 109 #define UCCE_RXF2 0x00000004 110 #define UCCE_RXF1 0x00000002 111 #define UCCE_RXF0 0x00000001 112 113 #define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \ 114 UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0) 115 #define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \ 116 UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0) 117 #define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \ 118 UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0) 119 #define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \ 120 UCCE_RXC | UCCE_TXC | UCCE_TXE) 121 122 /* UEC TEMODR Register */ 123 #define TEMODER_SCHEDULER_ENABLE 0x2000 124 #define TEMODER_IP_CHECKSUM_GENERATE 0x0400 125 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200 126 #define TEMODER_RMON_STATISTICS 0x0100 127 #define TEMODER_NUM_OF_QUEUES_SHIFT (15 - 15) 128 129 #define TEMODER_INIT_VALUE 0xc000 130 131 /* UEC REMODR Register */ 132 #define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000 133 #define REMODER_RX_EXTENDED_FEATURES 0x80000000 134 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31 - 9) 135 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31 - 10) 136 #define REMODER_RX_QOS_MODE_SHIFT (31 - 15) 137 #define REMODER_RMON_STATISTICS 0x00001000 138 #define REMODER_RX_EXTENDED_FILTERING 0x00000800 139 #define REMODER_NUM_OF_QUEUES_SHIFT (31 - 23) 140 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008 141 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004 142 #define REMODER_IP_CHECKSUM_CHECK 0x00000002 143 #define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001 144 145 #define REMODER_INIT_VALUE 0 146 147 /* BMRx - Bus Mode Register */ 148 #define BMR_GLB 0x20 149 #define BMR_BO_BE 0x10 150 #define BMR_DTB_SECONDARY_BUS 0x02 151 #define BMR_BDB_SECONDARY_BUS 0x01 152 153 #define BMR_SHIFT 24 154 #define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE) 155 156 /* UEC UCCS (Ethernet Status Register) 157 */ 158 #define UCCS_BPR 0x02 159 #define UCCS_PAU 0x02 160 #define UCCS_MPD 0x01 161 162 /* UEC MIIMCFG (MII Management Configuration Register) 163 */ 164 #define MIIMCFG_RESET_MANAGEMENT 0x80000000 165 #define MIIMCFG_NO_PREAMBLE 0x00000010 166 #define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31) 167 #define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f 168 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001 169 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002 170 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003 171 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004 172 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005 173 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006 174 #define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007 175 176 #define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \ 177 MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 178 179 /* UEC MIIMCOM (MII Management Command Register) 180 */ 181 #define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */ 182 #define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */ 183 184 /* UEC MIIMADD (MII Management Address Register) 185 */ 186 #define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23) 187 #define MIIMADD_PHY_REGISTER_SHIFT (31 - 31) 188 189 /* UEC MIIMCON (MII Management Control Register) 190 */ 191 #define MIIMCON_PHY_CONTROL_SHIFT (31 - 31) 192 #define MIIMCON_PHY_STATUS_SHIFT (31 - 31) 193 194 /* UEC MIIMIND (MII Management Indicator Register) 195 */ 196 #define MIIMIND_NOT_VALID 0x00000004 197 #define MIIMIND_SCAN 0x00000002 198 #define MIIMIND_BUSY 0x00000001 199 200 /* UEC UTBIPAR (Ten Bit Interface Physical Address Register) 201 */ 202 #define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31) 203 #define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f 204 205 /* UEC UESCR (Ethernet Statistics Control Register) 206 */ 207 #define UESCR_AUTOZ 0x8000 208 #define UESCR_CLRCNT 0x4000 209 #define UESCR_MAXCOV_SHIFT (15 - 7) 210 #define UESCR_SCOV_SHIFT (15 - 15) 211 212 /****** Tx data struct collection ******/ 213 /* Tx thread data, each Tx thread has one this struct. */ 214 struct uec_thread_data_tx { 215 u8 res0[136]; 216 } __packed; 217 218 /* Tx thread parameter, each Tx thread has one this struct. */ 219 struct uec_thread_tx_pram { 220 u8 res0[64]; 221 } __packed; 222 223 /* Send queue queue-descriptor, each Tx queue has one this QD */ 224 struct uec_send_queue_qd { 225 u32 bd_ring_base; /* pointer to BD ring base address */ 226 u8 res0[0x8]; 227 u32 last_bd_completed_address; /* last entry in BD ring */ 228 u8 res1[0x30]; 229 } __packed; 230 231 /* Send queue memory region */ 232 struct uec_send_queue_mem_region { 233 struct uec_send_queue_qd sqqd[MAX_TX_QUEUES]; 234 } __packed; 235 236 /* Scheduler struct */ 237 struct uec_scheduler { 238 u16 cpucount0; /* CPU packet counter */ 239 u16 cpucount1; /* CPU packet counter */ 240 u16 cecount0; /* QE packet counter */ 241 u16 cecount1; /* QE packet counter */ 242 u16 cpucount2; /* CPU packet counter */ 243 u16 cpucount3; /* CPU packet counter */ 244 u16 cecount2; /* QE packet counter */ 245 u16 cecount3; /* QE packet counter */ 246 u16 cpucount4; /* CPU packet counter */ 247 u16 cpucount5; /* CPU packet counter */ 248 u16 cecount4; /* QE packet counter */ 249 u16 cecount5; /* QE packet counter */ 250 u16 cpucount6; /* CPU packet counter */ 251 u16 cpucount7; /* CPU packet counter */ 252 u16 cecount6; /* QE packet counter */ 253 u16 cecount7; /* QE packet counter */ 254 u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */ 255 u32 rtsrshadow; /* temporary variable handled by QE */ 256 u32 time; /* temporary variable handled by QE */ 257 u32 ttl; /* temporary variable handled by QE */ 258 u32 mblinterval; /* max burst length interval */ 259 u16 nortsrbytetime; /* normalized value of byte time in tsr units */ 260 u8 fracsiz; 261 u8 res0[1]; 262 u8 strictpriorityq; /* Strict Priority Mask register */ 263 u8 txasap; /* Transmit ASAP register */ 264 u8 extrabw; /* Extra BandWidth register */ 265 u8 oldwfqmask; /* temporary variable handled by QE */ 266 u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */ 267 u32 minw; /* temporary variable handled by QE */ 268 u8 res1[0x70 - 0x64]; 269 } __packed; 270 271 /* Tx firmware counters */ 272 struct uec_tx_firmware_statistics_pram { 273 u32 sicoltx; /* single collision */ 274 u32 mulcoltx; /* multiple collision */ 275 u32 latecoltxfr; /* late collision */ 276 u32 frabortduecol; /* frames aborted due to tx collision */ 277 u32 frlostinmactxer; /* frames lost due to internal MAC error tx */ 278 u32 carriersenseertx; /* carrier sense error */ 279 u32 frtxok; /* frames transmitted OK */ 280 u32 txfrexcessivedefer; 281 u32 txpkts256; /* total packets(including bad) 256~511 B */ 282 u32 txpkts512; /* total packets(including bad) 512~1023B */ 283 u32 txpkts1024; /* total packets(including bad) 1024~1518B */ 284 u32 txpktsjumbo; /* total packets(including bad) >1024 */ 285 } __packed; 286 287 /* Tx global parameter table */ 288 struct uec_tx_global_pram { 289 u16 temoder; 290 u8 res0[0x38 - 0x02]; 291 u32 sqptr; 292 u32 schedulerbasepointer; 293 u32 txrmonbaseptr; 294 u32 tstate; 295 u8 iphoffset[MAX_IPH_OFFSET_ENTRY]; 296 u32 vtagtable[0x8]; 297 u32 tqptr; 298 u8 res2[0x80 - 0x74]; 299 } __packed; 300 301 /****** Rx data struct collection ******/ 302 /* Rx thread data, each Rx thread has one this struct. */ 303 struct uec_thread_data_rx { 304 u8 res0[40]; 305 } __packed; 306 307 /* Rx thread parameter, each Rx thread has one this struct. */ 308 struct uec_thread_rx_pram { 309 u8 res0[128]; 310 } __packed; 311 312 /* Rx firmware counters */ 313 struct uec_rx_firmware_statistics_pram { 314 u32 frrxfcser; /* frames with crc error */ 315 u32 fraligner; /* frames with alignment error */ 316 u32 inrangelenrxer; /* in range length error */ 317 u32 outrangelenrxer; /* out of range length error */ 318 u32 frtoolong; /* frame too long */ 319 u32 runt; /* runt */ 320 u32 verylongevent; /* very long event */ 321 u32 symbolerror; /* symbol error */ 322 u32 dropbsy; /* drop because of BD not ready */ 323 u8 res0[0x8]; 324 u32 mismatchdrop; /* drop because of MAC filtering */ 325 u32 underpkts; /* total frames less than 64 octets */ 326 u32 pkts256; /* total frames(including bad)256~511 B */ 327 u32 pkts512; /* total frames(including bad)512~1023 B */ 328 u32 pkts1024; /* total frames(including bad)1024~1518 B */ 329 u32 pktsjumbo; /* total frames(including bad) >1024 B */ 330 u32 frlossinmacer; 331 u32 pausefr; /* pause frames */ 332 u8 res1[0x4]; 333 u32 removevlan; 334 u32 replacevlan; 335 u32 insertvlan; 336 } __packed; 337 338 /* Rx interrupt coalescing entry, each Rx queue has one this entry. */ 339 struct uec_rx_interrupt_coalescing_entry { 340 u32 maxvalue; 341 u32 counter; 342 } __packed; 343 344 struct uec_rx_interrupt_coalescing_table { 345 struct uec_rx_interrupt_coalescing_entry entry[MAX_RX_QUEUES]; 346 } __packed; 347 348 /* RxBD queue entry, each Rx queue has one this entry. */ 349 struct uec_rx_bd_queues_entry { 350 u32 bdbaseptr; /* BD base pointer */ 351 u32 bdptr; /* BD pointer */ 352 u32 externalbdbaseptr; /* external BD base pointer */ 353 u32 externalbdptr; /* external BD pointer */ 354 } __packed; 355 356 /* Rx global parameter table */ 357 struct uec_rx_global_pram { 358 u32 remoder; /* ethernet mode reg. */ 359 u32 rqptr; /* base pointer to the Rx Queues */ 360 u32 res0[0x1]; 361 u8 res1[0x20 - 0xc]; 362 u16 typeorlen; 363 u8 res2[0x1]; 364 u8 rxgstpack; /* ack on GRACEFUL STOP RX command */ 365 u32 rxrmonbaseptr; /* Rx RMON statistics base */ 366 u8 res3[0x30 - 0x28]; 367 u32 intcoalescingptr; /* Interrupt coalescing table pointer */ 368 u8 res4[0x36 - 0x34]; 369 u8 rstate; 370 u8 res5[0x46 - 0x37]; 371 u16 mrblr; /* max receive buffer length reg. */ 372 u32 rbdqptr; /* RxBD parameter table description */ 373 u16 mflr; /* max frame length reg. */ 374 u16 minflr; /* min frame length reg. */ 375 u16 maxd1; /* max dma1 length reg. */ 376 u16 maxd2; /* max dma2 length reg. */ 377 u32 ecamptr; /* external CAM address */ 378 u32 l2qt; /* VLAN priority mapping table. */ 379 u32 l3qt[0x8]; /* IP priority mapping table. */ 380 u16 vlantype; /* vlan type */ 381 u16 vlantci; /* default vlan tci */ 382 u8 addressfiltering[64];/* address filtering data structure */ 383 u32 exf_global_param; /* extended filtering global parameters */ 384 u8 res6[0x100 - 0xc4]; /* Initialize to zero */ 385 } __packed; 386 387 #define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01 388 389 /****** UEC common ******/ 390 /* UCC statistics - hardware counters */ 391 struct uec_hardware_statistics { 392 u32 tx64; 393 u32 tx127; 394 u32 tx255; 395 u32 rx64; 396 u32 rx127; 397 u32 rx255; 398 u32 txok; 399 u16 txcf; 400 u32 tmca; 401 u32 tbca; 402 u32 rxfok; 403 u32 rxbok; 404 u32 rbyt; 405 u32 rmca; 406 u32 rbca; 407 } __packed; 408 409 /* InitEnet command parameter */ 410 struct uec_init_cmd_pram { 411 u8 resinit0; 412 u8 resinit1; 413 u8 resinit2; 414 u8 resinit3; 415 u16 resinit4; 416 u8 res1[0x1]; 417 u8 largestexternallookupkeysize; 418 u32 rgftgfrxglobal; 419 u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */ 420 u8 res2[0x38 - 0x30]; 421 u32 txglobal; /* tx global */ 422 u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */ 423 u8 res3[0x1]; 424 } __packed; 425 426 #define ENET_INIT_PARAM_RGF_SHIFT (32 - 4) 427 #define ENET_INIT_PARAM_TGF_SHIFT (32 - 8) 428 429 #define ENET_INIT_PARAM_RISC_MASK 0x0000003f 430 #define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0 431 #define ENET_INIT_PARAM_SNUM_MASK 0xff000000 432 #define ENET_INIT_PARAM_SNUM_SHIFT 24 433 434 #define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06 435 #define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30 436 #define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff 437 #define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00 438 #define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400 439 440 /* structure representing 82xx Address Filtering Enet Address in PRAM */ 441 struct uec_82xx_enet_addr { 442 u8 res1[0x2]; 443 u16 h; /* address (MSB) */ 444 u16 m; /* address */ 445 u16 l; /* address (LSB) */ 446 } __packed; 447 448 /* structure representing 82xx Address Filtering PRAM */ 449 struct uec_82xx_add_filtering_pram { 450 u32 iaddr_h; /* individual address filter, high */ 451 u32 iaddr_l; /* individual address filter, low */ 452 u32 gaddr_h; /* group address filter, high */ 453 u32 gaddr_l; /* group address filter, low */ 454 struct uec_82xx_enet_addr taddr; 455 struct uec_82xx_enet_addr paddr[4]; 456 u8 res0[0x40 - 0x38]; 457 } __packed; 458 459 /* Buffer Descriptor */ 460 struct buffer_descriptor { 461 u16 status; 462 u16 len; 463 u32 data; 464 } __packed; 465 466 #define SIZEOFBD sizeof(struct buffer_descriptor) 467 468 /* Common BD flags */ 469 #define BD_WRAP 0x2000 470 #define BD_INT 0x1000 471 #define BD_LAST 0x0800 472 #define BD_CLEAN 0x3000 473 474 /* TxBD status flags */ 475 #define TX_BD_READY 0x8000 476 #define TX_BD_PADCRC 0x4000 477 #define TX_BD_WRAP BD_WRAP 478 #define TX_BD_INT BD_INT 479 #define TX_BD_LAST BD_LAST 480 #define TX_BD_TXCRC 0x0400 481 #define TX_BD_DEF 0x0200 482 #define TX_BD_PP 0x0100 483 #define TX_BD_LC 0x0080 484 #define TX_BD_RL 0x0040 485 #define TX_BD_RC 0x003C 486 #define TX_BD_UNDERRUN 0x0002 487 #define TX_BD_TRUNC 0x0001 488 489 #define TX_BD_ERROR (TX_BD_UNDERRUN | TX_BD_TRUNC) 490 491 /* RxBD status flags */ 492 #define RX_BD_EMPTY 0x8000 493 #define RX_BD_OWNER 0x4000 494 #define RX_BD_WRAP BD_WRAP 495 #define RX_BD_INT BD_INT 496 #define RX_BD_LAST BD_LAST 497 #define RX_BD_FIRST 0x0400 498 #define RX_BD_CMR 0x0200 499 #define RX_BD_MISS 0x0100 500 #define RX_BD_BCAST 0x0080 501 #define RX_BD_MCAST 0x0040 502 #define RX_BD_LG 0x0020 503 #define RX_BD_NO 0x0010 504 #define RX_BD_SHORT 0x0008 505 #define RX_BD_CRCERR 0x0004 506 #define RX_BD_OVERRUN 0x0002 507 #define RX_BD_IPCH 0x0001 508 509 #define RX_BD_ERROR (RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \ 510 RX_BD_CRCERR | RX_BD_OVERRUN) 511 512 /* BD access macros */ 513 #define BD_STATUS(_bd) (in_be16(&((_bd)->status))) 514 #define BD_STATUS_SET(_bd, _v) (out_be16(&((_bd)->status), _v)) 515 #define BD_LENGTH(_bd) (in_be16(&((_bd)->len))) 516 #define BD_LENGTH_SET(_bd, _v) (out_be16(&((_bd)->len), _v)) 517 #define BD_DATA_CLEAR(_bd) (out_be32(&((_bd)->data), 0)) 518 #define BD_DATA(_bd) ((u8 *)(((_bd)->data))) 519 #define BD_DATA_SET(_bd, _data) (out_be32(&((_bd)->data), (u32)_data)) 520 #define BD_ADVANCE(_bd, _status, _base) \ 521 (((_status) & BD_WRAP) ? (_bd) = \ 522 ((struct buffer_descriptor *)(_base)) : ++(_bd)) 523 524 /* Rx Prefetched BDs */ 525 struct uec_rx_pref_bds { 526 struct buffer_descriptor bd[MAX_PREFETCHED_BDS]; /* prefetched bd */ 527 } __packed; 528 529 /* Alignments */ 530 #define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64 531 #define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64 532 #define UEC_THREAD_RX_PRAM_ALIGNMENT 128 533 #define UEC_THREAD_TX_PRAM_ALIGNMENT 64 534 #define UEC_THREAD_DATA_ALIGNMENT 256 535 #define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32 536 #define UEC_SCHEDULER_ALIGNMENT 4 537 #define UEC_TX_STATISTICS_ALIGNMENT 4 538 #define UEC_RX_STATISTICS_ALIGNMENT 4 539 #define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4 540 #define UEC_RX_BD_QUEUES_ALIGNMENT 8 541 #define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128 542 #define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4 543 #define UEC_RX_BD_RING_ALIGNMENT 32 544 #define UEC_TX_BD_RING_ALIGNMENT 32 545 #define UEC_MRBLR_ALIGNMENT 128 546 #define UEC_RX_BD_RING_SIZE_ALIGNMENT 4 547 #define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32 548 #define UEC_RX_DATA_BUF_ALIGNMENT 64 549 550 #define UEC_VLAN_PRIORITY_MAX 8 551 #define UEC_IP_PRIORITY_MAX 64 552 #define UEC_TX_VTAG_TABLE_ENTRY_MAX 8 553 #define UEC_RX_BD_RING_SIZE_MIN 8 554 #define UEC_TX_BD_RING_SIZE_MIN 2 555 556 /* TBI / MII Set Register */ 557 enum enet_tbi_mii_reg { 558 ENET_TBI_MII_CR = 0x00, 559 ENET_TBI_MII_SR = 0x01, 560 ENET_TBI_MII_ANA = 0x04, 561 ENET_TBI_MII_ANLPBPA = 0x05, 562 ENET_TBI_MII_ANEX = 0x06, 563 ENET_TBI_MII_ANNPT = 0x07, 564 ENET_TBI_MII_ANLPANP = 0x08, 565 ENET_TBI_MII_EXST = 0x0F, 566 ENET_TBI_MII_JD = 0x10, 567 ENET_TBI_MII_TBICON = 0x11 568 }; 569 570 /* TBI MDIO register bit fields*/ 571 #define TBICON_CLK_SELECT 0x0020 572 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 573 #define TBIANA_SYMMETRIC_PAUSE 0x0080 574 #define TBIANA_HALF_DUPLEX 0x0040 575 #define TBIANA_FULL_DUPLEX 0x0020 576 #define TBICR_PHY_RESET 0x8000 577 #define TBICR_ANEG_ENABLE 0x1000 578 #define TBICR_RESTART_ANEG 0x0200 579 #define TBICR_FULL_DUPLEX 0x0100 580 #define TBICR_SPEED1_SET 0x0040 581 582 #define TBIANA_SETTINGS ( \ 583 TBIANA_ASYMMETRIC_PAUSE \ 584 | TBIANA_SYMMETRIC_PAUSE \ 585 | TBIANA_FULL_DUPLEX \ 586 ) 587 588 #define TBICR_SETTINGS ( \ 589 TBICR_PHY_RESET \ 590 | TBICR_ANEG_ENABLE \ 591 | TBICR_FULL_DUPLEX \ 592 | TBICR_SPEED1_SET \ 593 ) 594 595 /* UEC number of threads */ 596 enum uec_num_of_threads { 597 UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */ 598 UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */ 599 UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */ 600 UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */ 601 UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */ 602 }; 603 604 /* UEC initialization info struct */ 605 #define STD_UEC_INFO(num) \ 606 { \ 607 .uf_info = { \ 608 .ucc_num = CONFIG_SYS_UEC##num##_UCC_NUM,\ 609 .rx_clock = CONFIG_SYS_UEC##num##_RX_CLK, \ 610 .tx_clock = CONFIG_SYS_UEC##num##_TX_CLK, \ 611 .eth_type = CONFIG_SYS_UEC##num##_ETH_TYPE,\ 612 }, \ 613 .num_threads_tx = UEC_NUM_OF_THREADS_1, \ 614 .num_threads_rx = UEC_NUM_OF_THREADS_1, \ 615 .risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ 616 .risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \ 617 .tx_bd_ring_len = 16, \ 618 .rx_bd_ring_len = 16, \ 619 .phy_address = CONFIG_SYS_UEC##num##_PHY_ADDR, \ 620 .enet_interface_type = CONFIG_SYS_UEC##num##_INTERFACE_TYPE, \ 621 .speed = CONFIG_SYS_UEC##num##_INTERFACE_SPEED, \ 622 } 623 624 struct uec_inf { 625 struct ucc_fast_inf uf_info; 626 enum uec_num_of_threads num_threads_tx; 627 enum uec_num_of_threads num_threads_rx; 628 unsigned int risc_tx; 629 unsigned int risc_rx; 630 u16 rx_bd_ring_len; 631 u16 tx_bd_ring_len; 632 u8 phy_address; 633 phy_interface_t enet_interface_type; 634 int speed; 635 }; 636 637 /* UEC driver initialized info */ 638 #define MAX_RXBUF_LEN 1536 639 #define MAX_FRAME_LEN 1518 640 #define MIN_FRAME_LEN 64 641 #define MAX_DMA1_LEN 1520 642 #define MAX_DMA2_LEN 1520 643 644 /* UEC driver private struct */ 645 struct uec_priv { 646 struct uec_inf *uec_info; 647 struct ucc_fast_priv *uccf; 648 struct eth_device *dev; 649 uec_t *uec_regs; 650 /* enet init command parameter */ 651 struct uec_init_cmd_pram *p_init_enet_param; 652 u32 init_enet_param_offset; 653 /* Rx and Tx parameter */ 654 struct uec_rx_global_pram *p_rx_glbl_pram; 655 u32 rx_glbl_pram_offset; 656 struct uec_tx_global_pram *p_tx_glbl_pram; 657 u32 tx_glbl_pram_offset; 658 struct uec_send_queue_mem_region *p_send_q_mem_reg; 659 u32 send_q_mem_reg_offset; 660 struct uec_thread_data_tx *p_thread_data_tx; 661 u32 thread_dat_tx_offset; 662 struct uec_thread_data_rx *p_thread_data_rx; 663 u32 thread_dat_rx_offset; 664 struct uec_rx_bd_queues_entry *p_rx_bd_qs_tbl; 665 u32 rx_bd_qs_tbl_offset; 666 /* BDs specific */ 667 u8 *p_tx_bd_ring; 668 u32 tx_bd_ring_offset; 669 u8 *p_rx_bd_ring; 670 u32 rx_bd_ring_offset; 671 u8 *p_rx_buf; 672 u32 rx_buf_offset; 673 struct buffer_descriptor *tx_bd; 674 struct buffer_descriptor *rx_bd; 675 /* Status */ 676 int mac_tx_enabled; 677 int mac_rx_enabled; 678 int grace_stopped_tx; 679 int grace_stopped_rx; 680 int the_first_run; 681 #if !defined(CONFIG_DM) 682 /* PHY specific */ 683 struct uec_mii_info *mii_info; 684 int oldspeed; 685 int oldduplex; 686 int oldlink; 687 #endif 688 }; 689 690 int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info); 691 int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num); 692 int uec_standard_init(struct bd_info *bis); 693 #endif /* __UEC_H__ */ 694