1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 4 * Author: Elaine <zhangqing@rock-chips.com> 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H 8 #define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H 9 10 /* core clocks */ 11 #define PLL_APLL 1 12 #define PLL_DPLL 2 13 #define PLL_CPLL 3 14 #define PLL_NPLL 4 15 #define APLL_BOOST_H 5 16 #define APLL_BOOST_L 6 17 #define ARMCLK 7 18 19 /* sclk gates (special clocks) */ 20 #define USB480M 14 21 #define SCLK_PDM 15 22 #define SCLK_I2S0_TX 16 23 #define SCLK_I2S0_TX_OUT 17 24 #define SCLK_I2S0_RX 18 25 #define SCLK_I2S0_RX_OUT 19 26 #define SCLK_I2S1 20 27 #define SCLK_I2S1_OUT 21 28 #define SCLK_I2S2 22 29 #define SCLK_I2S2_OUT 23 30 #define SCLK_UART1 24 31 #define SCLK_UART2 25 32 #define SCLK_UART3 26 33 #define SCLK_UART4 27 34 #define SCLK_UART5 28 35 #define SCLK_I2C0 29 36 #define SCLK_I2C1 30 37 #define SCLK_I2C2 31 38 #define SCLK_I2C3 32 39 #define SCLK_I2C4 33 40 #define SCLK_PWM0 34 41 #define SCLK_PWM1 35 42 #define SCLK_SPI0 36 43 #define SCLK_SPI1 37 44 #define SCLK_TIMER0 38 45 #define SCLK_TIMER1 39 46 #define SCLK_TIMER2 40 47 #define SCLK_TIMER3 41 48 #define SCLK_TIMER4 42 49 #define SCLK_TIMER5 43 50 #define SCLK_TSADC 44 51 #define SCLK_SARADC 45 52 #define SCLK_OTP 46 53 #define SCLK_OTP_USR 47 54 #define SCLK_CRYPTO 48 55 #define SCLK_CRYPTO_APK 49 56 #define SCLK_DDRC 50 57 #define SCLK_ISP 51 58 #define SCLK_CIF_OUT 52 59 #define SCLK_RGA_CORE 53 60 #define SCLK_VOPB_PWM 54 61 #define SCLK_NANDC 55 62 #define SCLK_SDIO 56 63 #define SCLK_EMMC 57 64 #define SCLK_SFC 58 65 #define SCLK_SDMMC 59 66 #define SCLK_OTG_ADP 60 67 #define SCLK_GMAC_SRC 61 68 #define SCLK_GMAC 62 69 #define SCLK_GMAC_RX_TX 63 70 #define SCLK_MAC_REF 64 71 #define SCLK_MAC_REFOUT 65 72 #define SCLK_MAC_OUT 66 73 #define SCLK_SDMMC_DRV 67 74 #define SCLK_SDMMC_SAMPLE 68 75 #define SCLK_SDIO_DRV 69 76 #define SCLK_SDIO_SAMPLE 70 77 #define SCLK_EMMC_DRV 71 78 #define SCLK_EMMC_SAMPLE 72 79 #define SCLK_GPU 73 80 #define SCLK_PVTM 74 81 #define SCLK_CORE_VPU 75 82 #define SCLK_GMAC_RMII 76 83 #define SCLK_UART2_SRC 77 84 #define SCLK_NANDC_DIV 78 85 #define SCLK_NANDC_DIV50 79 86 #define SCLK_SDIO_DIV 80 87 #define SCLK_SDIO_DIV50 81 88 #define SCLK_EMMC_DIV 82 89 #define SCLK_EMMC_DIV50 83 90 91 /* dclk gates */ 92 #define DCLK_VOPB 150 93 #define DCLK_VOPL 151 94 95 /* aclk gates */ 96 #define ACLK_GPU 170 97 #define ACLK_BUS_PRE 171 98 #define ACLK_CRYPTO 172 99 #define ACLK_VI_PRE 173 100 #define ACLK_VO_PRE 174 101 #define ACLK_VPU 175 102 #define ACLK_PERI_PRE 176 103 #define ACLK_GMAC 178 104 #define ACLK_CIF 179 105 #define ACLK_ISP 180 106 #define ACLK_VOPB 181 107 #define ACLK_VOPL 182 108 #define ACLK_RGA 183 109 #define ACLK_GIC 184 110 #define ACLK_DCF 186 111 #define ACLK_DMAC 187 112 113 /* hclk gates */ 114 #define HCLK_BUS_PRE 240 115 #define HCLK_CRYPTO 241 116 #define HCLK_VI_PRE 242 117 #define HCLK_VO_PRE 243 118 #define HCLK_VPU 244 119 #define HCLK_PERI_PRE 245 120 #define HCLK_MMC_NAND 246 121 #define HCLK_SDMMC 247 122 #define HCLK_USB 248 123 #define HCLK_CIF 249 124 #define HCLK_ISP 250 125 #define HCLK_VOPB 251 126 #define HCLK_VOPL 252 127 #define HCLK_RGA 253 128 #define HCLK_NANDC 254 129 #define HCLK_SDIO 255 130 #define HCLK_EMMC 256 131 #define HCLK_SFC 257 132 #define HCLK_OTG 258 133 #define HCLK_HOST 259 134 #define HCLK_HOST_ARB 260 135 #define HCLK_PDM 261 136 #define HCLK_I2S0 262 137 #define HCLK_I2S1 263 138 #define HCLK_I2S2 264 139 140 /* pclk gates */ 141 #define PCLK_BUS_PRE 320 142 #define PCLK_DDR 321 143 #define PCLK_VO_PRE 322 144 #define PCLK_GMAC 323 145 #define PCLK_MIPI_DSI 324 146 #define PCLK_MIPIDSIPHY 325 147 #define PCLK_MIPICSIPHY 326 148 #define PCLK_USB_GRF 327 149 #define PCLK_DCF 328 150 #define PCLK_UART1 329 151 #define PCLK_UART2 330 152 #define PCLK_UART3 331 153 #define PCLK_UART4 332 154 #define PCLK_UART5 333 155 #define PCLK_I2C0 334 156 #define PCLK_I2C1 335 157 #define PCLK_I2C2 336 158 #define PCLK_I2C3 337 159 #define PCLK_I2C4 338 160 #define PCLK_PWM0 339 161 #define PCLK_PWM1 340 162 #define PCLK_SPI0 341 163 #define PCLK_SPI1 342 164 #define PCLK_SARADC 343 165 #define PCLK_TSADC 344 166 #define PCLK_TIMER 345 167 #define PCLK_OTP_NS 346 168 #define PCLK_WDT_NS 347 169 #define PCLK_GPIO1 348 170 #define PCLK_GPIO2 349 171 #define PCLK_GPIO3 350 172 #define PCLK_ISP 351 173 #define PCLK_CIF 352 174 #define PCLK_OTP_PHY 353 175 176 #define CLK_NR_CLKS (PCLK_OTP_PHY + 1) 177 178 /* pmu-clocks indices */ 179 180 #define PLL_GPLL 1 181 182 #define SCLK_RTC32K_PMU 4 183 #define SCLK_WIFI_PMU 5 184 #define SCLK_UART0_PMU 6 185 #define SCLK_PVTM_PMU 7 186 #define PCLK_PMU_PRE 8 187 #define SCLK_REF24M_PMU 9 188 #define SCLK_USBPHY_REF 10 189 #define SCLK_MIPIDSIPHY_REF 11 190 191 #define XIN24M_DIV 12 192 193 #define PCLK_GPIO0_PMU 20 194 #define PCLK_UART0_PMU 21 195 196 #define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) 197 198 /* soft-reset indices */ 199 #define SRST_CORE0_PO 0 200 #define SRST_CORE1_PO 1 201 #define SRST_CORE2_PO 2 202 #define SRST_CORE3_PO 3 203 #define SRST_CORE0 4 204 #define SRST_CORE1 5 205 #define SRST_CORE2 6 206 #define SRST_CORE3 7 207 #define SRST_CORE0_DBG 8 208 #define SRST_CORE1_DBG 9 209 #define SRST_CORE2_DBG 10 210 #define SRST_CORE3_DBG 11 211 #define SRST_TOPDBG 12 212 #define SRST_CORE_NOC 13 213 #define SRST_STRC_A 14 214 #define SRST_L2C 15 215 216 #define SRST_DAP 16 217 #define SRST_CORE_PVTM 17 218 #define SRST_GPU 18 219 #define SRST_GPU_NIU 19 220 #define SRST_UPCTL2 20 221 #define SRST_UPCTL2_A 21 222 #define SRST_UPCTL2_P 22 223 #define SRST_MSCH 23 224 #define SRST_MSCH_P 24 225 #define SRST_DDRMON_P 25 226 #define SRST_DDRSTDBY_P 26 227 #define SRST_DDRSTDBY 27 228 #define SRST_DDRGRF_p 28 229 #define SRST_AXI_SPLIT_A 29 230 #define SRST_AXI_CMD_A 30 231 #define SRST_AXI_CMD_P 31 232 233 #define SRST_DDRPHY 32 234 #define SRST_DDRPHYDIV 33 235 #define SRST_DDRPHY_P 34 236 #define SRST_VPU_A 36 237 #define SRST_VPU_NIU_A 37 238 #define SRST_VPU_H 38 239 #define SRST_VPU_NIU_H 39 240 #define SRST_VI_NIU_A 40 241 #define SRST_VI_NIU_H 41 242 #define SRST_ISP_H 42 243 #define SRST_ISP 43 244 #define SRST_CIF_A 44 245 #define SRST_CIF_H 45 246 #define SRST_CIF_PCLKIN 46 247 #define SRST_MIPICSIPHY_P 47 248 249 #define SRST_VO_NIU_A 48 250 #define SRST_VO_NIU_H 49 251 #define SRST_VO_NIU_P 50 252 #define SRST_VOPB_A 51 253 #define SRST_VOPB_H 52 254 #define SRST_VOPB 53 255 #define SRST_PWM_VOPB 54 256 #define SRST_VOPL_A 55 257 #define SRST_VOPL_H 56 258 #define SRST_VOPL 57 259 #define SRST_RGA_A 58 260 #define SRST_RGA_H 59 261 #define SRST_RGA 60 262 #define SRST_MIPIDSI_HOST_P 61 263 #define SRST_MIPIDSIPHY_P 62 264 #define SRST_VPU_CORE 63 265 266 #define SRST_PERI_NIU_A 64 267 #define SRST_USB_NIU_H 65 268 #define SRST_USB2OTG_H 66 269 #define SRST_USB2OTG 67 270 #define SRST_USB2OTG_ADP 68 271 #define SRST_USB2HOST_H 69 272 #define SRST_USB2HOST_ARB_H 70 273 #define SRST_USB2HOST_AUX_H 71 274 #define SRST_USB2HOST_EHCI 72 275 #define SRST_USB2HOST 73 276 #define SRST_USBPHYPOR 74 277 #define SRST_USBPHY_OTG_PORT 75 278 #define SRST_USBPHY_HOST_PORT 76 279 #define SRST_USBPHY_GRF 77 280 #define SRST_CPU_BOOST_P 78 281 #define SRST_CPU_BOOST 79 282 283 #define SRST_MMC_NAND_NIU_H 80 284 #define SRST_SDIO_H 81 285 #define SRST_EMMC_H 82 286 #define SRST_SFC_H 83 287 #define SRST_SFC 84 288 #define SRST_SDCARD_NIU_H 85 289 #define SRST_SDMMC_H 86 290 #define SRST_NANDC_H 89 291 #define SRST_NANDC 90 292 #define SRST_GMAC_NIU_A 92 293 #define SRST_GMAC_NIU_P 93 294 #define SRST_GMAC_A 94 295 296 #define SRST_PMU_NIU_P 96 297 #define SRST_PMU_SGRF_P 97 298 #define SRST_PMU_GRF_P 98 299 #define SRST_PMU 99 300 #define SRST_PMU_MEM_P 100 301 #define SRST_PMU_GPIO0_P 101 302 #define SRST_PMU_UART0_P 102 303 #define SRST_PMU_CRU_P 103 304 #define SRST_PMU_PVTM 104 305 #define SRST_PMU_UART 105 306 #define SRST_PMU_NIU_H 106 307 #define SRST_PMU_DDR_FAIL_SAVE 107 308 #define SRST_PMU_CORE_PERF_A 108 309 #define SRST_PMU_CORE_GRF_P 109 310 #define SRST_PMU_GPU_PERF_A 110 311 #define SRST_PMU_GPU_GRF_P 111 312 313 #define SRST_CRYPTO_NIU_A 112 314 #define SRST_CRYPTO_NIU_H 113 315 #define SRST_CRYPTO_A 114 316 #define SRST_CRYPTO_H 115 317 #define SRST_CRYPTO 116 318 #define SRST_CRYPTO_APK 117 319 #define SRST_BUS_NIU_H 120 320 #define SRST_USB_NIU_P 121 321 #define SRST_BUS_TOP_NIU_P 122 322 #define SRST_INTMEM_A 123 323 #define SRST_GIC_A 124 324 #define SRST_ROM_H 126 325 #define SRST_DCF_A 127 326 327 #define SRST_DCF_P 128 328 #define SRST_PDM_H 129 329 #define SRST_PDM 130 330 #define SRST_I2S0_H 131 331 #define SRST_I2S0_TX 132 332 #define SRST_I2S1_H 133 333 #define SRST_I2S1 134 334 #define SRST_I2S2_H 135 335 #define SRST_I2S2 136 336 #define SRST_UART1_P 137 337 #define SRST_UART1 138 338 #define SRST_UART2_P 139 339 #define SRST_UART2 140 340 #define SRST_UART3_P 141 341 #define SRST_UART3 142 342 #define SRST_UART4_P 143 343 344 #define SRST_UART4 144 345 #define SRST_UART5_P 145 346 #define SRST_UART5 146 347 #define SRST_I2C0_P 147 348 #define SRST_I2C0 148 349 #define SRST_I2C1_P 149 350 #define SRST_I2C1 150 351 #define SRST_I2C2_P 151 352 #define SRST_I2C2 152 353 #define SRST_I2C3_P 153 354 #define SRST_I2C3 154 355 #define SRST_PWM0_P 157 356 #define SRST_PWM0 158 357 #define SRST_PWM1_P 159 358 359 #define SRST_PWM1 160 360 #define SRST_SPI0_P 161 361 #define SRST_SPI0 162 362 #define SRST_SPI1_P 163 363 #define SRST_SPI1 164 364 #define SRST_SARADC_P 165 365 #define SRST_SARADC 166 366 #define SRST_TSADC_P 167 367 #define SRST_TSADC 168 368 #define SRST_TIMER_P 169 369 #define SRST_TIMER0 170 370 #define SRST_TIMER1 171 371 #define SRST_TIMER2 172 372 #define SRST_TIMER3 173 373 #define SRST_TIMER4 174 374 #define SRST_TIMER5 175 375 376 #define SRST_OTP_NS_P 176 377 #define SRST_OTP_NS_SBPI 177 378 #define SRST_OTP_NS_USR 178 379 #define SRST_OTP_PHY_P 179 380 #define SRST_OTP_PHY 180 381 #define SRST_WDT_NS_P 181 382 #define SRST_GPIO1_P 182 383 #define SRST_GPIO2_P 183 384 #define SRST_GPIO3_P 184 385 #define SRST_SGRF_P 185 386 #define SRST_GRF_P 186 387 #define SRST_I2S0_RX 191 388 389 #endif 390