1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Qualcomm SDHCI driver - SD/eMMC controller
4 *
5 * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
6 *
7 * Based on Linux driver
8 */
9
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <malloc.h>
14 #include <sdhci.h>
15 #include <wait_bit.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <linux/bitops.h>
19
20 /* Non-standard registers needed for SDHCI startup */
21 #define SDCC_MCI_POWER 0x0
22 #define SDCC_MCI_POWER_SW_RST BIT(7)
23
24 /* This is undocumented register */
25 #define SDCC_MCI_VERSION 0x50
26 #define SDCC_MCI_VERSION_MAJOR_SHIFT 28
27 #define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
28 #define SDCC_MCI_VERSION_MINOR_MASK 0xff
29
30 #define SDCC_MCI_STATUS2 0x6C
31 #define SDCC_MCI_STATUS2_MCI_ACT 0x1
32 #define SDCC_MCI_HC_MODE 0x78
33
34 /* Offset to SDHCI registers */
35 #define SDCC_SDHCI_OFFSET 0x900
36
37 /* Non standard (?) SDHCI register */
38 #define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
39
40 struct msm_sdhc_plat {
41 struct mmc_config cfg;
42 struct mmc mmc;
43 };
44
45 struct msm_sdhc {
46 struct sdhci_host host;
47 void *base;
48 };
49
50 DECLARE_GLOBAL_DATA_PTR;
51
msm_sdc_clk_init(struct udevice * dev)52 static int msm_sdc_clk_init(struct udevice *dev)
53 {
54 int node = dev_of_offset(dev);
55 uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
56 400000);
57 uint clkd[2]; /* clk_id and clk_no */
58 int clk_offset;
59 struct udevice *clk_dev;
60 struct clk clk;
61 int ret;
62
63 ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
64 if (ret)
65 return ret;
66
67 clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
68 if (clk_offset < 0)
69 return clk_offset;
70
71 ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
72 if (ret)
73 return ret;
74
75 clk.id = clkd[1];
76 ret = clk_request(clk_dev, &clk);
77 if (ret < 0)
78 return ret;
79
80 ret = clk_set_rate(&clk, clk_rate);
81 clk_free(&clk);
82 if (ret < 0)
83 return ret;
84
85 return 0;
86 }
87
msm_sdc_probe(struct udevice * dev)88 static int msm_sdc_probe(struct udevice *dev)
89 {
90 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
91 struct msm_sdhc_plat *plat = dev_get_plat(dev);
92 struct msm_sdhc *prv = dev_get_priv(dev);
93 struct sdhci_host *host = &prv->host;
94 u32 core_version, core_minor, core_major;
95 u32 caps;
96 int ret;
97
98 host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
99
100 host->max_clk = 0;
101
102 /* Init clocks */
103 ret = msm_sdc_clk_init(dev);
104 if (ret)
105 return ret;
106
107 /* Reset the core and Enable SDHC mode */
108 writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
109 prv->base + SDCC_MCI_POWER);
110
111
112 /* Wait for reset to be written to register */
113 if (wait_for_bit_le32(prv->base + SDCC_MCI_STATUS2,
114 SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
115 printf("msm_sdhci: reset request failed\n");
116 return -EIO;
117 }
118
119 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
120 if (wait_for_bit_le32(prv->base + SDCC_MCI_POWER,
121 SDCC_MCI_POWER_SW_RST, false, 2, false)) {
122 printf("msm_sdhci: stuck in reset\n");
123 return -ETIMEDOUT;
124 }
125
126 /* Enable host-controller mode */
127 writel(1, prv->base + SDCC_MCI_HC_MODE);
128
129 core_version = readl(prv->base + SDCC_MCI_VERSION);
130
131 core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
132 core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
133
134 core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
135
136 /*
137 * Support for some capabilities is not advertised by newer
138 * controller versions and must be explicitly enabled.
139 */
140 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
141 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
142 caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
143 writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
144 }
145
146 ret = mmc_of_parse(dev, &plat->cfg);
147 if (ret)
148 return ret;
149
150 host->mmc = &plat->mmc;
151 host->mmc->dev = dev;
152 ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
153 if (ret)
154 return ret;
155 host->mmc->priv = &prv->host;
156 upriv->mmc = host->mmc;
157
158 return sdhci_probe(dev);
159 }
160
msm_sdc_remove(struct udevice * dev)161 static int msm_sdc_remove(struct udevice *dev)
162 {
163 struct msm_sdhc *priv = dev_get_priv(dev);
164
165 /* Disable host-controller mode */
166 writel(0, priv->base + SDCC_MCI_HC_MODE);
167
168 return 0;
169 }
170
msm_of_to_plat(struct udevice * dev)171 static int msm_of_to_plat(struct udevice *dev)
172 {
173 struct udevice *parent = dev->parent;
174 struct msm_sdhc *priv = dev_get_priv(dev);
175 struct sdhci_host *host = &priv->host;
176 int node = dev_of_offset(dev);
177
178 host->name = strdup(dev->name);
179 host->ioaddr = dev_read_addr_ptr(dev);
180 host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4);
181 host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
182 priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
183 dev_of_offset(parent), node, "reg", 1, NULL, false);
184 if (priv->base == (void *)FDT_ADDR_T_NONE ||
185 host->ioaddr == (void *)FDT_ADDR_T_NONE)
186 return -EINVAL;
187
188 return 0;
189 }
190
msm_sdc_bind(struct udevice * dev)191 static int msm_sdc_bind(struct udevice *dev)
192 {
193 struct msm_sdhc_plat *plat = dev_get_plat(dev);
194
195 return sdhci_bind(dev, &plat->mmc, &plat->cfg);
196 }
197
198 static const struct udevice_id msm_mmc_ids[] = {
199 { .compatible = "qcom,sdhci-msm-v4" },
200 { }
201 };
202
203 U_BOOT_DRIVER(msm_sdc_drv) = {
204 .name = "msm_sdc",
205 .id = UCLASS_MMC,
206 .of_match = msm_mmc_ids,
207 .of_to_plat = msm_of_to_plat,
208 .ops = &sdhci_ops,
209 .bind = msm_sdc_bind,
210 .probe = msm_sdc_probe,
211 .remove = msm_sdc_remove,
212 .priv_auto = sizeof(struct msm_sdhc),
213 .plat_auto = sizeof(struct msm_sdhc_plat),
214 };
215