1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Marvell MMC/SD/SDIO driver
4 *
5 * (C) Copyright 2012-2014
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Maen Suleiman, Gerald Kerma
8 */
9
10 #include <common.h>
11 #include <errno.h>
12 #include <log.h>
13 #include <malloc.h>
14 #include <dm.h>
15 #include <fdtdec.h>
16 #include <part.h>
17 #include <mmc.h>
18 #include <asm/io.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/soc.h>
21 #include <mvebu_mmc.h>
22 #include <dm/device_compat.h>
23
24 #define MVEBU_TARGET_DRAM 0
25
26 #define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
27
get_regbase(const struct mmc * mmc)28 static inline void *get_regbase(const struct mmc *mmc)
29 {
30 struct mvebu_mmc_plat *pdata = mmc->priv;
31
32 return pdata->iobase;
33 }
34
mvebu_mmc_write(const struct mmc * mmc,u32 offs,u32 val)35 static void mvebu_mmc_write(const struct mmc *mmc, u32 offs, u32 val)
36 {
37 writel(val, get_regbase(mmc) + (offs));
38 }
39
mvebu_mmc_read(const struct mmc * mmc,u32 offs)40 static u32 mvebu_mmc_read(const struct mmc *mmc, u32 offs)
41 {
42 return readl(get_regbase(mmc) + (offs));
43 }
44
mvebu_mmc_setup_data(struct udevice * dev,struct mmc_data * data)45 static int mvebu_mmc_setup_data(struct udevice *dev, struct mmc_data *data)
46 {
47 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
48 struct mmc *mmc = &pdata->mmc;
49 u32 ctrl_reg;
50
51 dev_dbg(dev, "data %s : blocks=%d blksz=%d\n",
52 (data->flags & MMC_DATA_READ) ? "read" : "write",
53 data->blocks, data->blocksize);
54
55 /* default to maximum timeout */
56 ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
57 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
58 mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
59
60 if (data->flags & MMC_DATA_READ) {
61 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
62 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
63 } else {
64 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
65 mvebu_mmc_write(mmc, SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
66 }
67
68 mvebu_mmc_write(mmc, SDIO_BLK_COUNT, data->blocks);
69 mvebu_mmc_write(mmc, SDIO_BLK_SIZE, data->blocksize);
70
71 return 0;
72 }
73
mvebu_mmc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)74 static int mvebu_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
75 struct mmc_data *data)
76 {
77 ulong start;
78 ushort waittype = 0;
79 ushort resptype = 0;
80 ushort xfertype = 0;
81 ushort resp_indx = 0;
82 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
83 struct mmc *mmc = &pdata->mmc;
84
85 dev_dbg(dev, "cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
86 cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
87
88 dev_dbg(dev, "cmd %d (hw state 0x%04x)\n",
89 cmd->cmdidx, mvebu_mmc_read(mmc, SDIO_HW_STATE));
90
91 /*
92 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
93 * register is sometimes not set before a while when some
94 * "unusual" data block sizes are used (such as with the SWITCH
95 * command), even despite the fact that the XFER_DONE interrupt
96 * was raised. And if another data transfer starts before
97 * this bit comes to good sense (which eventually happens by
98 * itself) then the new transfer simply fails with a timeout.
99 */
100 if (!(mvebu_mmc_read(mmc, SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
101 ushort hw_state, count = 0;
102
103 start = get_timer(0);
104 do {
105 hw_state = mvebu_mmc_read(mmc, SDIO_HW_STATE);
106 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
107 printf("%s : FIFO_EMPTY bit missing\n",
108 dev->name);
109 break;
110 }
111 count++;
112 } while (!(hw_state & CMD_FIFO_EMPTY));
113 dev_dbg(dev, "*** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
114 hw_state, count, (get_timer(0) - (start)));
115 }
116
117 /* Clear status */
118 mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
119 mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
120
121 resptype = SDIO_CMD_INDEX(cmd->cmdidx);
122
123 /* Analyzing resptype/xfertype/waittype for the command */
124 if (cmd->resp_type & MMC_RSP_BUSY)
125 resptype |= SDIO_CMD_RSP_48BUSY;
126 else if (cmd->resp_type & MMC_RSP_136)
127 resptype |= SDIO_CMD_RSP_136;
128 else if (cmd->resp_type & MMC_RSP_PRESENT)
129 resptype |= SDIO_CMD_RSP_48;
130 else
131 resptype |= SDIO_CMD_RSP_NONE;
132
133 if (cmd->resp_type & MMC_RSP_CRC)
134 resptype |= SDIO_CMD_CHECK_CMDCRC;
135
136 if (cmd->resp_type & MMC_RSP_OPCODE)
137 resptype |= SDIO_CMD_INDX_CHECK;
138
139 if (cmd->resp_type & MMC_RSP_PRESENT) {
140 resptype |= SDIO_UNEXPECTED_RESP;
141 waittype |= SDIO_NOR_UNEXP_RSP;
142 }
143
144 if (data) {
145 int err = mvebu_mmc_setup_data(dev, data);
146
147 if (err) {
148 dev_dbg(dev, "command DATA error :%x\n", err);
149 return err;
150 }
151
152 resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
153 xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
154 if (data->flags & MMC_DATA_READ) {
155 xfertype |= SDIO_XFER_MODE_TO_HOST;
156 waittype = SDIO_NOR_DMA_INI;
157 } else {
158 waittype |= SDIO_NOR_XFER_DONE;
159 }
160 } else {
161 waittype |= SDIO_NOR_CMD_DONE;
162 }
163
164 /* Setting cmd arguments */
165 mvebu_mmc_write(mmc, SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
166 mvebu_mmc_write(mmc, SDIO_ARG_HI, cmd->cmdarg >> 16);
167
168 /* Setting Xfer mode */
169 mvebu_mmc_write(mmc, SDIO_XFER_MODE, xfertype);
170
171 /* Sending command */
172 mvebu_mmc_write(mmc, SDIO_CMD, resptype);
173
174 start = get_timer(0);
175
176 while (!((mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS)) & waittype)) {
177 if (mvebu_mmc_read(mmc, SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
178 dev_dbg(dev, "error! cmdidx : %d, err reg: %04x\n",
179 cmd->cmdidx,
180 mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS));
181 if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
182 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
183 dev_dbg(dev, "command READ timed out\n");
184 return -ETIMEDOUT;
185 }
186 dev_dbg(dev, "command READ error\n");
187 return -ECOMM;
188 }
189
190 if ((get_timer(0) - start) > TIMEOUT_DELAY) {
191 dev_dbg(dev, "command timed out\n");
192 return -ETIMEDOUT;
193 }
194 }
195
196 /* Handling response */
197 if (cmd->resp_type & MMC_RSP_136) {
198 uint response[8];
199
200 for (resp_indx = 0; resp_indx < 8; resp_indx++)
201 response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
202
203 cmd->response[0] = ((response[0] & 0x03ff) << 22) |
204 ((response[1] & 0xffff) << 6) |
205 ((response[2] & 0xfc00) >> 10);
206 cmd->response[1] = ((response[2] & 0x03ff) << 22) |
207 ((response[3] & 0xffff) << 6) |
208 ((response[4] & 0xfc00) >> 10);
209 cmd->response[2] = ((response[4] & 0x03ff) << 22) |
210 ((response[5] & 0xffff) << 6) |
211 ((response[6] & 0xfc00) >> 10);
212 cmd->response[3] = ((response[6] & 0x03ff) << 22) |
213 ((response[7] & 0x3fff) << 8);
214 } else if (cmd->resp_type & MMC_RSP_PRESENT) {
215 uint response[3];
216
217 for (resp_indx = 0; resp_indx < 3; resp_indx++)
218 response[resp_indx] = mvebu_mmc_read(mmc, SDIO_RSP(resp_indx));
219
220 cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
221 ((response[1] & 0xffff) << (14 - 8)) |
222 ((response[0] & 0x03ff) << (30 - 8));
223 cmd->response[1] = ((response[0] & 0xfc00) >> 10);
224 cmd->response[2] = 0;
225 cmd->response[3] = 0;
226 } else {
227 cmd->response[0] = 0;
228 cmd->response[1] = 0;
229 cmd->response[2] = 0;
230 cmd->response[3] = 0;
231 }
232
233 dev_dbg(dev, "resp[0x%x] ", cmd->resp_type);
234 debug("[0x%x] ", cmd->response[0]);
235 debug("[0x%x] ", cmd->response[1]);
236 debug("[0x%x] ", cmd->response[2]);
237 debug("[0x%x] ", cmd->response[3]);
238 debug("\n");
239
240 if (mvebu_mmc_read(mmc, SDIO_ERR_INTR_STATUS) &
241 (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
242 return -ETIMEDOUT;
243
244 return 0;
245 }
246
mvebu_mmc_power_up(struct udevice * dev)247 static void mvebu_mmc_power_up(struct udevice *dev)
248 {
249 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
250 struct mmc *mmc = &pdata->mmc;
251
252 dev_dbg(dev, "power up\n");
253
254 /* disable interrupts */
255 mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
256 mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
257
258 /* SW reset */
259 mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
260
261 mvebu_mmc_write(mmc, SDIO_XFER_MODE, 0);
262
263 /* enable status */
264 mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
265 mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
266
267 /* enable interrupts status */
268 mvebu_mmc_write(mmc, SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
269 mvebu_mmc_write(mmc, SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
270 }
271
mvebu_mmc_set_clk(struct udevice * dev,unsigned int clock)272 static void mvebu_mmc_set_clk(struct udevice *dev, unsigned int clock)
273 {
274 unsigned int m;
275 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
276 struct mmc *mmc = &pdata->mmc;
277
278 if (clock == 0) {
279 dev_dbg(dev, "clock off\n");
280 mvebu_mmc_write(mmc, SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
281 mvebu_mmc_write(mmc, SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
282 } else {
283 m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
284 if (m > MVEBU_MMC_BASE_DIV_MAX)
285 m = MVEBU_MMC_BASE_DIV_MAX;
286 mvebu_mmc_write(mmc, SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
287 dev_dbg(dev, "clock (%d) div : %d\n", clock, m);
288 }
289 }
290
mvebu_mmc_set_bus(struct udevice * dev,unsigned int bus)291 static void mvebu_mmc_set_bus(struct udevice *dev, unsigned int bus)
292 {
293 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
294 struct mmc *mmc = &pdata->mmc;
295 u32 ctrl_reg = 0;
296
297 ctrl_reg = mvebu_mmc_read(mmc, SDIO_HOST_CTRL);
298 ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
299
300 switch (bus) {
301 case 4:
302 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
303 break;
304 case 1:
305 default:
306 ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
307 }
308
309 /* default transfer mode */
310 ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
311 ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
312
313 /* default to maximum timeout */
314 ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
315 ctrl_reg |= SDIO_HOST_CTRL_TMOUT_EN;
316
317 ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
318
319 ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
320
321 dev_dbg(dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
322 (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
323 "push-pull" : "open-drain",
324 (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
325 "4bit-width" : "1bit-width",
326 (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
327 "high-speed" : "");
328
329 mvebu_mmc_write(mmc, SDIO_HOST_CTRL, ctrl_reg);
330 }
331
mvebu_mmc_set_ios(struct udevice * dev)332 static int mvebu_mmc_set_ios(struct udevice *dev)
333 {
334 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
335 struct mmc *mmc = &pdata->mmc;
336
337 dev_dbg(dev, "bus[%d] clock[%d]\n",
338 mmc->bus_width, mmc->clock);
339 mvebu_mmc_set_bus(dev, mmc->bus_width);
340 mvebu_mmc_set_clk(dev, mmc->clock);
341
342 return 0;
343 }
344
345 /*
346 * Set window register.
347 */
mvebu_window_setup(const struct mmc * mmc)348 static void mvebu_window_setup(const struct mmc *mmc)
349 {
350 int i;
351
352 for (i = 0; i < 4; i++) {
353 mvebu_mmc_write(mmc, WINDOW_CTRL(i), 0);
354 mvebu_mmc_write(mmc, WINDOW_BASE(i), 0);
355 }
356 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
357 u32 size, base, attrib;
358
359 /* Enable DRAM bank */
360 switch (i) {
361 case 0:
362 attrib = KWCPU_ATTR_DRAM_CS0;
363 break;
364 case 1:
365 attrib = KWCPU_ATTR_DRAM_CS1;
366 break;
367 case 2:
368 attrib = KWCPU_ATTR_DRAM_CS2;
369 break;
370 case 3:
371 attrib = KWCPU_ATTR_DRAM_CS3;
372 break;
373 default:
374 /* invalide bank, disable access */
375 attrib = 0;
376 break;
377 }
378
379 size = gd->bd->bi_dram[i].size;
380 base = gd->bd->bi_dram[i].start;
381 if (size && attrib) {
382 mvebu_mmc_write(mmc, WINDOW_CTRL(i),
383 MVCPU_WIN_CTRL_DATA(size,
384 MVEBU_TARGET_DRAM,
385 attrib,
386 MVCPU_WIN_ENABLE));
387 } else {
388 mvebu_mmc_write(mmc, WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
389 }
390 mvebu_mmc_write(mmc, WINDOW_BASE(i), base);
391 }
392 }
393
mvebu_mmc_initialize(struct udevice * dev)394 static int mvebu_mmc_initialize(struct udevice *dev)
395 {
396 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
397 struct mmc *mmc = &pdata->mmc;
398
399 dev_dbg(dev, "%s\n", __func__);
400
401 /*
402 * Setting host parameters
403 * Initial Host Ctrl : Timeout : max , Normal Speed mode,
404 * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
405 */
406 mvebu_mmc_write(mmc, SDIO_HOST_CTRL,
407 SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
408 SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
409 SDIO_HOST_CTRL_BIG_ENDIAN |
410 SDIO_HOST_CTRL_PUSH_PULL_EN |
411 SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
412
413 mvebu_mmc_write(mmc, SDIO_CLK_CTRL, 0);
414
415 /* enable status */
416 mvebu_mmc_write(mmc, SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
417 mvebu_mmc_write(mmc, SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
418
419 /* disable interrupts */
420 mvebu_mmc_write(mmc, SDIO_NOR_INTR_EN, 0);
421 mvebu_mmc_write(mmc, SDIO_ERR_INTR_EN, 0);
422
423 mvebu_window_setup(mmc);
424
425 /* SW reset */
426 mvebu_mmc_write(mmc, SDIO_SW_RESET, SDIO_SW_RESET_NOW);
427
428 return 0;
429 }
430
mvebu_mmc_of_to_plat(struct udevice * dev)431 static int mvebu_mmc_of_to_plat(struct udevice *dev)
432 {
433 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
434 fdt_addr_t addr;
435
436 addr = dev_read_addr(dev);
437 if (addr == FDT_ADDR_T_NONE)
438 return -EINVAL;
439
440 pdata->iobase = (void *)addr;
441
442 return 0;
443 }
444
mvebu_mmc_probe(struct udevice * dev)445 static int mvebu_mmc_probe(struct udevice *dev)
446 {
447 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
448 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
449 struct mmc *mmc = &pdata->mmc;
450 struct mmc_config *cfg = &pdata->cfg;
451
452 cfg->name = dev->name;
453 cfg->f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX;
454 cfg->f_max = MVEBU_MMC_CLOCKRATE_MAX;
455 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
456 cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
457 cfg->part_type = PART_TYPE_DOS;
458 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
459
460 mmc->cfg = cfg;
461 mmc->priv = pdata;
462 mmc->dev = dev;
463 upriv->mmc = mmc;
464
465 mvebu_mmc_power_up(dev);
466 mvebu_mmc_initialize(dev);
467
468 return 0;
469 }
470
471 static const struct dm_mmc_ops mvebu_dm_mmc_ops = {
472 .send_cmd = mvebu_mmc_send_cmd,
473 .set_ios = mvebu_mmc_set_ios,
474 };
475
mvebu_mmc_bind(struct udevice * dev)476 static int mvebu_mmc_bind(struct udevice *dev)
477 {
478 struct mvebu_mmc_plat *pdata = dev_get_plat(dev);
479
480 return mmc_bind(dev, &pdata->mmc, &pdata->cfg);
481 }
482
483 static const struct udevice_id mvebu_mmc_match[] = {
484 { .compatible = "marvell,orion-sdio" },
485 { /* sentinel */ }
486 };
487
488 U_BOOT_DRIVER(mvebu_mmc) = {
489 .name = "mvebu_mmc",
490 .id = UCLASS_MMC,
491 .of_match = mvebu_mmc_match,
492 .ops = &mvebu_dm_mmc_ops,
493 .probe = mvebu_mmc_probe,
494 .bind = mvebu_mmc_bind,
495 .of_to_plat = mvebu_mmc_of_to_plat,
496 .plat_auto = sizeof(struct mvebu_mmc_plat),
497 };
498