1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at)
7 * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 */
9
10 #include <common.h>
11 #include <init.h>
12 #include <vsprintf.h>
13 #include <asm/global_data.h>
14 #include <linux/sizes.h>
15 #include <asm/io.h>
16 #include <asm/gpio.h>
17 #include <asm/arch/at91sam9_smc.h>
18 #include <asm/arch/at91_common.h>
19 #include <asm/arch/at91_rstc.h>
20 #include <asm/arch/at91_matrix.h>
21 #include <asm/arch/clk.h>
22 #include <asm/arch/gpio.h>
23 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
24 #include <net.h>
25 #endif
26 #include <netdev.h>
27 #include <asm/mach-types.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 /* ------------------------------------------------------------------------- */
32 /*
33 * Miscelaneous platform dependent initialisations
34 */
35
36 #ifdef CONFIG_CMD_NAND
pm9261_nand_hw_init(void)37 static void pm9261_nand_hw_init(void)
38 {
39 unsigned long csa;
40 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
41 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
42
43 /* Enable CS3 */
44 csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A;
45 writel(csa, &matrix->csa);
46
47 /* Configure SMC CS3 for NAND/SmartMedia */
48 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
50 &smc->cs[3].setup);
51
52 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
53 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
54 &smc->cs[3].pulse);
55
56 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
57 &smc->cs[3].cycle);
58
59 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
60 AT91_SMC_MODE_EXNW_DISABLE |
61 #ifdef CONFIG_SYS_NAND_DBW_16
62 AT91_SMC_MODE_DBW_16 |
63 #else /* CONFIG_SYS_NAND_DBW_8 */
64 AT91_SMC_MODE_DBW_8 |
65 #endif
66 AT91_SMC_MODE_TDF_CYCLE(2),
67 &smc->cs[3].mode);
68
69 at91_periph_clk_enable(ATMEL_ID_PIOA);
70 at91_periph_clk_enable(ATMEL_ID_PIOC);
71
72 /* Configure RDY/BSY */
73 gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
74
75 /* Enable NandFlash */
76 gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
77
78 at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* NANDOE */
79 at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* NANDWE */
80 }
81 #endif
82
83
84 #ifdef CONFIG_DRIVER_DM9000
pm9261_dm9000_hw_init(void)85 static void pm9261_dm9000_hw_init(void)
86 {
87 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
88
89 /* Configure SMC CS2 for DM9000 */
90 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
91 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
92 &smc->cs[2].setup);
93
94 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
95 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
96 &smc->cs[2].pulse);
97
98 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
99 &smc->cs[2].cycle);
100
101 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
102 AT91_SMC_MODE_EXNW_DISABLE |
103 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
104 AT91_SMC_MODE_TDF_CYCLE(1),
105 &smc->cs[2].mode);
106
107 /* Configure Interrupt pin as input, no pull-up */
108 at91_periph_clk_enable(ATMEL_ID_PIOA);
109 at91_set_pio_input(AT91_PIO_PORTA, 24, 0);
110 }
111 #endif
112
board_early_init_f(void)113 int board_early_init_f(void)
114 {
115 return 0;
116 }
117
board_init(void)118 int board_init(void)
119 {
120 /* arch number of PM9261-Board */
121 gd->bd->bi_arch_number = MACH_TYPE_PM9261;
122
123 /* adress of boot parameters */
124 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
125
126 #ifdef CONFIG_CMD_NAND
127 pm9261_nand_hw_init();
128 #endif
129 #ifdef CONFIG_DRIVER_DM9000
130 pm9261_dm9000_hw_init();
131 #endif
132 return 0;
133 }
134
135 #ifdef CONFIG_DRIVER_DM9000
board_eth_init(struct bd_info * bis)136 int board_eth_init(struct bd_info *bis)
137 {
138 return dm9000_initialize(bis);
139 }
140 #endif
141
dram_init(void)142 int dram_init(void)
143 {
144 /* dram_init must store complete ramsize in gd->ram_size */
145 gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
146 PHYS_SDRAM_SIZE);
147 return 0;
148 }
149
dram_init_banksize(void)150 int dram_init_banksize(void)
151 {
152 gd->bd->bi_dram[0].start = PHYS_SDRAM;
153 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
154
155 return 0;
156 }
157
158 #ifdef CONFIG_RESET_PHY_R
reset_phy(void)159 void reset_phy(void)
160 {
161 #ifdef CONFIG_DRIVER_DM9000
162 /*
163 * Initialize ethernet HW addr prior to starting Linux,
164 * needed for nfsroot
165 */
166 eth_init();
167 #endif
168 }
169 #endif
170
171 #ifdef CONFIG_DISPLAY_BOARDINFO
checkboard(void)172 int checkboard (void)
173 {
174 char buf[32];
175
176 printf ("Board : Ronetix PM9261\n");
177 printf ("Crystal frequency: %8s MHz\n",
178 strmhz(buf, get_main_clk_rate()));
179 printf ("CPU clock : %8s MHz\n",
180 strmhz(buf, get_cpu_clk_rate()));
181 printf ("Master clock : %8s MHz\n",
182 strmhz(buf, get_mck_clk_rate()));
183
184 return 0;
185 }
186 #endif
187