1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2010 Samsung Electronics
4  * Minkyu Kang <mk7.kang@samsung.com>
5  */
6 
7 #ifndef __ASM_ARM_ARCH_CLOCK_H_
8 #define __ASM_ARM_ARCH_CLOCK_H_
9 
10 #ifndef __ASSEMBLY__
11 #include <linux/bitops.h>
12 struct exynos4_clock {
13 	unsigned char	res1[0x4200];
14 	unsigned int	src_leftbus;
15 	unsigned char	res2[0x1fc];
16 	unsigned int	mux_stat_leftbus;
17 	unsigned char	res4[0xfc];
18 	unsigned int	div_leftbus;
19 	unsigned char	res5[0xfc];
20 	unsigned int	div_stat_leftbus;
21 	unsigned char	res6[0x1fc];
22 	unsigned int	gate_ip_leftbus;
23 	unsigned char	res7[0x1fc];
24 	unsigned int	clkout_leftbus;
25 	unsigned int	clkout_leftbus_div_stat;
26 	unsigned char	res8[0x37f8];
27 	unsigned int	src_rightbus;
28 	unsigned char	res9[0x1fc];
29 	unsigned int	mux_stat_rightbus;
30 	unsigned char	res10[0xfc];
31 	unsigned int	div_rightbus;
32 	unsigned char	res11[0xfc];
33 	unsigned int	div_stat_rightbus;
34 	unsigned char	res12[0x1fc];
35 	unsigned int	gate_ip_rightbus;
36 	unsigned char	res13[0x1fc];
37 	unsigned int	clkout_rightbus;
38 	unsigned int	clkout_rightbus_div_stat;
39 	unsigned char	res14[0x3608];
40 	unsigned int	epll_lock;
41 	unsigned char	res15[0xc];
42 	unsigned int	vpll_lock;
43 	unsigned char	res16[0xec];
44 	unsigned int	epll_con0;
45 	unsigned int	epll_con1;
46 	unsigned char	res17[0x8];
47 	unsigned int	vpll_con0;
48 	unsigned int	vpll_con1;
49 	unsigned char	res18[0xe8];
50 	unsigned int	src_top0;
51 	unsigned int	src_top1;
52 	unsigned char	res19[0x8];
53 	unsigned int	src_cam;
54 	unsigned int	src_tv;
55 	unsigned int	src_mfc;
56 	unsigned int	src_g3d;
57 	unsigned int	src_image;
58 	unsigned int	src_lcd0;
59 	unsigned int	src_lcd1;
60 	unsigned int	src_maudio;
61 	unsigned int	src_fsys;
62 	unsigned char	res20[0xc];
63 	unsigned int	src_peril0;
64 	unsigned int	src_peril1;
65 	unsigned char	res21[0xb8];
66 	unsigned int	src_mask_top;
67 	unsigned char	res22[0xc];
68 	unsigned int	src_mask_cam;
69 	unsigned int	src_mask_tv;
70 	unsigned char	res23[0xc];
71 	unsigned int	src_mask_lcd0;
72 	unsigned int	src_mask_lcd1;
73 	unsigned int	src_mask_maudio;
74 	unsigned int	src_mask_fsys;
75 	unsigned char	res24[0xc];
76 	unsigned int	src_mask_peril0;
77 	unsigned int	src_mask_peril1;
78 	unsigned char	res25[0xb8];
79 	unsigned int	mux_stat_top;
80 	unsigned char	res26[0x14];
81 	unsigned int	mux_stat_mfc;
82 	unsigned int	mux_stat_g3d;
83 	unsigned int	mux_stat_image;
84 	unsigned char	res27[0xdc];
85 	unsigned int	div_top;
86 	unsigned char	res28[0xc];
87 	unsigned int	div_cam;
88 	unsigned int	div_tv;
89 	unsigned int	div_mfc;
90 	unsigned int	div_g3d;
91 	unsigned int	div_image;
92 	unsigned int	div_lcd0;
93 	unsigned int	div_lcd1;
94 	unsigned int	div_maudio;
95 	unsigned int	div_fsys0;
96 	unsigned int	div_fsys1;
97 	unsigned int	div_fsys2;
98 	unsigned int	div_fsys3;
99 	unsigned int	div_peril0;
100 	unsigned int	div_peril1;
101 	unsigned int	div_peril2;
102 	unsigned int	div_peril3;
103 	unsigned int	div_peril4;
104 	unsigned int	div_peril5;
105 	unsigned char	res29[0x18];
106 	unsigned int	div2_ratio;
107 	unsigned char	res30[0x8c];
108 	unsigned int	div_stat_top;
109 	unsigned char	res31[0xc];
110 	unsigned int	div_stat_cam;
111 	unsigned int	div_stat_tv;
112 	unsigned int	div_stat_mfc;
113 	unsigned int	div_stat_g3d;
114 	unsigned int	div_stat_image;
115 	unsigned int	div_stat_lcd0;
116 	unsigned int	div_stat_lcd1;
117 	unsigned int	div_stat_maudio;
118 	unsigned int	div_stat_fsys0;
119 	unsigned int	div_stat_fsys1;
120 	unsigned int	div_stat_fsys2;
121 	unsigned int	div_stat_fsys3;
122 	unsigned int	div_stat_peril0;
123 	unsigned int	div_stat_peril1;
124 	unsigned int	div_stat_peril2;
125 	unsigned int	div_stat_peril3;
126 	unsigned int	div_stat_peril4;
127 	unsigned int	div_stat_peril5;
128 	unsigned char	res32[0x18];
129 	unsigned int	div2_stat;
130 	unsigned char	res33[0x29c];
131 	unsigned int	gate_ip_cam;
132 	unsigned int	gate_ip_tv;
133 	unsigned int	gate_ip_mfc;
134 	unsigned int	gate_ip_g3d;
135 	unsigned int	gate_ip_image;
136 	unsigned int	gate_ip_lcd0;
137 	unsigned int	gate_ip_lcd1;
138 	unsigned char	res34[0x4];
139 	unsigned int	gate_ip_fsys;
140 	unsigned char	res35[0x8];
141 	unsigned int	gate_ip_gps;
142 	unsigned int	gate_ip_peril;
143 	unsigned char	res36[0xc];
144 	unsigned int	gate_ip_perir;
145 	unsigned char	res37[0xc];
146 	unsigned int	gate_block;
147 	unsigned char	res38[0x8c];
148 	unsigned int	clkout_cmu_top;
149 	unsigned int	clkout_cmu_top_div_stat;
150 	unsigned char	res39[0x37f8];
151 	unsigned int	src_dmc;
152 	unsigned char	res40[0xfc];
153 	unsigned int	src_mask_dmc;
154 	unsigned char	res41[0xfc];
155 	unsigned int	mux_stat_dmc;
156 	unsigned char	res42[0xfc];
157 	unsigned int	div_dmc0;
158 	unsigned int	div_dmc1;
159 	unsigned char	res43[0xf8];
160 	unsigned int	div_stat_dmc0;
161 	unsigned int	div_stat_dmc1;
162 	unsigned char	res44[0x2f8];
163 	unsigned int	gate_ip_dmc;
164 	unsigned char	res45[0xfc];
165 	unsigned int	clkout_cmu_dmc;
166 	unsigned int	clkout_cmu_dmc_div_stat;
167 	unsigned char	res46[0x5f8];
168 	unsigned int	dcgidx_map0;
169 	unsigned int	dcgidx_map1;
170 	unsigned int	dcgidx_map2;
171 	unsigned char	res47[0x14];
172 	unsigned int	dcgperf_map0;
173 	unsigned int	dcgperf_map1;
174 	unsigned char	res48[0x18];
175 	unsigned int	dvcidx_map;
176 	unsigned char	res49[0x1c];
177 	unsigned int	freq_cpu;
178 	unsigned int	freq_dpm;
179 	unsigned char	res50[0x18];
180 	unsigned int	dvsemclk_en;
181 	unsigned int	maxperf;
182 	unsigned char	res51[0x2f78];
183 	unsigned int	apll_lock;
184 	unsigned char	res52[0x4];
185 	unsigned int	mpll_lock;
186 	unsigned char	res53[0xf4];
187 	unsigned int	apll_con0;
188 	unsigned int	apll_con1;
189 	unsigned int	mpll_con0;
190 	unsigned int	mpll_con1;
191 	unsigned char	res54[0xf0];
192 	unsigned int	src_cpu;
193 	unsigned char	res55[0x1fc];
194 	unsigned int	mux_stat_cpu;
195 	unsigned char	res56[0xfc];
196 	unsigned int	div_cpu0;
197 	unsigned int	div_cpu1;
198 	unsigned char	res57[0xf8];
199 	unsigned int	div_stat_cpu0;
200 	unsigned int	div_stat_cpu1;
201 	unsigned char	res58[0x3f8];
202 	unsigned int	clkout_cmu_cpu;
203 	unsigned int	clkout_cmu_cpu_div_stat;
204 	unsigned char	res59[0x5f8];
205 	unsigned int	armclk_stopctrl;
206 	unsigned int	atclk_stopctrl;
207 	unsigned char	res60[0x8];
208 	unsigned int	parityfail_status;
209 	unsigned int	parityfail_clear;
210 	unsigned char	res61[0xe8];
211 	unsigned int	apll_con0_l8;
212 	unsigned int	apll_con0_l7;
213 	unsigned int	apll_con0_l6;
214 	unsigned int	apll_con0_l5;
215 	unsigned int	apll_con0_l4;
216 	unsigned int	apll_con0_l3;
217 	unsigned int	apll_con0_l2;
218 	unsigned int	apll_con0_l1;
219 	unsigned int	iem_control;
220 	unsigned char	res62[0xdc];
221 	unsigned int	apll_con1_l8;
222 	unsigned int	apll_con1_l7;
223 	unsigned int	apll_con1_l6;
224 	unsigned int	apll_con1_l5;
225 	unsigned int	apll_con1_l4;
226 	unsigned int	apll_con1_l3;
227 	unsigned int	apll_con1_l2;
228 	unsigned int	apll_con1_l1;
229 	unsigned char	res63[0xe0];
230 	unsigned int	div_iem_l8;
231 	unsigned int	div_iem_l7;
232 	unsigned int	div_iem_l6;
233 	unsigned int	div_iem_l5;
234 	unsigned int	div_iem_l4;
235 	unsigned int	div_iem_l3;
236 	unsigned int	div_iem_l2;
237 	unsigned int	div_iem_l1;
238 };
239 
240 struct exynos4x12_clock {
241 	unsigned char	res1[0x4200];
242 	unsigned int	src_leftbus;
243 	unsigned char	res2[0x1fc];
244 	unsigned int	mux_stat_leftbus;
245 	unsigned char	res3[0xfc];
246 	unsigned int	div_leftbus;
247 	unsigned char	res4[0xfc];
248 	unsigned int	div_stat_leftbus;
249 	unsigned char	res5[0x1fc];
250 	unsigned int	gate_ip_leftbus;
251 	unsigned char	res6[0x12c];
252 	unsigned int	gate_ip_image;
253 	unsigned char	res7[0xcc];
254 	unsigned int	clkout_leftbus;
255 	unsigned int	clkout_leftbus_div_stat;
256 	unsigned char	res8[0x37f8];
257 	unsigned int	src_rightbus;
258 	unsigned char	res9[0x1fc];
259 	unsigned int	mux_stat_rightbus;
260 	unsigned char	res10[0xfc];
261 	unsigned int	div_rightbus;
262 	unsigned char	res11[0xfc];
263 	unsigned int	div_stat_rightbus;
264 	unsigned char	res12[0x1fc];
265 	unsigned int	gate_ip_rightbus;
266 	unsigned char	res13[0x15c];
267 	unsigned int	gate_ip_perir;
268 	unsigned char	res14[0x9c];
269 	unsigned int	clkout_rightbus;
270 	unsigned int	clkout_rightbus_div_stat;
271 	unsigned char	res15[0x3608];
272 	unsigned int	epll_lock;
273 	unsigned char	res16[0xc];
274 	unsigned int	vpll_lock;
275 	unsigned char	res17[0xec];
276 	unsigned int	epll_con0;
277 	unsigned int	epll_con1;
278 	unsigned int	epll_con2;
279 	unsigned char	res18[0x4];
280 	unsigned int	vpll_con0;
281 	unsigned int	vpll_con1;
282 	unsigned int	vpll_con2;
283 	unsigned char	res19[0xe4];
284 	unsigned int	src_top0;
285 	unsigned int	src_top1;
286 	unsigned char	res20[0x8];
287 	unsigned int	src_cam;
288 	unsigned int	src_tv;
289 	unsigned int	src_mfc;
290 	unsigned int	src_g3d;
291 	unsigned char	res21[0x4];
292 	unsigned int	src_lcd;
293 	unsigned int	src_isp;
294 	unsigned int	src_maudio;
295 	unsigned int	src_fsys;
296 	unsigned char	res22[0xc];
297 	unsigned int	src_peril0;
298 	unsigned int	src_peril1;
299 	unsigned int	src_cam1;
300 	unsigned char	res23[0xb4];
301 	unsigned int	src_mask_top;
302 	unsigned char	res24[0xc];
303 	unsigned int	src_mask_cam;
304 	unsigned int	src_mask_tv;
305 	unsigned char	res25[0xc];
306 	unsigned int	src_mask_lcd;
307 	unsigned int	src_mask_isp;
308 	unsigned int	src_mask_maudio;
309 	unsigned int	src_mask_fsys;
310 	unsigned char	res26[0xc];
311 	unsigned int	src_mask_peril0;
312 	unsigned int	src_mask_peril1;
313 	unsigned char	res27[0xb8];
314 	unsigned int	mux_stat_top0;
315 	unsigned int	mux_stat_top1;
316 	unsigned char	res28[0x10];
317 	unsigned int	mux_stat_mfc;
318 	unsigned int	mux_stat_g3d;
319 	unsigned char	res29[0x28];
320 	unsigned int	mux_stat_cam1;
321 	unsigned char	res30[0xb4];
322 	unsigned int	div_top;
323 	unsigned char	res31[0xc];
324 	unsigned int	div_cam;
325 	unsigned int	div_tv;
326 	unsigned int	div_mfc;
327 	unsigned int	div_g3d;
328 	unsigned char	res32[0x4];
329 	unsigned int	div_lcd;
330 	unsigned int	div_isp;
331 	unsigned int	div_maudio;
332 	unsigned int	div_fsys0;
333 	unsigned int	div_fsys1;
334 	unsigned int	div_fsys2;
335 	unsigned int	div_fsys3;
336 	unsigned int	div_peril0;
337 	unsigned int	div_peril1;
338 	unsigned int	div_peril2;
339 	unsigned int	div_peril3;
340 	unsigned int	div_peril4;
341 	unsigned int	div_peril5;
342 	unsigned int	div_cam1;
343 	unsigned char	res33[0x14];
344 	unsigned int	div2_ratio;
345 	unsigned char	res34[0x8c];
346 	unsigned int	div_stat_top;
347 	unsigned char	res35[0xc];
348 	unsigned int	div_stat_cam;
349 	unsigned int	div_stat_tv;
350 	unsigned int	div_stat_mfc;
351 	unsigned int	div_stat_g3d;
352 	unsigned char	res36[0x4];
353 	unsigned int	div_stat_lcd;
354 	unsigned int	div_stat_isp;
355 	unsigned int	div_stat_maudio;
356 	unsigned int	div_stat_fsys0;
357 	unsigned int	div_stat_fsys1;
358 	unsigned int	div_stat_fsys2;
359 	unsigned int	div_stat_fsys3;
360 	unsigned int	div_stat_peril0;
361 	unsigned int	div_stat_peril1;
362 	unsigned int	div_stat_peril2;
363 	unsigned int	div_stat_peril3;
364 	unsigned int	div_stat_peril4;
365 	unsigned int	div_stat_peril5;
366 	unsigned int	div_stat_cam1;
367 	unsigned char	res37[0x14];
368 	unsigned int	div2_stat;
369 	unsigned char	res38[0x29c];
370 	unsigned int	gate_ip_cam;
371 	unsigned int	gate_ip_tv;
372 	unsigned int	gate_ip_mfc;
373 	unsigned int	gate_ip_g3d;
374 	unsigned char	res39[0x4];
375 	unsigned int	gate_ip_lcd;
376 	unsigned int	gate_ip_isp;
377 	unsigned char	res40[0x4];
378 	unsigned int	gate_ip_fsys;
379 	unsigned char	res41[0x8];
380 	unsigned int	gate_ip_gps;
381 	unsigned int	gate_ip_peril;
382 	unsigned char	res42[0xc];
383 	unsigned char	res43[0x4];
384 	unsigned char	res44[0xc];
385 	unsigned int	gate_block;
386 	unsigned char	res45[0x8c];
387 	unsigned int	clkout_cmu_top;
388 	unsigned int	clkout_cmu_top_div_stat;
389 	unsigned char	res46[0x3600];
390 	unsigned int	mpll_lock;
391 	unsigned char	res47[0xfc];
392 	unsigned int	mpll_con0;
393 	unsigned int	mpll_con1;
394 	unsigned char	res48[0xf0];
395 	unsigned int	src_dmc;
396 	unsigned char	res49[0xfc];
397 	unsigned int	src_mask_dmc;
398 	unsigned char	res50[0xfc];
399 	unsigned int	mux_stat_dmc;
400 	unsigned char	res51[0xfc];
401 	unsigned int	div_dmc0;
402 	unsigned int	div_dmc1;
403 	unsigned char	res52[0xf8];
404 	unsigned int	div_stat_dmc0;
405 	unsigned int	div_stat_dmc1;
406 	unsigned char	res53[0xf8];
407 	unsigned int	gate_bus_dmc0;
408 	unsigned int	gate_bus_dmc1;
409 	unsigned char	res54[0x1f8];
410 	unsigned int	gate_ip_dmc0;
411 	unsigned int	gate_ip_dmc1;
412 	unsigned char	res55[0xf8];
413 	unsigned int	clkout_cmu_dmc;
414 	unsigned int	clkout_cmu_dmc_div_stat;
415 	unsigned char	res56[0x5f8];
416 	unsigned int	dcgidx_map0;
417 	unsigned int	dcgidx_map1;
418 	unsigned int	dcgidx_map2;
419 	unsigned char	res57[0x14];
420 	unsigned int	dcgperf_map0;
421 	unsigned int	dcgperf_map1;
422 	unsigned char	res58[0x18];
423 	unsigned int	dvcidx_map;
424 	unsigned char	res59[0x1c];
425 	unsigned int	freq_cpu;
426 	unsigned int	freq_dpm;
427 	unsigned char	res60[0x18];
428 	unsigned int	dvsemclk_en;
429 	unsigned int	maxperf;
430 	unsigned char	res61[0x8];
431 	unsigned int	dmc_freq_ctrl;
432 	unsigned int	dmc_pause_ctrl;
433 	unsigned int	dddrphy_lock_ctrl;
434 	unsigned int	c2c_state;
435 	unsigned char	res62[0x2f60];
436 	unsigned int	apll_lock;
437 	unsigned char	res63[0x8];
438 	unsigned char	res64[0xf4];
439 	unsigned int	apll_con0;
440 	unsigned int	apll_con1;
441 	unsigned char	res65[0xf8];
442 	unsigned int	src_cpu;
443 	unsigned char	res66[0x1fc];
444 	unsigned int	mux_stat_cpu;
445 	unsigned char	res67[0xfc];
446 	unsigned int	div_cpu0;
447 	unsigned int	div_cpu1;
448 	unsigned char	res68[0xf8];
449 	unsigned int	div_stat_cpu0;
450 	unsigned int	div_stat_cpu1;
451 	unsigned char	res69[0x2f8];
452 	unsigned int	clk_gate_ip_cpu;
453 	unsigned char	res70[0xfc];
454 	unsigned int	clkout_cmu_cpu;
455 	unsigned int	clkout_cmu_cpu_div_stat;
456 	unsigned char	res71[0x5f8];
457 	unsigned int	armclk_stopctrl;
458 	unsigned int	atclk_stopctrl;
459 	unsigned char	res72[0x10];
460 	unsigned char	res73[0x8];
461 	unsigned int	pwr_ctrl;
462 	unsigned int	pwr_ctrl2;
463 	unsigned char	res74[0xd8];
464 	unsigned int	apll_con0_l8;
465 	unsigned int	apll_con0_l7;
466 	unsigned int	apll_con0_l6;
467 	unsigned int	apll_con0_l5;
468 	unsigned int	apll_con0_l4;
469 	unsigned int	apll_con0_l3;
470 	unsigned int	apll_con0_l2;
471 	unsigned int	apll_con0_l1;
472 	unsigned int	iem_control;
473 	unsigned char	res75[0xdc];
474 	unsigned int	apll_con1_l8;
475 	unsigned int	apll_con1_l7;
476 	unsigned int	apll_con1_l6;
477 	unsigned int	apll_con1_l5;
478 	unsigned int	apll_con1_l4;
479 	unsigned int	apll_con1_l3;
480 	unsigned int	apll_con1_l2;
481 	unsigned int	apll_con1_l1;
482 	unsigned char	res76[0xe0];
483 	unsigned int	div_iem_l8;
484 	unsigned int	div_iem_l7;
485 	unsigned int	div_iem_l6;
486 	unsigned int	div_iem_l5;
487 	unsigned int	div_iem_l4;
488 	unsigned int	div_iem_l3;
489 	unsigned int	div_iem_l2;
490 	unsigned int	div_iem_l1;
491 	unsigned char	res77[0xe0];
492 	unsigned int	l2_status;
493 	unsigned char	res78[0xc];
494 	unsigned int	cpu_status;
495 	unsigned char	res79[0xc];
496 	unsigned int	ptm_status;
497 	unsigned char	res80[0x2edc];
498 	unsigned int	div_isp0;
499 	unsigned int	div_isp1;
500 	unsigned char	res81[0xf8];
501 	unsigned int	div_stat_isp0;
502 	unsigned int	div_stat_isp1;
503 	unsigned char	res82[0x3f8];
504 	unsigned int	gate_ip_isp0;
505 	unsigned int	gate_ip_isp1;
506 	unsigned char	res83[0x1f8];
507 	unsigned int	clkout_cmu_isp;
508 	unsigned int	clkout_cmu_ispd_div_stat;
509 	unsigned char	res84[0xf8];
510 	unsigned int	cmu_isp_spar0;
511 	unsigned int	cmu_isp_spar1;
512 	unsigned int	cmu_isp_spar2;
513 	unsigned int	cmu_isp_spar3;
514 };
515 
516 struct exynos5_clock {
517 	unsigned int	apll_lock;
518 	unsigned char	res1[0xfc];
519 	unsigned int	apll_con0;
520 	unsigned int	apll_con1;
521 	unsigned char	res2[0xf8];
522 	unsigned int	src_cpu;
523 	unsigned char	res3[0x1fc];
524 	unsigned int	mux_stat_cpu;
525 	unsigned char	res4[0xfc];
526 	unsigned int	div_cpu0;
527 	unsigned int	div_cpu1;
528 	unsigned char	res5[0xf8];
529 	unsigned int	div_stat_cpu0;
530 	unsigned int	div_stat_cpu1;
531 	unsigned char	res6[0x1f8];
532 	unsigned int	gate_sclk_cpu;
533 	unsigned char	res7[0x1fc];
534 	unsigned int	clkout_cmu_cpu;
535 	unsigned int	clkout_cmu_cpu_div_stat;
536 	unsigned char	res8[0x5f8];
537 	unsigned int	armclk_stopctrl;
538 	unsigned char	res9[0x0c];
539 	unsigned int	parityfail_status;
540 	unsigned int	parityfail_clear;
541 	unsigned char	res10[0x8];
542 	unsigned int	pwr_ctrl;
543 	unsigned int	pwr_ctr2;
544 	unsigned char	res11[0xd8];
545 	unsigned int	apll_con0_l8;
546 	unsigned int	apll_con0_l7;
547 	unsigned int	apll_con0_l6;
548 	unsigned int	apll_con0_l5;
549 	unsigned int	apll_con0_l4;
550 	unsigned int	apll_con0_l3;
551 	unsigned int	apll_con0_l2;
552 	unsigned int	apll_con0_l1;
553 	unsigned int	iem_control;
554 	unsigned char	res12[0xdc];
555 	unsigned int	apll_con1_l8;
556 	unsigned int	apll_con1_l7;
557 	unsigned int	apll_con1_l6;
558 	unsigned int	apll_con1_l5;
559 	unsigned int	apll_con1_l4;
560 	unsigned int	apll_con1_l3;
561 	unsigned int	apll_con1_l2;
562 	unsigned int	apll_con1_l1;
563 	unsigned char	res13[0xe0];
564 	unsigned int	div_iem_l8;
565 	unsigned int	div_iem_l7;
566 	unsigned int	div_iem_l6;
567 	unsigned int	div_iem_l5;
568 	unsigned int	div_iem_l4;
569 	unsigned int	div_iem_l3;
570 	unsigned int	div_iem_l2;
571 	unsigned int	div_iem_l1;
572 	unsigned char	res14[0x2ce0];
573 	unsigned int	mpll_lock;
574 	unsigned char	res15[0xfc];
575 	unsigned int	mpll_con0;
576 	unsigned int	mpll_con1;
577 	unsigned char	res16[0xf8];
578 	unsigned int	src_core0;
579 	unsigned int	src_core1;
580 	unsigned char	res17[0xf8];
581 	unsigned int	src_mask_core;
582 	unsigned char	res18[0x100];
583 	unsigned int	mux_stat_core1;
584 	unsigned char	res19[0xf8];
585 	unsigned int	div_core0;
586 	unsigned int	div_core1;
587 	unsigned int	div_sysrgt;
588 	unsigned char	res20[0xf4];
589 	unsigned int	div_stat_core0;
590 	unsigned int	div_stat_core1;
591 	unsigned int	div_stat_sysrgt;
592 	unsigned char	res21[0x2f4];
593 	unsigned int	gate_ip_core;
594 	unsigned int	gate_ip_sysrgt;
595 	unsigned char	res22[0x8];
596 	unsigned int	c2c_monitor;
597 	unsigned char	res23[0xec];
598 	unsigned int	clkout_cmu_core;
599 	unsigned int	clkout_cmu_core_div_stat;
600 	unsigned char	res24[0x5f8];
601 	unsigned int	dcgidx_map0;
602 	unsigned int	dcgidx_map1;
603 	unsigned int	dcgidx_map2;
604 	unsigned char	res25[0x14];
605 	unsigned int	dcgperf_map0;
606 	unsigned int	dcgperf_map1;
607 	unsigned char	res26[0x18];
608 	unsigned int	dvcidx_map;
609 	unsigned char	res27[0x1c];
610 	unsigned int	freq_cpu;
611 	unsigned int	freq_dpm;
612 	unsigned char	res28[0x18];
613 	unsigned int	dvsemclk_en;
614 	unsigned int	maxperf;
615 	unsigned char	res29[0xf78];
616 	unsigned int	c2c_config;
617 	unsigned char	res30[0x24fc];
618 	unsigned int	div_acp;
619 	unsigned char	res31[0xfc];
620 	unsigned int	div_stat_acp;
621 	unsigned char	res32[0x1fc];
622 	unsigned int	gate_ip_acp;
623 	unsigned char	res33[0xfc];
624 	unsigned int	div_syslft;
625 	unsigned char	res34[0xc];
626 	unsigned int	div_stat_syslft;
627 	unsigned char	res35[0x1c];
628 	unsigned int	gate_ip_syslft;
629 	unsigned char	res36[0xcc];
630 	unsigned int	clkout_cmu_acp;
631 	unsigned int	clkout_cmu_acp_div_stat;
632 	unsigned char	res37[0x8];
633 	unsigned int	ufmc_config;
634 	unsigned char	res38[0x38ec];
635 	unsigned int	div_isp0;
636 	unsigned int	div_isp1;
637 	unsigned int	div_isp2;
638 	unsigned char	res39[0xf4];
639 	unsigned int	div_stat_isp0;
640 	unsigned int	div_stat_isp1;
641 	unsigned int	div_stat_isp2;
642 	unsigned char	res40[0x3f4];
643 	unsigned int	gate_ip_isp0;
644 	unsigned int	gate_ip_isp1;
645 	unsigned char	res41[0xf8];
646 	unsigned int	gate_sclk_isp;
647 	unsigned char	res42[0xc];
648 	unsigned int	mcuisp_pwr_ctrl;
649 	unsigned char	res43[0xec];
650 	unsigned int	clkout_cmu_isp;
651 	unsigned int	clkout_cmu_isp_div_stat;
652 	unsigned char	res44[0x3618];
653 	unsigned int	cpll_lock;
654 	unsigned char	res45[0xc];
655 	unsigned int	epll_lock;
656 	unsigned char	res46[0xc];
657 	unsigned int	vpll_lock;
658 	unsigned char	res47[0xc];
659 	unsigned int	gpll_lock;
660 	unsigned char	res48[0xcc];
661 	unsigned int	cpll_con0;
662 	unsigned int	cpll_con1;
663 	unsigned char	res49[0x8];
664 	unsigned int	epll_con0;
665 	unsigned int	epll_con1;
666 	unsigned int	epll_con2;
667 	unsigned char	res50[0x4];
668 	unsigned int	vpll_con0;
669 	unsigned int	vpll_con1;
670 	unsigned int	vpll_con2;
671 	unsigned char	res51[0x4];
672 	unsigned int	gpll_con0;
673 	unsigned int	gpll_con1;
674 	unsigned char	res52[0xb8];
675 	unsigned int	src_top0;
676 	unsigned int	src_top1;
677 	unsigned int	src_top2;
678 	unsigned int	src_top3;
679 	unsigned int	src_gscl;
680 	unsigned char	res53[0x8];
681 	unsigned int	src_disp1_0;
682 	unsigned char	res54[0x10];
683 	unsigned int	src_mau;
684 	unsigned int	src_fsys;
685 	unsigned int	src_gen;
686 	unsigned char	res55[0x4];
687 	unsigned int	src_peric0;
688 	unsigned int	src_peric1;
689 	unsigned char	res56[0x18];
690 	unsigned int	sclk_src_isp;
691 	unsigned char	res57[0x9c];
692 	unsigned int	src_mask_top;
693 	unsigned char	res58[0xc];
694 	unsigned int	src_mask_gscl;
695 	unsigned char	res59[0x8];
696 	unsigned int	src_mask_disp1_0;
697 	unsigned char	res60[0x4];
698 	unsigned int	src_mask_mau;
699 	unsigned char	res61[0x8];
700 	unsigned int	src_mask_fsys;
701 	unsigned int	src_mask_gen;
702 	unsigned char	res62[0x8];
703 	unsigned int	src_mask_peric0;
704 	unsigned int	src_mask_peric1;
705 	unsigned char	res63[0x18];
706 	unsigned int	src_mask_isp;
707 	unsigned char	res67[0x9c];
708 	unsigned int	mux_stat_top0;
709 	unsigned int	mux_stat_top1;
710 	unsigned int	mux_stat_top2;
711 	unsigned int	mux_stat_top3;
712 	unsigned char	res68[0xf0];
713 	unsigned int	div_top0;
714 	unsigned int	div_top1;
715 	unsigned char	res69[0x8];
716 	unsigned int	div_gscl;
717 	unsigned char	res70[0x8];
718 	unsigned int	div_disp1_0;
719 	unsigned char	res71[0xc];
720 	unsigned int	div_gen;
721 	unsigned char	res72[0x4];
722 	unsigned int	div_mau;
723 	unsigned int	div_fsys0;
724 	unsigned int	div_fsys1;
725 	unsigned int	div_fsys2;
726 	unsigned char	res73[0x4];
727 	unsigned int	div_peric0;
728 	unsigned int	div_peric1;
729 	unsigned int	div_peric2;
730 	unsigned int	div_peric3;
731 	unsigned int	div_peric4;
732 	unsigned int	div_peric5;
733 	unsigned char	res74[0x10];
734 	unsigned int	sclk_div_isp;
735 	unsigned char	res75[0xc];
736 	unsigned int	div2_ratio0;
737 	unsigned int	div2_ratio1;
738 	unsigned char	res76[0x8];
739 	unsigned int	div4_ratio;
740 	unsigned char	res77[0x6c];
741 	unsigned int	div_stat_top0;
742 	unsigned int	div_stat_top1;
743 	unsigned char	res78[0x8];
744 	unsigned int	div_stat_gscl;
745 	unsigned char	res79[0x8];
746 	unsigned int	div_stat_disp1_0;
747 	unsigned char	res80[0xc];
748 	unsigned int	div_stat_gen;
749 	unsigned char	res81[0x4];
750 	unsigned int	div_stat_mau;
751 	unsigned int	div_stat_fsys0;
752 	unsigned int	div_stat_fsys1;
753 	unsigned int	div_stat_fsys2;
754 	unsigned char	res82[0x4];
755 	unsigned int	div_stat_peric0;
756 	unsigned int	div_stat_peric1;
757 	unsigned int	div_stat_peric2;
758 	unsigned int	div_stat_peric3;
759 	unsigned int	div_stat_peric4;
760 	unsigned int	div_stat_peric5;
761 	unsigned char	res83[0x10];
762 	unsigned int	sclk_div_stat_isp;
763 	unsigned char	res84[0xc];
764 	unsigned int	div2_stat0;
765 	unsigned int	div2_stat1;
766 	unsigned char	res85[0x8];
767 	unsigned int	div4_stat;
768 	unsigned char	res86[0x184];
769 	unsigned int	gate_top_sclk_disp1;
770 	unsigned int	gate_top_sclk_gen;
771 	unsigned char	res87[0xc];
772 	unsigned int	gate_top_sclk_mau;
773 	unsigned int	gate_top_sclk_fsys;
774 	unsigned char	res88[0xc];
775 	unsigned int	gate_top_sclk_peric;
776 	unsigned char	res89[0x1c];
777 	unsigned int	gate_top_sclk_isp;
778 	unsigned char	res90[0xac];
779 	unsigned int	gate_ip_gscl;
780 	unsigned char	res91[0x4];
781 	unsigned int	gate_ip_disp1;
782 	unsigned int	gate_ip_mfc;
783 	unsigned int	gate_ip_g3d;
784 	unsigned int	gate_ip_gen;
785 	unsigned char	res92[0xc];
786 	unsigned int	gate_ip_fsys;
787 	unsigned char	res93[0x8];
788 	unsigned int	gate_ip_peric;
789 	unsigned char	res94[0xc];
790 	unsigned int	gate_ip_peris;
791 	unsigned char	res95[0x1c];
792 	unsigned int	gate_block;
793 	unsigned char	res96[0x1c];
794 	unsigned int	mcuiop_pwr_ctrl;
795 	unsigned char	res97[0x5c];
796 	unsigned int	clkout_cmu_top;
797 	unsigned int	clkout_cmu_top_div_stat;
798 	unsigned char	res98[0x37f8];
799 	unsigned int	src_lex;
800 	unsigned char	res99[0x1fc];
801 	unsigned int	mux_stat_lex;
802 	unsigned char	res100[0xfc];
803 	unsigned int	div_lex;
804 	unsigned char	res101[0xfc];
805 	unsigned int	div_stat_lex;
806 	unsigned char	res102[0x1fc];
807 	unsigned int	gate_ip_lex;
808 	unsigned char	res103[0x1fc];
809 	unsigned int	clkout_cmu_lex;
810 	unsigned int	clkout_cmu_lex_div_stat;
811 	unsigned char	res104[0x3af8];
812 	unsigned int	div_r0x;
813 	unsigned char	res105[0xfc];
814 	unsigned int	div_stat_r0x;
815 	unsigned char	res106[0x1fc];
816 	unsigned int	gate_ip_r0x;
817 	unsigned char	res107[0x1fc];
818 	unsigned int	clkout_cmu_r0x;
819 	unsigned int	clkout_cmu_r0x_div_stat;
820 	unsigned char	res108[0x3af8];
821 	unsigned int	div_r1x;
822 	unsigned char	res109[0xfc];
823 	unsigned int	div_stat_r1x;
824 	unsigned char	res110[0x1fc];
825 	unsigned int	gate_ip_r1x;
826 	unsigned char	res111[0x1fc];
827 	unsigned int	clkout_cmu_r1x;
828 	unsigned int	clkout_cmu_r1x_div_stat;
829 	unsigned char	res112[0x3608];
830 	unsigned int	bpll_lock;
831 	unsigned char	res113[0xfc];
832 	unsigned int	bpll_con0;
833 	unsigned int	bpll_con1;
834 	unsigned char	res114[0xe8];
835 	unsigned int	src_cdrex;
836 	unsigned char	res115[0x1fc];
837 	unsigned int	mux_stat_cdrex;
838 	unsigned char	res116[0xfc];
839 	unsigned int	div_cdrex;
840 	unsigned char	res117[0xfc];
841 	unsigned int	div_stat_cdrex;
842 	unsigned char	res118[0x2fc];
843 	unsigned int	gate_ip_cdrex;
844 	unsigned char	res119[0x10];
845 	unsigned int	dmc_freq_ctrl;
846 	unsigned char	res120[0x4];
847 	unsigned int	drex2_pause;
848 	unsigned char	res121[0xe0];
849 	unsigned int	clkout_cmu_cdrex;
850 	unsigned int	clkout_cmu_cdrex_div_stat;
851 	unsigned char	res122[0x8];
852 	unsigned int	lpddr3phy_ctrl;
853 	unsigned int	lpddr3phy_con0;
854 	unsigned int	lpddr3phy_con1;
855 	unsigned int	lpddr3phy_con2;
856 	unsigned int	lpddr3phy_con3;
857 	unsigned int	pll_div2_sel;
858 	unsigned char	res123[0xf5d8];
859 };
860 
861 struct exynos5420_clock {
862 	unsigned int	apll_lock;			/* 0x10010000 */
863 	unsigned char	res1[0xfc];
864 	unsigned int	apll_con0;
865 	unsigned int	apll_con1;
866 	unsigned char	res2[0xf8];
867 	unsigned int	src_cpu;
868 	unsigned char	res3[0x1fc];
869 	unsigned int	mux_stat_cpu;
870 	unsigned char	res4[0xfc];
871 	unsigned int	div_cpu0;		/* 0x10010500 */
872 	unsigned int	div_cpu1;
873 	unsigned char	res5[0xf8];
874 	unsigned int	div_stat_cpu0;
875 	unsigned int	div_stat_cpu1;
876 	unsigned char	res6[0xf8];
877 	unsigned int	gate_bus_cpu;
878 	unsigned char	res7[0xfc];
879 	unsigned int	gate_sclk_cpu;
880 	unsigned char	res8[0x1fc];
881 	unsigned int	clkout_cmu_cpu;		/* 0x10010a00 */
882 	unsigned int	clkout_cmu_cpu_div_stat;
883 	unsigned char	res9[0x5f8];
884 	unsigned int	armclk_stopctrl;
885 	unsigned char	res10[0x4];
886 	unsigned int	arm_ema_ctrl;
887 	unsigned int	arm_ema_status;
888 	unsigned char	res11[0x10];
889 	unsigned int	pwr_ctrl;
890 	unsigned int	pwr_ctrl2;
891 	unsigned char	res12[0xd8];
892 	unsigned int	apll_con0_l8;		/* 0x1001100 */
893 	unsigned int	apll_con0_l7;
894 	unsigned int	apll_con0_l6;
895 	unsigned int	apll_con0_l5;
896 	unsigned int	apll_con0_l4;
897 	unsigned int	apll_con0_l3;
898 	unsigned int	apll_con0_l2;
899 	unsigned int	apll_con0_l1;
900 	unsigned int	iem_control;
901 	unsigned char	res13[0xdc];
902 	unsigned int	apll_con1_l8;		/* 0x10011200 */
903 	unsigned int	apll_con1_l7;
904 	unsigned int	apll_con1_l6;
905 	unsigned int	apll_con1_l5;
906 	unsigned int	apll_con1_l4;
907 	unsigned int	apll_con1_l3;
908 	unsigned int	apll_con1_l2;
909 	unsigned int	apll_con1_l1;
910 	unsigned char	res14[0xe0];
911 	unsigned int	clkdiv_iem_l8;
912 	unsigned int	clkdiv_iem_l7;		/* 0x10011304 */
913 	unsigned int	clkdiv_iem_l6;
914 	unsigned int	clkdiv_iem_l5;
915 	unsigned int	clkdiv_iem_l4;
916 	unsigned int	clkdiv_iem_l3;
917 	unsigned int	clkdiv_iem_l2;
918 	unsigned int	clkdiv_iem_l1;
919 	unsigned char	res15[0xe0];
920 	unsigned int	l2_status;
921 	unsigned char	res16[0x0c];
922 	unsigned int	cpu_status;		/* 0x10011410 */
923 	unsigned char	res17[0x0c];
924 	unsigned int	ptm_status;
925 	unsigned char	res18[0xbdc];
926 	unsigned int	cmu_cpu_spare0;
927 	unsigned int	cmu_cpu_spare1;
928 	unsigned int	cmu_cpu_spare2;
929 	unsigned int	cmu_cpu_spare3;
930 	unsigned int	cmu_cpu_spare4;
931 	unsigned char	res19[0x1fdc];
932 	unsigned int	cmu_cpu_version;
933 	unsigned char	res20[0x20c];
934 	unsigned int	src_cperi0;		/* 0x10014200 */
935 	unsigned int	src_cperi1;
936 	unsigned char	res21[0xf8];
937 	unsigned int	src_mask_cperi;
938 	unsigned char	res22[0x100];
939 	unsigned int	mux_stat_cperi1;
940 	unsigned char	res23[0xfc];
941 	unsigned int	div_cperi1;
942 	unsigned char	res24[0xfc];
943 	unsigned int	div_stat_cperi1;
944 	unsigned char	res25[0xf8];
945 	unsigned int	gate_bus_cperi0;	/* 0x10014700 */
946 	unsigned int	gate_bus_cperi1;
947 	unsigned char	res26[0xf8];
948 	unsigned int	gate_sclk_cperi;
949 	unsigned char	res27[0xfc];
950 	unsigned int	gate_ip_cperi;
951 	unsigned char	res28[0xfc];
952 	unsigned int	clkout_cmu_cperi;
953 	unsigned int	clkout_cmu_cperi_div_stat;
954 	unsigned char	res29[0x5f8];
955 	unsigned int	dcgidx_map0;		/* 0x10015000 */
956 	unsigned int	dcgidx_map1;
957 	unsigned int	dcgidx_map2;
958 	unsigned char	res30[0x14];
959 	unsigned int	dcgperf_map0;
960 	unsigned int	dcgperf_map1;
961 	unsigned char	res31[0x18];
962 	unsigned int	dvcidx_map;
963 	unsigned char	res32[0x1c];
964 	unsigned int	freq_cpu;
965 	unsigned int	freq_dpm;
966 	unsigned char	res33[0x18];
967 	unsigned int	dvsemclk_en;		/* 0x10015080 */
968 	unsigned int	maxperf;
969 	unsigned char	res34[0x2e78];
970 	unsigned int	cmu_cperi_spare0;
971 	unsigned int	cmu_cperi_spare1;
972 	unsigned int	cmu_cperi_spare2;
973 	unsigned int	cmu_cperi_spare3;
974 	unsigned int	cmu_cperi_spare4;
975 	unsigned int	cmu_cperi_spare5;
976 	unsigned int	cmu_cperi_spare6;
977 	unsigned int	cmu_cperi_spare7;
978 	unsigned int	cmu_cperi_spare8;
979 	unsigned char	res35[0xcc];
980 	unsigned int	cmu_cperi_version;		/* 0x10017ff0 */
981 	unsigned char	res36[0x50c];
982 	unsigned int	div_g2d;
983 	unsigned char	res37[0xfc];
984 	unsigned int	div_stat_g2d;
985 	unsigned char	res38[0xfc];
986 	unsigned int	gate_bus_g2d;
987 	unsigned char	res39[0xfc];
988 	unsigned int	gate_ip_g2d;
989 	unsigned char	res40[0x1fc];
990 	unsigned int	clkout_cmu_g2d;
991 	unsigned int	clkout_cmu_g2d_div_stat;	/* 0x10018a04 */
992 	unsigned char	res41[0xf8];
993 	unsigned int	cmu_g2d_spare0;
994 	unsigned int	cmu_g2d_spare1;
995 	unsigned int	cmu_g2d_spare2;
996 	unsigned int	cmu_g2d_spare3;
997 	unsigned int	cmu_g2d_spare4;
998 	unsigned char	res42[0x34dc];
999 	unsigned int	cmu_g2d_version;
1000 	unsigned char	res43[0x30c];
1001 	unsigned int	div_cmu_isp0;
1002 	unsigned int	div_cmu_isp1;
1003 	unsigned int	div_isp2;		/* 0x1001c308 */
1004 	unsigned char	res44[0xf4];
1005 	unsigned int	div_stat_cmu_isp0;
1006 	unsigned int	div_stat_cmu_isp1;
1007 	unsigned int	div_stat_isp2;
1008 	unsigned char	res45[0x2f4];
1009 	unsigned int	gate_bus_isp0;
1010 	unsigned int	gate_bus_isp1;
1011 	unsigned int	gate_bus_isp2;
1012 	unsigned int	gate_bus_isp3;
1013 	unsigned char	res46[0xf0];
1014 	unsigned int	gate_ip_isp0;
1015 	unsigned int	gate_ip_isp1;
1016 	unsigned char	res47[0xf8];
1017 	unsigned int	gate_sclk_isp;
1018 	unsigned char	res48[0x0c];
1019 	unsigned int	mcuisp_pwr_ctrl;		/* 0x1001c910 */
1020 	unsigned char	res49[0x0ec];
1021 	unsigned int	clkout_cmu_isp;
1022 	unsigned int	clkout_cmu_isp_div_stat;
1023 	unsigned char	res50[0xf8];
1024 	unsigned int	cmu_isp_spare0;
1025 	unsigned int	cmu_isp_spare1;
1026 	unsigned int	cmu_isp_spare2;
1027 	unsigned int	cmu_isp_spare3;
1028 	unsigned char	res51[0x34e0];
1029 	unsigned int	cmu_isp_version;
1030 	unsigned char	res52[0x2c];
1031 	unsigned int	cpll_lock;			/* 10020020 */
1032 	unsigned char	res53[0xc];
1033 	unsigned int	dpll_lock;
1034 	unsigned char	res54[0xc];
1035 	unsigned int	epll_lock;
1036 	unsigned char	res55[0xc];
1037 	unsigned int	rpll_lock;
1038 	unsigned char	res56[0xc];
1039 	unsigned int	ipll_lock;
1040 	unsigned char	res57[0xc];
1041 	unsigned int	spll_lock;
1042 	unsigned char	res58[0xc];
1043 	unsigned int	vpll_lock;
1044 	unsigned char	res59[0xc];
1045 	unsigned int	mpll_lock;
1046 	unsigned char	res60[0x8c];
1047 	unsigned int	cpll_con0;			/* 10020120 */
1048 	unsigned int	cpll_con1;
1049 	unsigned int	dpll_con0;
1050 	unsigned int	dpll_con1;
1051 	unsigned int	epll_con0;
1052 	unsigned int	epll_con1;
1053 	unsigned int	epll_con2;
1054 	unsigned char	res601[0x4];
1055 	unsigned int	rpll_con0;
1056 	unsigned int	rpll_con1;
1057 	unsigned int	rpll_con2;
1058 	unsigned char	res602[0x4];
1059 	unsigned int	ipll_con0;
1060 	unsigned int	ipll_con1;
1061 	unsigned char	res61[0x8];
1062 	unsigned int	spll_con0;
1063 	unsigned int	spll_con1;
1064 	unsigned char	res62[0x8];
1065 	unsigned int	vpll_con0;
1066 	unsigned int	vpll_con1;
1067 	unsigned char	res63[0x8];
1068 	unsigned int	mpll_con0;
1069 	unsigned int	mpll_con1;
1070 	unsigned char	res64[0x78];
1071 	unsigned int	src_top0;		/* 0x10020200 */
1072 	unsigned int	src_top1;
1073 	unsigned int	src_top2;
1074 	unsigned int	src_top3;
1075 	unsigned int	src_top4;
1076 	unsigned int	src_top5;
1077 	unsigned int	src_top6;
1078 	unsigned int	src_top7;
1079 	unsigned char	res65[0xc];
1080 	unsigned int	src_disp10;		/* 0x1002022c */
1081 	unsigned char	res66[0x10];
1082 	unsigned int	src_mau;
1083 	unsigned int	src_fsys;
1084 	unsigned char	res67[0x8];
1085 	unsigned int	src_peric0;
1086 	unsigned int	src_peric1;
1087 	unsigned char	res68[0x18];
1088 	unsigned int	src_isp;
1089 	unsigned char	res69[0x0c];
1090 	unsigned int	src_top10;
1091 	unsigned int	src_top11;
1092 	unsigned int	src_top12;
1093 	unsigned char	res70[0x74];
1094 	unsigned int	src_mask_top0;
1095 	unsigned int	src_mask_top1;
1096 	unsigned int	src_mask_top2;
1097 	unsigned char	res71[0x10];
1098 	unsigned int	src_mask_top7;
1099 	unsigned char	res72[0xc];
1100 	unsigned int	src_mask_disp10;	/* 0x1002032c */
1101 	unsigned char	res73[0x4];
1102 	unsigned int	src_mask_mau;
1103 	unsigned char	res74[0x8];
1104 	unsigned int	src_mask_fsys;
1105 	unsigned char	res75[0xc];
1106 	unsigned int	src_mask_peric0;
1107 	unsigned int	src_mask_peric1;
1108 	unsigned char	res76[0x18];
1109 	unsigned int	src_mask_isp;
1110 	unsigned char	res77[0x8c];
1111 	unsigned int	mux_stat_top0;		/* 0x10020400 */
1112 	unsigned int	mux_stat_top1;
1113 	unsigned int	mux_stat_top2;
1114 	unsigned int	mux_stat_top3;
1115 	unsigned int	mux_stat_top4;
1116 	unsigned int	mux_stat_top5;
1117 	unsigned int	mux_stat_top6;
1118 	unsigned int	mux_stat_top7;
1119 	unsigned char	res78[0x60];
1120 	unsigned int	mux_stat_top10;
1121 	unsigned int	mux_stat_top11;
1122 	unsigned int	mux_stat_top12;
1123 	unsigned char	res79[0x74];
1124 	unsigned int	div_top0;		/* 0x10020500 */
1125 	unsigned int	div_top1;
1126 	unsigned int	div_top2;
1127 	unsigned char	res80[0x20];
1128 	unsigned int	div_disp10;
1129 	unsigned char	res81[0x14];
1130 	unsigned int	div_mau;
1131 	unsigned int	div_fsys0;
1132 	unsigned int	div_fsys1;
1133 	unsigned int	div_fsys2;
1134 	unsigned char	res82[0x4];
1135 	unsigned int	div_peric0;
1136 	unsigned int	div_peric1;
1137 	unsigned int	div_peric2;
1138 	unsigned int	div_peric3;
1139 	unsigned int	div_peric4;		/* 0x10020568 */
1140 	unsigned char	res83[0x14];
1141 	unsigned int	div_isp0;
1142 	unsigned int	div_isp1;
1143 	unsigned char	res84[0x8];
1144 	unsigned int	clkdiv2_ratio;
1145 	unsigned char	res850[0xc];
1146 	unsigned int	clkdiv4_ratio;
1147 	unsigned char	res85[0x5c];
1148 	unsigned int	div_stat_top0;
1149 	unsigned int	div_stat_top1;
1150 	unsigned int	div_stat_top2;
1151 	unsigned char	res86[0x20];
1152 	unsigned int	div_stat_disp10;
1153 	unsigned char	res87[0x14];
1154 	unsigned int	div_stat_mau;		/* 0x10020644 */
1155 	unsigned int	div_stat_fsys0;
1156 	unsigned int	div_stat_fsys1;
1157 	unsigned int	div_stat_fsys2;
1158 	unsigned char	res88[0x4];
1159 	unsigned int	div_stat_peric0;
1160 	unsigned int	div_stat_peric1;
1161 	unsigned int	div_stat_peric2;
1162 	unsigned int	div_stat_peric3;
1163 	unsigned int	div_stat_peric4;
1164 	unsigned char	res89[0x14];
1165 	unsigned int	div_stat_isp0;
1166 	unsigned int	div_stat_isp1;
1167 	unsigned char	res90[0x8];
1168 	unsigned int	clkdiv2_stat0;
1169 	unsigned char	res91[0xc];
1170 	unsigned int	clkdiv4_stat;
1171 	unsigned char	res92[0x5c];
1172 	unsigned int	gate_bus_top;		/* 0x10020700 */
1173 	unsigned char	res93[0xc];
1174 	unsigned int	gate_bus_gscl0;
1175 	unsigned char	res94[0xc];
1176 	unsigned int	gate_bus_gscl1;
1177 	unsigned char	res95[0x4];
1178 	unsigned int	gate_bus_disp1;
1179 	unsigned char	res96[0x4];
1180 	unsigned int	gate_bus_wcore;
1181 	unsigned int	gate_bus_mfc;
1182 	unsigned int	gate_bus_g3d;
1183 	unsigned int	gate_bus_gen;
1184 	unsigned int	gate_bus_fsys0;
1185 	unsigned int	gate_bus_fsys1;
1186 	unsigned int	gate_bus_fsys2;
1187 	unsigned int	gate_bus_mscl;
1188 	unsigned int	gate_bus_peric;
1189 	unsigned int	gate_bus_peric1;
1190 	unsigned char	res97[0x8];
1191 	unsigned int	gate_bus_peris0;
1192 	unsigned int	gate_bus_peris1;	/* 0x10020764 */
1193 	unsigned char	res98[0x8];
1194 	unsigned int	gate_bus_noc;
1195 	unsigned char	res99[0xac];
1196 	unsigned int	gate_top_sclk_gscl;
1197 	unsigned char	res1000[0x4];
1198 	unsigned int	gate_top_sclk_disp1;
1199 	unsigned char	res100[0x10];
1200 	unsigned int	gate_top_sclk_mau;
1201 	unsigned int	gate_top_sclk_fsys;
1202 	unsigned char	res101[0xc];
1203 	unsigned int	gate_top_sclk_peric;
1204 	unsigned char	res102[0xc];
1205 	unsigned int	gate_top_sclk_cperi;
1206 	unsigned char	res103[0xc];
1207 	unsigned int	gate_top_sclk_isp;
1208 	unsigned char	res104[0x9c];
1209 	unsigned int	gate_ip_gscl0;
1210 	unsigned char	res105[0xc];
1211 	unsigned int	gate_ip_gscl1;
1212 	unsigned char	res106[0x4];
1213 	unsigned int	gate_ip_disp1;
1214 	unsigned int	gate_ip_mfc;
1215 	unsigned int	gate_ip_g3d;
1216 	unsigned int	gate_ip_gen;		/* 0x10020934 */
1217 	unsigned char	res107[0xc];
1218 	unsigned int	gate_ip_fsys;
1219 	unsigned char	res108[0x8];
1220 	unsigned int	gate_ip_peric;
1221 	unsigned char	res109[0xc];
1222 	unsigned int	gate_ip_peris;
1223 	unsigned char	res110[0xc];
1224 	unsigned int	gate_ip_mscl;
1225 	unsigned char	res111[0xc];
1226 	unsigned int	gate_ip_block;
1227 	unsigned char	res112[0xc];
1228 	unsigned int	bypass;
1229 	unsigned char	res113[0x6c];
1230 	unsigned int	clkout_cmu_top;
1231 	unsigned int	clkout_cmu_top_div_stat;
1232 	unsigned char	res114[0xf8];
1233 	unsigned int	clkout_top_spare0;
1234 	unsigned int	clkout_top_spare1;
1235 	unsigned int	clkout_top_spare2;
1236 	unsigned int	clkout_top_spare3;
1237 	unsigned char	res115[0x34e0];
1238 	unsigned int	clkout_top_version;
1239 	unsigned char	res116[0xc01c];
1240 	unsigned int	bpll_lock;			/* 0x10030010 */
1241 	unsigned char	res117[0xfc];
1242 	unsigned int	bpll_con0;
1243 	unsigned int	bpll_con1;
1244 	unsigned char	res118[0xe8];
1245 	unsigned int	src_cdrex;
1246 	unsigned char	res119[0x1fc];
1247 	unsigned int	mux_stat_cdrex;
1248 	unsigned char	res120[0xfc];
1249 	unsigned int	div_cdrex0;
1250 	unsigned int	div_cdrex1;
1251 	unsigned char	res121[0xf8];
1252 	unsigned int	div_stat_cdrex;
1253 	unsigned char	res1211[0xfc];
1254 	unsigned int	gate_bus_cdrex;
1255 	unsigned int	gate_bus_cdrex1;
1256 	unsigned char	res122[0x1f8];
1257 	unsigned int	gate_ip_cdrex;
1258 	unsigned char	res123[0x10];
1259 	unsigned int	dmc_freq_ctrl;		/* 0x10030914 */
1260 	unsigned char	res124[0x4];
1261 	unsigned int	pause;
1262 	unsigned int	ddrphy_lock_ctrl;
1263 	unsigned char	res125[0xdc];
1264 	unsigned int	clkout_cmu_cdrex;
1265 	unsigned int	clkout_cmu_cdrex_div_stat;
1266 	unsigned char	res126[0x8];
1267 	unsigned int	lpddr3phy_ctrl;
1268 	unsigned int	lpddr3phy_con0;
1269 	unsigned int	lpddr3phy_con1;
1270 	unsigned int	lpddr3phy_con2;
1271 	unsigned int	lpddr3phy_con3;
1272 	unsigned int	lpddr3phy_con4;
1273 	unsigned int	lpddr3phy_con5;		/* 0x10030a28 */
1274 	unsigned int	pll_div2_sel;
1275 	unsigned char	res127[0xd0];
1276 	unsigned int	cmu_cdrex_spare0;
1277 	unsigned int	cmu_cdrex_spare1;
1278 	unsigned int	cmu_cdrex_spare2;
1279 	unsigned int	cmu_cdrex_spare3;
1280 	unsigned int	cmu_cdrex_spare4;
1281 	unsigned char	res128[0x34dc];
1282 	unsigned int	cmu_cdrex_version;		/* 0x10033ff0 */
1283 	unsigned char	res129[0x400c];
1284 	unsigned int	kpll_lock;
1285 	unsigned char	res130[0xfc];
1286 	unsigned int	kpll_con0;
1287 	unsigned int	kpll_con1;
1288 	unsigned char	res131[0xf8];
1289 	unsigned int	src_kfc;
1290 	unsigned char	res132[0x1fc];
1291 	unsigned int	mux_stat_kfc;		/* 0x10038400 */
1292 	unsigned char	res133[0xfc];
1293 	unsigned int	div_kfc0;
1294 	unsigned char	res134[0xfc];
1295 	unsigned int	div_stat_kfc0;
1296 	unsigned char	res135[0xfc];
1297 	unsigned int	gate_bus_cpu_kfc;
1298 	unsigned char	res136[0xfc];
1299 	unsigned int	gate_sclk_cpu_kfc;
1300 	unsigned char	res137[0x1fc];
1301 	unsigned int	clkout_cmu_kfc;
1302 	unsigned int	clkout_cmu_kfc_div_stat;	/* 0x10038a04 */
1303 	unsigned char	res138[0x5f8];
1304 	unsigned int	armclk_stopctrl_kfc;
1305 	unsigned char	res139[0x4];
1306 	unsigned int	armclk_ema_ctrl_kfc;
1307 	unsigned int	armclk_ema_status_kfc;
1308 	unsigned char	res140[0x10];
1309 	unsigned int	pwr_ctrl_kfc;
1310 	unsigned int	pwr_ctrl2_kfc;
1311 	unsigned char	res141[0xd8];
1312 	unsigned int	kpll_con0_l8;
1313 	unsigned int	kpll_con0_l7;
1314 	unsigned int	kpll_con0_l6;
1315 	unsigned int	kpll_con0_l5;
1316 	unsigned int	kpll_con0_l4;
1317 	unsigned int	kpll_con0_l3;
1318 	unsigned int	kpll_con0_l2;
1319 	unsigned int	kpll_con0_l1;
1320 	unsigned int	iem_control_kfc;		/* 0x10039120 */
1321 	unsigned char	res142[0xdc];
1322 	unsigned int	kpll_con1_l8;
1323 	unsigned int	kpll_con1_l7;
1324 	unsigned int	kpll_con1_l6;
1325 	unsigned int	kpll_con1_l5;
1326 	unsigned int	kpll_con1_l4;
1327 	unsigned int	kpll_con1_l3;
1328 	unsigned int	kpll_con1_l2;
1329 	unsigned int	kpll_con1_l1;
1330 	unsigned char	res143[0xe0];
1331 	unsigned int	clkdiv_iem_l8_kfc;		/* 0x10039300 */
1332 	unsigned int	clkdiv_iem_l7_kfc;
1333 	unsigned int	clkdiv_iem_l6_kfc;
1334 	unsigned int	clkdiv_iem_l5_kfc;
1335 	unsigned int	clkdiv_iem_l4_kfc;
1336 	unsigned int	clkdiv_iem_l3_kfc;
1337 	unsigned int	clkdiv_iem_l2_kfc;
1338 	unsigned int	clkdiv_iem_l1_kfc;
1339 	unsigned char	res144[0xe0];
1340 	unsigned int	l2_status_kfc;
1341 	unsigned char	res145[0xc];
1342 	unsigned int	cpu_status_kfc;		/* 0x10039410 */
1343 	unsigned char	res146[0xc];
1344 	unsigned int	ptm_status_kfc;
1345 	unsigned char	res147[0xbdc];
1346 	unsigned int	cmu_kfc_spare0;
1347 	unsigned int	cmu_kfc_spare1;
1348 	unsigned int	cmu_kfc_spare2;
1349 	unsigned int	cmu_kfc_spare3;
1350 	unsigned int	cmu_kfc_spare4;
1351 	unsigned char	res148[0x1fdc];
1352 	unsigned int	cmu_kfc_version;		/* 0x1003bff0 */
1353 };
1354 
1355 /* structure for epll configuration used in audio clock configuration */
1356 struct set_epll_con_val {
1357 	unsigned int freq_out;		/* frequency out */
1358 	unsigned int en_lock_det;	/* enable lock detect */
1359 	unsigned int m_div;		/* m divider value */
1360 	unsigned int p_div;		/* p divider value */
1361 	unsigned int s_div;		/* s divider value */
1362 	unsigned int k_dsm;		/* k value of delta signal modulator */
1363 };
1364 #endif
1365 
1366 #define MPLL_FOUT_SEL_SHIFT	4
1367 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
1368 #define TIMEOUT_EPLL_LOCK		1000
1369 
1370 #define AUDIO_0_RATIO_MASK		0x0f
1371 #define AUDIO_1_RATIO_MASK		0x0f
1372 
1373 #define AUDIO0_SEL_MASK			0xf
1374 #define EXYNOS5420_AUDIO0_SEL_MASK	(0x3 << 28)
1375 #define AUDIO1_SEL_MASK			0xf
1376 
1377 #define CLK_SRC_SCLK_EPLL		0x7
1378 #define EXYNOS5420_CLK_SRC_SCLK_EPLL	(0x6 << 28)
1379 #define CLK_SRC_MOUT_EPLL		(1<<12)
1380 #define EXYNOS5420_CLK_SRC_MOUT_EPLL	BIT(20)
1381 #define AUDIO_CLKMUX_ASS		(1<<0)
1382 
1383 /* CON0 bit-fields */
1384 #define EPLL_CON0_MDIV_MASK		0x1ff
1385 #define EPLL_CON0_PDIV_MASK		0x3f
1386 #define EPLL_CON0_SDIV_MASK		0x7
1387 #define EPLL_CON0_MDIV_SHIFT		16
1388 #define EPLL_CON0_PDIV_SHIFT		8
1389 #define EPLL_CON0_SDIV_SHIFT		0
1390 #define EPLL_CON0_LOCK_DET_EN_SHIFT	28
1391 #define EPLL_CON0_LOCK_DET_EN_MASK	1
1392 
1393 #define MPLL_FOUT_SEL_MASK	0x1
1394 #define BPLL_FOUT_SEL_SHIFT	0
1395 #define BPLL_FOUT_SEL_MASK	0x1
1396 #endif
1397