1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2019-2021 NXP 4 */ 5 6 #ifndef __L1028A_COMMON_H 7 #define __L1028A_COMMON_H 8 9 #define CONFIG_REMAKE_ELF 10 #define CONFIG_MP 11 12 #include <asm/arch/stream_id_lsch3.h> 13 #include <asm/arch/config.h> 14 #include <asm/arch/soc.h> 15 16 /* Link Definitions */ 17 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 18 19 #define CONFIG_SKIP_LOWLEVEL_INIT 20 21 #define CONFIG_VERY_BIG_RAM 22 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 23 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 24 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 25 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL 26 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 27 28 /* 29 * SMP Definitinos 30 */ 31 #define CPU_RELEASE_ADDR secondary_boot_addr 32 33 /* Generic Timer Definitions */ 34 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 35 36 /* Size of malloc() pool */ 37 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 38 39 /* GPIO */ 40 #ifdef CONFIG_DM_GPIO 41 #ifndef CONFIG_MPC8XXX_GPIO 42 #define CONFIG_MPC8XXX_GPIO 43 #endif 44 #endif 45 46 /* I2C */ 47 #if !CONFIG_IS_ENABLED(DM_I2C) 48 #define CONFIG_SYS_I2C 49 #endif 50 51 /* Serial Port */ 52 #define CONFIG_SYS_NS16550_SERIAL 53 #define CONFIG_SYS_NS16550_REG_SIZE 1 54 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) 55 56 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 57 58 /* Miscellaneous configurable options */ 59 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 60 61 /* Physical Memory Map */ 62 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 63 64 #define CONFIG_HWCONFIG 65 #define HWCONFIG_BUFFER_SIZE 128 66 67 #define BOOT_TARGET_DEVICES(func) \ 68 func(MMC, mmc, 0) \ 69 func(MMC, mmc, 1) \ 70 func(USB, usb, 0) \ 71 func(DHCP, dhcp, na) 72 #include <config_distro_bootcmd.h> 73 74 #undef CONFIG_BOOTCOMMAND 75 76 #define XSPI_NOR_BOOTCOMMAND \ 77 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \ 78 "env exists secureboot && esbc_halt;;" 79 #define SD_BOOTCOMMAND \ 80 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \ 81 "env exists secureboot && esbc_halt;" 82 #define SD2_BOOTCOMMAND \ 83 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \ 84 "env exists secureboot && esbc_halt;" 85 86 /* Monitor Command Prompt */ 87 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 88 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 89 sizeof(CONFIG_SYS_PROMPT) + 16) 90 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 91 92 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 93 94 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 95 96 #define OCRAM_NONSECURE_SIZE 0x00010000 97 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 98 99 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 100 101 /* I2C bus multiplexer */ 102 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 103 #define I2C_MUX_CH_DEFAULT 0x8 104 105 /* EEPROM */ 106 #define CONFIG_ID_EEPROM 107 #define CONFIG_SYS_I2C_EEPROM_NXID 108 #define CONFIG_SYS_EEPROM_BUS_NUM 0 109 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 110 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 112 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 113 114 /* DisplayPort */ 115 #define DP_PWD_EN_DEFAULT_MASK 0x8 116 117 #ifdef CONFIG_NXP_ESBC 118 #include <asm/fsl_secure_boot.h> 119 #endif 120 121 /* Ethernet */ 122 /* smallest ENETC BD ring has 8 entries */ 123 #define CONFIG_SYS_RX_ETH_BUFFER 8 124 125 #endif /* __L1028A_COMMON_H */ 126