1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2018 Marvell International Ltd.
4 */
5
6 #ifndef NIC_H
7 #define NIC_H
8
9 #include <linux/netdevice.h>
10 #include "bgx.h"
11
12 #define PCI_DEVICE_ID_CAVIUM_NICVF_1 0x0011
13
14 /* Subsystem device IDs */
15 #define PCI_SUBSYS_DEVID_88XX_NIC_PF 0xA11E
16 #define PCI_SUBSYS_DEVID_81XX_NIC_PF 0xA21E
17 #define PCI_SUBSYS_DEVID_83XX_NIC_PF 0xA31E
18
19 #define PCI_SUBSYS_DEVID_88XX_PASS1_NIC_VF 0xA11E
20 #define PCI_SUBSYS_DEVID_88XX_NIC_VF 0xA134
21 #define PCI_SUBSYS_DEVID_81XX_NIC_VF 0xA234
22 #define PCI_SUBSYS_DEVID_83XX_NIC_VF 0xA334
23
24 #define NIC_INTF_COUNT 2 /* Interfaces btw VNIC and TNS/BGX */
25 #define NIC_CHANS_PER_INF 128
26 #define NIC_MAX_CHANS (NIC_INTF_COUNT * NIC_CHANS_PER_INF)
27
28 /* PCI BAR nos */
29 #define PCI_CFG_REG_BAR_NUM 0
30 #define PCI_MSIX_REG_BAR_NUM 4
31
32 /* NIC SRIOV VF count */
33 #define MAX_NUM_VFS_SUPPORTED 128
34 #define DEFAULT_NUM_VF_ENABLED 8
35
36 #define NIC_TNS_BYPASS_MODE 0
37 #define NIC_TNS_MODE 1
38
39 /* NIC priv flags */
40 #define NIC_SRIOV_ENABLED BIT(0)
41 #define NIC_TNS_ENABLED BIT(1)
42
43 /* VNIC HW optimiation features */
44 #define VNIC_RX_CSUM_OFFLOAD_SUPPORT
45 #undef VNIC_TX_CSUM_OFFLOAD_SUPPORT
46 #undef VNIC_SG_SUPPORT
47 #undef VNIC_TSO_SUPPORT
48 #undef VNIC_LRO_SUPPORT
49 #undef VNIC_RSS_SUPPORT
50
51 /* TSO not supported in Thunder pass1 */
52 #ifdef VNIC_TSO_SUPPORT
53 #define VNIC_SW_TSO_SUPPORT
54 #undef VNIC_HW_TSO_SUPPORT
55 #endif
56
57 /* ETHTOOL enable or disable, undef this to disable */
58 #define NICVF_ETHTOOL_ENABLE
59
60 /* Min/Max packet size */
61 #define NIC_HW_MIN_FRS 64
62 #define NIC_HW_MAX_FRS 9200 /* 9216 max packet including FCS */
63
64 /* Max pkinds */
65 #define NIC_MAX_PKIND 16
66
67 /* Max when CPI_ALG is IP diffserv */
68 #define NIC_MAX_CPI_PER_LMAC 64
69
70 /* NIC VF Interrupts */
71 #define NICVF_INTR_CQ 0
72 #define NICVF_INTR_SQ 1
73 #define NICVF_INTR_RBDR 2
74 #define NICVF_INTR_PKT_DROP 3
75 #define NICVF_INTR_TCP_TIMER 4
76 #define NICVF_INTR_MBOX 5
77 #define NICVF_INTR_QS_ERR 6
78
79 #define NICVF_INTR_CQ_SHIFT 0
80 #define NICVF_INTR_SQ_SHIFT 8
81 #define NICVF_INTR_RBDR_SHIFT 16
82 #define NICVF_INTR_PKT_DROP_SHIFT 20
83 #define NICVF_INTR_TCP_TIMER_SHIFT 21
84 #define NICVF_INTR_MBOX_SHIFT 22
85 #define NICVF_INTR_QS_ERR_SHIFT 23
86
87 #define NICVF_INTR_CQ_MASK (0xFF << NICVF_INTR_CQ_SHIFT)
88 #define NICVF_INTR_SQ_MASK (0xFF << NICVF_INTR_SQ_SHIFT)
89 #define NICVF_INTR_RBDR_MASK (0x03 << NICVF_INTR_RBDR_SHIFT)
90 #define NICVF_INTR_PKT_DROP_MASK BIT(NICVF_INTR_PKT_DROP_SHIFT)
91 #define NICVF_INTR_TCP_TIMER_MASK BIT(NICVF_INTR_TCP_TIMER_SHIFT)
92 #define NICVF_INTR_MBOX_MASK BIT(NICVF_INTR_MBOX_SHIFT)
93 #define NICVF_INTR_QS_ERR_MASK BIT(NICVF_INTR_QS_ERR_SHIFT)
94
95 /* MSI-X interrupts */
96 #define NIC_PF_MSIX_VECTORS 10
97 #define NIC_VF_MSIX_VECTORS 20
98
99 #define NIC_PF_INTR_ID_ECC0_SBE 0
100 #define NIC_PF_INTR_ID_ECC0_DBE 1
101 #define NIC_PF_INTR_ID_ECC1_SBE 2
102 #define NIC_PF_INTR_ID_ECC1_DBE 3
103 #define NIC_PF_INTR_ID_ECC2_SBE 4
104 #define NIC_PF_INTR_ID_ECC2_DBE 5
105 #define NIC_PF_INTR_ID_ECC3_SBE 6
106 #define NIC_PF_INTR_ID_ECC3_DBE 7
107 #define NIC_PF_INTR_ID_MBOX0 8
108 #define NIC_PF_INTR_ID_MBOX1 9
109
110 /* Global timer for CQ timer thresh interrupts
111 * Calculated for SCLK of 700Mhz
112 * value written should be a 1/16thof what is expected
113 *
114 * 1 tick per ms
115 */
116 #define NICPF_CLK_PER_INT_TICK 43750
117
118 struct nicvf_cq_poll {
119 u8 cq_idx; /* Completion queue index */
120 };
121
122 #define NIC_MAX_RSS_HASH_BITS 8
123 #define NIC_MAX_RSS_IDR_TBL_SIZE BIT(NIC_MAX_RSS_HASH_BITS)
124 #define RSS_HASH_KEY_SIZE 5 /* 320 bit key */
125
126 #ifdef VNIC_RSS_SUPPORT
127 struct nicvf_rss_info {
128 bool enable;
129 #define RSS_L2_EXTENDED_HASH_ENA BIT(0)
130 #define RSS_IP_HASH_ENA BIT(1)
131 #define RSS_TCP_HASH_ENA BIT(2)
132 #define RSS_TCP_SYN_DIS BIT(3)
133 #define RSS_UDP_HASH_ENA BIT(4)
134 #define RSS_L4_EXTENDED_HASH_ENA BIT(5)
135 #define RSS_ROCE_ENA BIT(6)
136 #define RSS_L3_BI_DIRECTION_ENA BIT(7)
137 #define RSS_L4_BI_DIRECTION_ENA BIT(8)
138 u64 cfg;
139 u8 hash_bits;
140 u16 rss_size;
141 u8 ind_tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
142 u64 key[RSS_HASH_KEY_SIZE];
143 };
144 #endif
145
146 enum rx_stats_reg_offset {
147 RX_OCTS = 0x0,
148 RX_UCAST = 0x1,
149 RX_BCAST = 0x2,
150 RX_MCAST = 0x3,
151 RX_RED = 0x4,
152 RX_RED_OCTS = 0x5,
153 RX_ORUN = 0x6,
154 RX_ORUN_OCTS = 0x7,
155 RX_FCS = 0x8,
156 RX_L2ERR = 0x9,
157 RX_DRP_BCAST = 0xa,
158 RX_DRP_MCAST = 0xb,
159 RX_DRP_L3BCAST = 0xc,
160 RX_DRP_L3MCAST = 0xd,
161 RX_STATS_ENUM_LAST,
162 };
163
164 enum tx_stats_reg_offset {
165 TX_OCTS = 0x0,
166 TX_UCAST = 0x1,
167 TX_BCAST = 0x2,
168 TX_MCAST = 0x3,
169 TX_DROP = 0x4,
170 TX_STATS_ENUM_LAST,
171 };
172
173 struct nicvf_hw_stats {
174 u64 rx_bytes_ok;
175 u64 rx_ucast_frames_ok;
176 u64 rx_bcast_frames_ok;
177 u64 rx_mcast_frames_ok;
178 u64 rx_fcs_errors;
179 u64 rx_l2_errors;
180 u64 rx_drop_red;
181 u64 rx_drop_red_bytes;
182 u64 rx_drop_overrun;
183 u64 rx_drop_overrun_bytes;
184 u64 rx_drop_bcast;
185 u64 rx_drop_mcast;
186 u64 rx_drop_l3_bcast;
187 u64 rx_drop_l3_mcast;
188 u64 tx_bytes_ok;
189 u64 tx_ucast_frames_ok;
190 u64 tx_bcast_frames_ok;
191 u64 tx_mcast_frames_ok;
192 u64 tx_drops;
193 };
194
195 struct nicvf_drv_stats {
196 /* Rx */
197 u64 rx_frames_ok;
198 u64 rx_frames_64;
199 u64 rx_frames_127;
200 u64 rx_frames_255;
201 u64 rx_frames_511;
202 u64 rx_frames_1023;
203 u64 rx_frames_1518;
204 u64 rx_frames_jumbo;
205 u64 rx_drops;
206 /* Tx */
207 u64 tx_frames_ok;
208 u64 tx_drops;
209 u64 tx_busy;
210 u64 tx_tso;
211 };
212
213 struct hw_info {
214 u8 bgx_cnt;
215 u8 chans_per_lmac;
216 u8 chans_per_bgx; /* Rx/Tx chans */
217 u8 chans_per_rgx;
218 u8 chans_per_lbk;
219 u16 cpi_cnt;
220 u16 rssi_cnt;
221 u16 rss_ind_tbl_size;
222 u16 tl4_cnt;
223 u16 tl3_cnt;
224 u8 tl2_cnt;
225 u8 tl1_cnt;
226 bool tl1_per_bgx; /* TL1 per BGX or per LMAC */
227 u8 model_id;
228 };
229
230 struct nicvf {
231 struct udevice *dev;
232 u8 vf_id;
233 bool sqs_mode:1;
234 bool loopback_supported:1;
235 u8 tns_mode;
236 u8 node;
237 u16 mtu;
238 struct queue_set *qs;
239 #define MAX_SQS_PER_VF_SINGLE_NODE 5
240 #define MAX_SQS_PER_VF 11
241 u8 num_qs;
242 void *addnl_qs;
243 u16 vf_mtu;
244 void __iomem *reg_base;
245 #define MAX_QUEUES_PER_QSET 8
246 struct nicvf_cq_poll *napi[8];
247
248 u8 cpi_alg;
249
250 struct nicvf_hw_stats stats;
251 struct nicvf_drv_stats drv_stats;
252
253 struct nicpf *nicpf;
254
255 /* VF <-> PF mailbox communication */
256 bool pf_acked;
257 bool pf_nacked;
258 bool set_mac_pending;
259
260 bool link_up;
261 u8 duplex;
262 u32 speed;
263 u8 rev_id;
264 u8 rx_queues;
265 u8 tx_queues;
266
267 bool open;
268 bool rb_alloc_fail;
269 void *rcv_buf;
270 bool hw_tso;
271 };
272
node_id(void * addr)273 static inline int node_id(void *addr)
274 {
275 return ((uintptr_t)addr >> 44) & 0x3;
276 }
277
278 struct nicpf {
279 struct udevice *udev;
280 struct hw_info *hw;
281 u8 node;
282 unsigned int flags;
283 u16 total_vf_cnt; /* Total num of VF supported */
284 u16 num_vf_en; /* No of VF enabled */
285 void __iomem *reg_base; /* Register start address */
286 u16 rss_ind_tbl_size;
287 u8 num_sqs_en; /* Secondary qsets enabled */
288 u64 nicvf[MAX_NUM_VFS_SUPPORTED];
289 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
290 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
291 bool sqs_used[MAX_NUM_VFS_SUPPORTED];
292 struct pkind_cfg pkind;
293 u8 bgx_cnt;
294 u8 rev_id;
295 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) ((((bgx) & 0xF) << 4) | ((lmac) & 0xF))
296 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) (((map) >> 4) & 0xF)
297 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) ((map) & 0xF)
298 u8 vf_lmac_map[MAX_LMAC];
299 u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
300 u64 mac[MAX_NUM_VFS_SUPPORTED];
301 bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
302 u8 link[MAX_LMAC];
303 u8 duplex[MAX_LMAC];
304 u32 speed[MAX_LMAC];
305 bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
306 u16 rssi_base[MAX_NUM_VFS_SUPPORTED];
307 u8 lmac_cnt;
308 };
309
310 /* PF <--> VF Mailbox communication
311 * Eight 64bit registers are shared between PF and VF.
312 * Separate set for each VF.
313 * Writing '1' into last register mbx7 means end of message.
314 */
315
316 /* PF <--> VF mailbox communication */
317 #define NIC_PF_VF_MAILBOX_SIZE 2
318 #define NIC_PF_VF_MBX_TIMEOUT 2000 /* ms */
319
320 /* Mailbox message types */
321 #define NIC_MBOX_MSG_READY 0x01 /* Is PF ready to rcv msgs */
322 #define NIC_MBOX_MSG_ACK 0x02 /* ACK the message received */
323 #define NIC_MBOX_MSG_NACK 0x03 /* NACK the message received */
324 #define NIC_MBOX_MSG_QS_CFG 0x04 /* Configure Qset */
325 #define NIC_MBOX_MSG_RQ_CFG 0x05 /* Configure receive queue */
326 #define NIC_MBOX_MSG_SQ_CFG 0x06 /* Configure Send queue */
327 #define NIC_MBOX_MSG_RQ_DROP_CFG 0x07 /* Configure receive queue */
328 #define NIC_MBOX_MSG_SET_MAC 0x08 /* Add MAC ID to DMAC filter */
329 #define NIC_MBOX_MSG_SET_MAX_FRS 0x09 /* Set max frame size */
330 #define NIC_MBOX_MSG_CPI_CFG 0x0A /* Config CPI, RSSI */
331 #define NIC_MBOX_MSG_RSS_SIZE 0x0B /* Get RSS indir_tbl size */
332 #define NIC_MBOX_MSG_RSS_CFG 0x0C /* Config RSS table */
333 #define NIC_MBOX_MSG_RSS_CFG_CONT 0x0D /* RSS config continuation */
334 #define NIC_MBOX_MSG_RQ_BP_CFG 0x0E /* RQ backpressure config */
335 #define NIC_MBOX_MSG_RQ_SW_SYNC 0x0F /* Flush inflight pkts to RQ */
336 #define NIC_MBOX_MSG_BGX_STATS 0x10 /* Get stats from BGX */
337 #define NIC_MBOX_MSG_BGX_LINK_CHANGE 0x11 /* BGX:LMAC link status */
338 #define NIC_MBOX_MSG_ALLOC_SQS 0x12 /* Allocate secondary Qset */
339 #define NIC_MBOX_MSG_NICVF_PTR 0x13 /* Send nicvf ptr to PF */
340 #define NIC_MBOX_MSG_PNICVF_PTR 0x14 /* Get primary qset nicvf ptr */
341 #define NIC_MBOX_MSG_SNICVF_PTR 0x15 /* Send sqet nicvf ptr to PVF */
342 #define NIC_MBOX_MSG_LOOPBACK 0x16 /* Set interface in loopback */
343 #define NIC_MBOX_MSG_CFG_DONE 0xF0 /* VF configuration done */
344 #define NIC_MBOX_MSG_SHUTDOWN 0xF1 /* VF is being shutdown */
345
346 struct nic_cfg_msg {
347 u8 msg;
348 u8 vf_id;
349 u8 node_id;
350 bool tns_mode:1;
351 bool sqs_mode:1;
352 bool loopback_supported:1;
353 u8 mac_addr[6];
354 };
355
356 /* Qset configuration */
357 struct qs_cfg_msg {
358 u8 msg;
359 u8 num;
360 u8 sqs_count;
361 u64 cfg;
362 };
363
364 /* Receive queue configuration */
365 struct rq_cfg_msg {
366 u8 msg;
367 u8 qs_num;
368 u8 rq_num;
369 u64 cfg;
370 };
371
372 /* Send queue configuration */
373 struct sq_cfg_msg {
374 u8 msg;
375 u8 qs_num;
376 u8 sq_num;
377 bool sqs_mode;
378 u64 cfg;
379 };
380
381 /* Set VF's MAC address */
382 struct set_mac_msg {
383 u8 msg;
384 u8 vf_id;
385 u8 mac_addr[6];
386 };
387
388 /* Set Maximum frame size */
389 struct set_frs_msg {
390 u8 msg;
391 u8 vf_id;
392 u16 max_frs;
393 };
394
395 /* Set CPI algorithm type */
396 struct cpi_cfg_msg {
397 u8 msg;
398 u8 vf_id;
399 u8 rq_cnt;
400 u8 cpi_alg;
401 };
402
403 /* Get RSS table size */
404 struct rss_sz_msg {
405 u8 msg;
406 u8 vf_id;
407 u16 ind_tbl_size;
408 };
409
410 /* Set RSS configuration */
411 struct rss_cfg_msg {
412 u8 msg;
413 u8 vf_id;
414 u8 hash_bits;
415 u8 tbl_len;
416 u8 tbl_offset;
417 #define RSS_IND_TBL_LEN_PER_MBX_MSG 8
418 u8 ind_tbl[RSS_IND_TBL_LEN_PER_MBX_MSG];
419 };
420
421 struct bgx_stats_msg {
422 u8 msg;
423 u8 vf_id;
424 u8 rx;
425 u8 idx;
426 u64 stats;
427 };
428
429 /* Physical interface link status */
430 struct bgx_link_status {
431 u8 msg;
432 u8 link_up;
433 u8 duplex;
434 u32 speed;
435 };
436
437 #ifdef VNIC_MULTI_QSET_SUPPORT
438 /* Get Extra Qset IDs */
439 struct sqs_alloc {
440 u8 msg;
441 u8 vf_id;
442 u8 qs_count;
443 };
444
445 struct nicvf_ptr {
446 u8 msg;
447 u8 vf_id;
448 bool sqs_mode;
449 u8 sqs_id;
450 u64 nicvf;
451 };
452 #endif
453
454 /* Set interface in loopback mode */
455 struct set_loopback {
456 u8 msg;
457 u8 vf_id;
458 bool enable;
459 };
460
461 /* 128 bit shared memory between PF and each VF */
462 union nic_mbx {
463 struct { u8 msg; } msg;
464 struct nic_cfg_msg nic_cfg;
465 struct qs_cfg_msg qs;
466 struct rq_cfg_msg rq;
467 struct sq_cfg_msg sq;
468 struct set_mac_msg mac;
469 struct set_frs_msg frs;
470 struct cpi_cfg_msg cpi_cfg;
471 struct rss_sz_msg rss_size;
472 struct rss_cfg_msg rss_cfg;
473 struct bgx_stats_msg bgx_stats;
474 struct bgx_link_status link_status;
475 #ifdef VNIC_MULTI_QSET_SUPPORT
476 struct sqs_alloc sqs_alloc;
477 struct nicvf_ptr nicvf;
478 #endif
479 struct set_loopback lbk;
480 };
481
482 int nicvf_set_real_num_queues(struct udevice *dev,
483 int tx_queues, int rx_queues);
484 int nicvf_open(struct udevice *dev);
485 void nicvf_stop(struct udevice *dev);
486 int nicvf_send_msg_to_pf(struct nicvf *vf, union nic_mbx *mbx);
487 void nicvf_update_stats(struct nicvf *nic);
488
489 void nic_handle_mbx_intr(struct nicpf *nic, int vf);
490
491 int bgx_poll_for_link(int node, int bgx_idx, int lmacid);
492 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid);
493 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac);
494 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable);
495 void bgx_lmac_internal_loopback(int node, int bgx_idx,
496 int lmac_idx, bool enable);
497
pass1_silicon(unsigned int revision,int model_id)498 static inline bool pass1_silicon(unsigned int revision, int model_id)
499 {
500 return ((revision < 8) && (model_id == 0x88));
501 }
502
pass2_silicon(unsigned int revision,int model_id)503 static inline bool pass2_silicon(unsigned int revision, int model_id)
504 {
505 return ((revision >= 8) && (model_id == 0x88));
506 }
507
508 #endif /* NIC_H */
509