1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007-2012 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <env.h>
8 #include <init.h>
9 #include <log.h>
10 #include <malloc.h>
11 #include <asm/fsl_serdes.h>
12 #include <asm/global_data.h>
13 #include <linux/delay.h>
14
15 DECLARE_GLOBAL_DATA_PTR;
16
17 /*
18 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
19 *
20 * Initialize controller and call the common driver/pci pci_hose_scan to
21 * scan for bridges and devices.
22 *
23 * Hose fields which need to be pre-initialized by board specific code:
24 * regions[]
25 * first_busno
26 *
27 * Fields updated:
28 * last_busno
29 */
30
31 #include <pci.h>
32 #include <asm/io.h>
33 #include <asm/fsl_pci.h>
34
35 #define MAX_PCI_REGIONS 7
36
37 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
38 #define CONFIG_SYS_PCI_MEMORY_BUS 0
39 #endif
40
41 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
42 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
43 #endif
44
45 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
46 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
47 #endif
48
49 /* Setup one inbound ATMU window.
50 *
51 * We let the caller decide what the window size should be
52 */
set_inbound_window(volatile pit_t * pi,struct pci_region * r,u64 size)53 static void set_inbound_window(volatile pit_t *pi,
54 struct pci_region *r,
55 u64 size)
56 {
57 u32 sz = (__ilog2_u64(size) - 1);
58 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
59 u32 flag = 0;
60 #else
61 u32 flag = PIWAR_LOCAL;
62 #endif
63
64 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
65
66 out_be32(&pi->pitar, r->phys_start >> 12);
67 out_be32(&pi->piwbar, r->bus_start >> 12);
68 #ifdef CONFIG_SYS_PCI_64BIT
69 out_be32(&pi->piwbear, r->bus_start >> 44);
70 #else
71 out_be32(&pi->piwbear, 0);
72 #endif
73 if (r->flags & PCI_REGION_PREFETCH)
74 flag |= PIWAR_PF;
75 out_be32(&pi->piwar, flag | sz);
76 }
77
fsl_setup_hose(struct pci_controller * hose,unsigned long addr)78 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
79 {
80 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
81
82 /* Reset hose to make sure its in a clean state */
83 memset(hose, 0, sizeof(struct pci_controller));
84
85 hose->regions = (struct pci_region *)
86 calloc(1, MAX_PCI_REGIONS * sizeof(struct pci_region));
87
88 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
89
90 return fsl_is_pci_agent(hose);
91 }
92
fsl_pci_setup_inbound_windows(struct pci_controller * hose,u64 out_lo,u8 pcie_cap,volatile pit_t * pi)93 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
94 u64 out_lo, u8 pcie_cap,
95 volatile pit_t *pi)
96 {
97 struct pci_region *r = hose->regions + hose->region_count;
98 u64 sz = min((u64)gd->ram_size, (1ull << 32));
99
100 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
101 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
102 pci_size_t pci_sz;
103
104 /* we have no space available for inbound memory mapping */
105 if (bus_start > out_lo) {
106 printf ("no space for inbound mapping of memory\n");
107 return 0;
108 }
109
110 /* limit size */
111 if ((bus_start + sz) > out_lo) {
112 sz = out_lo - bus_start;
113 debug ("limiting size to %llx\n", sz);
114 }
115
116 pci_sz = 1ull << __ilog2_u64(sz);
117 /*
118 * we can overlap inbound/outbound windows on PCI-E since RX & TX
119 * links a separate
120 */
121 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
122 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
123 (u64)bus_start, (u64)phys_start, (u64)sz);
124 pci_set_region(r, bus_start, phys_start, sz,
125 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
126 PCI_REGION_PREFETCH);
127
128 /* if we aren't an exact power of two match, pci_sz is smaller
129 * round it up to the next power of two. We report the actual
130 * size to pci region tracking.
131 */
132 if (pci_sz != sz)
133 sz = 2ull << __ilog2_u64(sz);
134
135 set_inbound_window(pi--, r++, sz);
136 sz = 0; /* make sure we dont set the R2 window */
137 } else {
138 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
139 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
140 pci_set_region(r, bus_start, phys_start, pci_sz,
141 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
142 PCI_REGION_PREFETCH);
143 set_inbound_window(pi--, r++, pci_sz);
144
145 sz -= pci_sz;
146 bus_start += pci_sz;
147 phys_start += pci_sz;
148
149 pci_sz = 1ull << __ilog2_u64(sz);
150 if (sz) {
151 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
152 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
153 pci_set_region(r, bus_start, phys_start, pci_sz,
154 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
155 PCI_REGION_PREFETCH);
156 set_inbound_window(pi--, r++, pci_sz);
157 sz -= pci_sz;
158 bus_start += pci_sz;
159 phys_start += pci_sz;
160 }
161 }
162
163 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
164 /*
165 * On 64-bit capable systems, set up a mapping for all of DRAM
166 * in high pci address space.
167 */
168 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
169 /* round up to the next largest power of two */
170 if (gd->ram_size > pci_sz)
171 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
172 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
173 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
174 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
175 (u64)pci_sz);
176 pci_set_region(r,
177 CONFIG_SYS_PCI64_MEMORY_BUS,
178 CONFIG_SYS_PCI_MEMORY_PHYS,
179 pci_sz,
180 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
181 PCI_REGION_PREFETCH);
182 set_inbound_window(pi--, r++, pci_sz);
183 #else
184 pci_sz = 1ull << __ilog2_u64(sz);
185 if (sz) {
186 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
187 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
188 pci_set_region(r, bus_start, phys_start, pci_sz,
189 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
190 PCI_REGION_PREFETCH);
191 sz -= pci_sz;
192 bus_start += pci_sz;
193 phys_start += pci_sz;
194 set_inbound_window(pi--, r++, pci_sz);
195 }
196 #endif
197
198 #ifdef CONFIG_PHYS_64BIT
199 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
200 printf("Was not able to map all of memory via "
201 "inbound windows -- %lld remaining\n", sz);
202 #endif
203
204 hose->region_count = r - hose->regions;
205
206 return 1;
207 }
208
209 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
fsl_pcie_boot_master(pit_t * pi)210 static void fsl_pcie_boot_master(pit_t *pi)
211 {
212 /* configure inbound window for slave's u-boot image */
213 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
214 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
215 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
216 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
217 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
218 struct pci_region r_inbound;
219 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
220 - 1;
221 pci_set_region(&r_inbound,
222 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
223 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
224 sz_inbound,
225 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
226
227 set_inbound_window(pi--, &r_inbound,
228 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
229
230 /* configure inbound window for slave's u-boot image */
231 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
232 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
233 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
234 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
235 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
236 pci_set_region(&r_inbound,
237 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
238 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
239 sz_inbound,
240 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
241
242 set_inbound_window(pi--, &r_inbound,
243 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
244
245 /* configure inbound window for slave's ucode and ENV */
246 debug("PCIEBOOT - MASTER: Inbound window for slave's "
247 "ucode and ENV; "
248 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
249 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
250 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
251 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
252 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
253 - 1;
254 pci_set_region(&r_inbound,
255 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
256 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
257 sz_inbound,
258 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
259
260 set_inbound_window(pi--, &r_inbound,
261 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
262 }
263
fsl_pcie_boot_master_release_slave(int port)264 static void fsl_pcie_boot_master_release_slave(int port)
265 {
266 unsigned long release_addr;
267
268 /* now release slave's core 0 */
269 switch (port) {
270 case 1:
271 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
272 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
273 break;
274 #ifdef CONFIG_SYS_PCIE2_MEM_VIRT
275 case 2:
276 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
277 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
278 break;
279 #endif
280 #ifdef CONFIG_SYS_PCIE3_MEM_VIRT
281 case 3:
282 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
283 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
284 break;
285 #endif
286 default:
287 release_addr = 0;
288 break;
289 }
290 if (release_addr != 0) {
291 out_be32((void *)release_addr,
292 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
293 debug("PCIEBOOT - MASTER: "
294 "Release slave successfully! Now the slave should start up!\n");
295 } else {
296 debug("PCIEBOOT - MASTER: "
297 "Release slave failed!\n");
298 }
299 }
300 #endif
301
fsl_pci_init(struct pci_controller * hose,struct fsl_pci_info * pci_info)302 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
303 {
304 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
305 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
306 u16 temp16;
307 u32 temp32;
308 u32 block_rev;
309 int enabled, r, inbound = 0;
310 u16 ltssm;
311 u8 temp8, pcie_cap;
312 int pcie_cap_pos;
313 int pci_dcr;
314 int pci_dsr;
315 int pci_lsr;
316
317 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
318 int pci_lcr;
319 #endif
320
321 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
322 struct pci_region *reg = hose->regions + hose->region_count;
323 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
324
325 /* Initialize ATMU registers based on hose regions and flags */
326 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
327 volatile pit_t *pi;
328
329 u64 out_hi = 0, out_lo = -1ULL;
330 u32 pcicsrbar, pcicsrbar_sz;
331
332 pci_setup_indirect(hose, cfg_addr, cfg_data);
333
334 #ifdef PEX_CCB_DIV
335 /* Configure the PCIE controller core clock ratio */
336 pci_hose_write_config_dword(hose, dev, 0x440,
337 ((gd->bus_clk / 1000000) *
338 (16 / PEX_CCB_DIV)) / 333);
339 #endif
340 block_rev = in_be32(&pci->block_rev1);
341 if (PEX_IP_BLK_REV_2_2 <= block_rev) {
342 pi = &pci->pit[2]; /* 0xDC0 */
343 } else {
344 pi = &pci->pit[3]; /* 0xDE0 */
345 }
346
347 /* Handle setup of outbound windows first */
348 for (r = 0; r < hose->region_count; r++) {
349 unsigned long flags = hose->regions[r].flags;
350 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
351
352 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
353 if (flags != PCI_REGION_SYS_MEMORY) {
354 u64 start = hose->regions[r].bus_start;
355 u64 end = start + hose->regions[r].size;
356
357 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
358 out_be32(&po->potar, start >> 12);
359 #ifdef CONFIG_SYS_PCI_64BIT
360 out_be32(&po->potear, start >> 44);
361 #else
362 out_be32(&po->potear, 0);
363 #endif
364 if (hose->regions[r].flags & PCI_REGION_IO) {
365 out_be32(&po->powar, POWAR_EN | sz |
366 POWAR_IO_READ | POWAR_IO_WRITE);
367 } else {
368 out_be32(&po->powar, POWAR_EN | sz |
369 POWAR_MEM_READ | POWAR_MEM_WRITE);
370 out_lo = min(start, out_lo);
371 out_hi = max(end, out_hi);
372 }
373 po++;
374 }
375 }
376 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
377
378 /* setup PCSRBAR/PEXCSRBAR */
379 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
380 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
381 pcicsrbar_sz = ~pcicsrbar_sz + 1;
382
383 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
384 (out_lo > 0x100000000ull))
385 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
386 else
387 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
388 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
389
390 out_lo = min(out_lo, (u64)pcicsrbar);
391
392 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
393
394 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
395 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
396 hose->region_count++;
397
398 /* see if we are a PCIe or PCI controller */
399 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
400 pci_dcr = pcie_cap_pos + 0x08;
401 pci_dsr = pcie_cap_pos + 0x0a;
402 pci_lsr = pcie_cap_pos + 0x12;
403
404 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
405
406 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
407 /* boot from PCIE --master */
408 char *s = env_get("bootmaster");
409 char pcie[6];
410 sprintf(pcie, "PCIE%d", pci_info->pci_num);
411
412 if (s && (strcmp(s, pcie) == 0)) {
413 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
414 pci_info->pci_num);
415 fsl_pcie_boot_master((pit_t *)pi);
416 } else {
417 /* inbound */
418 inbound = fsl_pci_setup_inbound_windows(hose,
419 out_lo, pcie_cap, pi);
420 }
421 #else
422 /* inbound */
423 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
424 #endif
425
426 for (r = 0; r < hose->region_count; r++)
427 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
428 (u64)hose->regions[r].phys_start,
429 (u64)hose->regions[r].bus_start,
430 (u64)hose->regions[r].size,
431 hose->regions[r].flags);
432
433 pci_register_hose(hose);
434 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
435 hose->current_busno = hose->first_busno;
436
437 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
438 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
439 * - Master abort (pci)
440 * - Master PERR (pci)
441 * - ICCA (PCIe)
442 */
443 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
444 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
445 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
446
447 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
448 pci_lcr = pcie_cap_pos + 0x10;
449 temp32 = 0;
450 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
451 temp32 &= ~0x03; /* Disable ASPM */
452 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
453 udelay(1);
454 #endif
455 if (pcie_cap == PCI_CAP_ID_EXP) {
456 if (block_rev >= PEX_IP_BLK_REV_3_0) {
457 #define PEX_CSR0_LTSSM_MASK 0xFC
458 #define PEX_CSR0_LTSSM_SHIFT 2
459 ltssm = (in_be32(&pci->pex_csr0)
460 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
461 enabled = (ltssm == 0x11) ? 1 : 0;
462 #ifdef CONFIG_FSL_PCIE_RESET
463 int i;
464 /* assert PCIe reset */
465 setbits_be32(&pci->pdb_stat, 0x08000000);
466 (void) in_be32(&pci->pdb_stat);
467 udelay(1000);
468 /* clear PCIe reset */
469 clrbits_be32(&pci->pdb_stat, 0x08000000);
470 asm("sync;isync");
471 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
472 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
473 <ssm);
474 udelay(1000);
475 }
476 #endif
477 } else {
478 /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
479 /* enabled = ltssm >= PCI_LTSSM_L0; */
480 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
481 enabled = ltssm >= PCI_LTSSM_L0;
482
483 #ifdef CONFIG_FSL_PCIE_RESET
484 if (ltssm == 1) {
485 int i;
486 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
487 /* assert PCIe reset */
488 setbits_be32(&pci->pdb_stat, 0x08000000);
489 (void) in_be32(&pci->pdb_stat);
490 udelay(100);
491 debug(" Asserting PCIe reset @%p = %x\n",
492 &pci->pdb_stat, in_be32(&pci->pdb_stat));
493 /* clear PCIe reset */
494 clrbits_be32(&pci->pdb_stat, 0x08000000);
495 asm("sync;isync");
496 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
497 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
498 <ssm);
499 udelay(1000);
500 debug("....PCIe link error. "
501 "LTSSM=0x%02x.\n", ltssm);
502 }
503 enabled = ltssm >= PCI_LTSSM_L0;
504
505 /* we need to re-write the bar0 since a reset will
506 * clear it
507 */
508 pci_hose_write_config_dword(hose, dev,
509 PCI_BASE_ADDRESS_0, pcicsrbar);
510 }
511 #endif
512 }
513
514 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
515 if (enabled == 0) {
516 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
517 temp32 = in_be32(&srds_regs->srdspccr0);
518
519 if ((temp32 >> 28) == 3) {
520 int i;
521
522 out_be32(&srds_regs->srdspccr0, 2 << 28);
523 setbits_be32(&pci->pdb_stat, 0x08000000);
524 in_be32(&pci->pdb_stat);
525 udelay(100);
526 clrbits_be32(&pci->pdb_stat, 0x08000000);
527 asm("sync;isync");
528 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
529 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
530 udelay(1000);
531 }
532 enabled = ltssm >= PCI_LTSSM_L0;
533 }
534 }
535 #endif
536 if (!enabled) {
537 /* Let the user know there's no PCIe link for root
538 * complex. for endpoint, the link may not setup, so
539 * print undetermined.
540 */
541 if (fsl_is_pci_agent(hose))
542 printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
543 else
544 printf("no link, regs @ 0x%lx\n", pci_info->regs);
545 hose->last_busno = hose->first_busno;
546 return;
547 }
548
549 out_be32(&pci->pme_msg_det, 0xffffffff);
550 out_be32(&pci->pme_msg_int_en, 0xffffffff);
551
552 /* Print the negotiated PCIe link width */
553 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
554 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
555 (temp16 & 0xf), pci_info->regs);
556
557 hose->current_busno++; /* Start scan with secondary */
558 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
559 }
560
561 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
562 /* The Read-Only Write Enable bit defaults to 1 instead of 0.
563 * Set to 0 to protect the read-only registers.
564 */
565 clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
566 #endif
567
568 /* Use generic setup_device to initialize standard pci regs,
569 * but do not allocate any windows since any BAR found (such
570 * as PCSRBAR) is not in this cpu's memory space.
571 */
572 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
573 hose->pci_prefetch, hose->pci_io);
574
575 if (inbound) {
576 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
577 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
578 temp16 | PCI_COMMAND_MEMORY);
579 }
580
581 #ifndef CONFIG_PCI_NOSCAN
582 if (!fsl_is_pci_agent(hose)) {
583 debug(" Scanning PCI bus %02x\n",
584 hose->current_busno);
585 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
586 } else {
587 debug(" Not scanning PCI bus %02x. PI=%x\n",
588 hose->current_busno, temp8);
589 hose->last_busno = hose->current_busno;
590 }
591
592 /* if we are PCIe - update limit regs and subordinate busno
593 * for the virtual P2P bridge
594 */
595 if (pcie_cap == PCI_CAP_ID_EXP) {
596 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
597 }
598 #else
599 hose->last_busno = hose->current_busno;
600 #endif
601
602 /* Clear all error indications */
603 if (pcie_cap == PCI_CAP_ID_EXP)
604 out_be32(&pci->pme_msg_det, 0xffffffff);
605 out_be32(&pci->pedr, 0xffffffff);
606
607 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
608 if (temp16) {
609 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
610 }
611
612 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
613 if (temp16) {
614 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
615 }
616 }
617
fsl_is_pci_agent(struct pci_controller * hose)618 int fsl_is_pci_agent(struct pci_controller *hose)
619 {
620 int pcie_cap_pos;
621 u8 pcie_cap;
622 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
623
624 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
625 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
626 if (pcie_cap == PCI_CAP_ID_EXP) {
627 u8 header_type;
628
629 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
630 &header_type);
631 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
632 } else {
633 u8 prog_if;
634
635 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
636 /* Programming Interface (PCI_CLASS_PROG)
637 * 0 == pci host or pcie root-complex,
638 * 1 == pci agent or pcie end-point
639 */
640 return (prog_if == FSL_PROG_IF_AGENT);
641 }
642 }
643
fsl_pci_init_port(struct fsl_pci_info * pci_info,struct pci_controller * hose,int busno)644 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
645 struct pci_controller *hose, int busno)
646 {
647 volatile ccsr_fsl_pci_t *pci;
648 struct pci_region *r;
649 pci_dev_t dev = PCI_BDF(busno,0,0);
650 int pcie_cap_pos;
651 u8 pcie_cap;
652
653 pci = (ccsr_fsl_pci_t *) pci_info->regs;
654
655 /* on non-PCIe controllers we don't have pme_msg_det so this code
656 * should do nothing since the read will return 0
657 */
658 if (in_be32(&pci->pme_msg_det)) {
659 out_be32(&pci->pme_msg_det, 0xffffffff);
660 debug (" with errors. Clearing. Now 0x%08x",
661 pci->pme_msg_det);
662 }
663
664 r = hose->regions + hose->region_count;
665
666 /* outbound memory */
667 pci_set_region(r++,
668 pci_info->mem_bus,
669 pci_info->mem_phys,
670 pci_info->mem_size,
671 PCI_REGION_MEM);
672
673 /* outbound io */
674 pci_set_region(r++,
675 pci_info->io_bus,
676 pci_info->io_phys,
677 pci_info->io_size,
678 PCI_REGION_IO);
679
680 hose->region_count = r - hose->regions;
681 hose->first_busno = busno;
682
683 fsl_pci_init(hose, pci_info);
684
685 if (fsl_is_pci_agent(hose)) {
686 fsl_pci_config_unlock(hose);
687 hose->last_busno = hose->first_busno;
688 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
689 } else {
690 /* boot from PCIE --master releases slave's core 0 */
691 char *s = env_get("bootmaster");
692 char pcie[6];
693 sprintf(pcie, "PCIE%d", pci_info->pci_num);
694
695 if (s && (strcmp(s, pcie) == 0))
696 fsl_pcie_boot_master_release_slave(pci_info->pci_num);
697 #endif
698 }
699
700 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
701 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
702 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
703 "e" : "", pci_info->pci_num,
704 hose->first_busno, hose->last_busno);
705 return(hose->last_busno + 1);
706 }
707
708 /* Enable inbound PCI config cycles for agent/endpoint interface */
fsl_pci_config_unlock(struct pci_controller * hose)709 void fsl_pci_config_unlock(struct pci_controller *hose)
710 {
711 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
712 int pcie_cap_pos;
713 u8 pcie_cap;
714 u16 pbfr;
715
716 if (!fsl_is_pci_agent(hose))
717 return;
718
719 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
720 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
721 if (pcie_cap != 0x0) {
722 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
723 u32 block_rev = in_be32(&pci->block_rev1);
724 /* PCIe - set CFG_READY bit of Configuration Ready Register */
725 if (block_rev >= PEX_IP_BLK_REV_3_0)
726 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
727 else
728 pci_hose_write_config_byte(hose, dev,
729 FSL_PCIE_CFG_RDY, 0x1);
730 } else {
731 /* PCI - clear ACL bit of PBFR */
732 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
733 pbfr &= ~0x20;
734 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
735 }
736 }
737
738 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
739 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
fsl_configure_pcie(struct fsl_pci_info * info,struct pci_controller * hose,const char * connected,int busno)740 int fsl_configure_pcie(struct fsl_pci_info *info,
741 struct pci_controller *hose,
742 const char *connected, int busno)
743 {
744 int is_endpoint;
745
746 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
747 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
748
749 is_endpoint = fsl_setup_hose(hose, info->regs);
750 printf("PCIe%u: %s", info->pci_num,
751 is_endpoint ? "Endpoint" : "Root Complex");
752 if (connected)
753 printf(" of %s", connected);
754 puts(", ");
755
756 return fsl_pci_init_port(info, hose, busno);
757 }
758
759 #if defined(CONFIG_FSL_CORENET)
760 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
761 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
762 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
763 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
764 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
765 #else
766 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
767 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
768 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
769 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
770 #endif
771 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
772 #elif defined(CONFIG_MPC85xx)
773 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
774 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
775 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
776 #define _DEVDISR_PCIE4 0
777 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
778 #elif defined(CONFIG_MPC86xx)
779 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
780 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
781 #define _DEVDISR_PCIE3 0
782 #define _DEVDISR_PCIE4 0
783 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
784 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
785 #else
786 #error "No defines for DEVDISR_PCIE"
787 #endif
788
789 /* Implement a dummy function for those platforms w/o SERDES */
__board_serdes_name(enum srds_prtcl device)790 static const char *__board_serdes_name(enum srds_prtcl device)
791 {
792 switch (device) {
793 #ifdef CONFIG_SYS_PCIE1_NAME
794 case PCIE1:
795 return CONFIG_SYS_PCIE1_NAME;
796 #endif
797 #ifdef CONFIG_SYS_PCIE2_NAME
798 case PCIE2:
799 return CONFIG_SYS_PCIE2_NAME;
800 #endif
801 #ifdef CONFIG_SYS_PCIE3_NAME
802 case PCIE3:
803 return CONFIG_SYS_PCIE3_NAME;
804 #endif
805 #ifdef CONFIG_SYS_PCIE4_NAME
806 case PCIE4:
807 return CONFIG_SYS_PCIE4_NAME;
808 #endif
809 default:
810 return NULL;
811 }
812
813 return NULL;
814 }
815
816 __attribute__((weak, alias("__board_serdes_name"))) const char *
817 board_serdes_name(enum srds_prtcl device);
818
819 static u32 devdisr_mask[] = {
820 _DEVDISR_PCIE1,
821 _DEVDISR_PCIE2,
822 _DEVDISR_PCIE3,
823 _DEVDISR_PCIE4,
824 };
825
fsl_pcie_init_ctrl(int busno,u32 devdisr,enum srds_prtcl dev,struct fsl_pci_info * pci_info)826 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
827 struct fsl_pci_info *pci_info)
828 {
829 struct pci_controller *hose;
830 int num = dev - PCIE1;
831
832 hose = calloc(1, sizeof(struct pci_controller));
833 if (!hose)
834 return busno;
835
836 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
837 busno = fsl_configure_pcie(pci_info, hose,
838 board_serdes_name(dev), busno);
839 } else {
840 printf("PCIe%d: disabled\n", num + 1);
841 }
842
843 return busno;
844 }
845
fsl_pcie_init_board(int busno)846 int fsl_pcie_init_board(int busno)
847 {
848 struct fsl_pci_info pci_info;
849 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
850 u32 devdisr;
851 u32 *addr;
852
853 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
854 addr = &gur->devdisr3;
855 #else
856 addr = &gur->devdisr;
857 #endif
858 devdisr = in_be32(addr);
859
860 #ifdef CONFIG_PCIE1
861 SET_STD_PCIE_INFO(pci_info, 1);
862 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
863 #else
864 setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
865 #endif
866
867 #ifdef CONFIG_PCIE2
868 SET_STD_PCIE_INFO(pci_info, 2);
869 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
870 #else
871 setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
872 #endif
873
874 #ifdef CONFIG_PCIE3
875 SET_STD_PCIE_INFO(pci_info, 3);
876 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
877 #else
878 setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
879 #endif
880
881 #ifdef CONFIG_PCIE4
882 SET_STD_PCIE_INFO(pci_info, 4);
883 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
884 #else
885 setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
886 #endif
887
888 return busno;
889 }
890 #else
fsl_pcie_init_ctrl(int busno,u32 devdisr,enum srds_prtcl dev,struct fsl_pci_info * pci_info)891 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
892 struct fsl_pci_info *pci_info)
893 {
894 return busno;
895 }
896
fsl_pcie_init_board(int busno)897 int fsl_pcie_init_board(int busno)
898 {
899 return busno;
900 }
901 #endif
902
903 #ifdef CONFIG_OF_BOARD_SETUP
904 #include <linux/libfdt.h>
905 #include <fdt_support.h>
906
ft_fsl_pci_setup(void * blob,const char * pci_compat,unsigned long ctrl_addr)907 void ft_fsl_pci_setup(void *blob, const char *pci_compat,
908 unsigned long ctrl_addr)
909 {
910 int off;
911 u32 bus_range[2];
912 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
913 struct pci_controller *hose;
914
915 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
916
917 /* convert ctrl_addr to true physical address */
918 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
919 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
920
921 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
922
923 if (off < 0)
924 return;
925
926 /* We assume a cfg_addr not being set means we didn't setup the controller */
927 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
928 fdt_del_node(blob, off);
929 } else {
930 bus_range[0] = 0;
931 bus_range[1] = hose->last_busno - hose->first_busno;
932 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
933 fdt_pci_dma_ranges(blob, off, hose);
934 }
935 }
936 #endif
937