1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Tests for the driver model pmic API
4 *
5 * Copyright (c) 2015 Samsung Electronics
6 * Przemyslaw Marczak <p.marczak@samsung.com>
7 */
8
9 #include <common.h>
10 #include <errno.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <fsl_pmic.h>
14 #include <malloc.h>
15 #include <dm/device-internal.h>
16 #include <dm/root.h>
17 #include <dm/test.h>
18 #include <dm/uclass-internal.h>
19 #include <dm/util.h>
20 #include <power/pmic.h>
21 #include <power/sandbox_pmic.h>
22 #include <test/test.h>
23 #include <test/ut.h>
24
25 /* Test PMIC get method */
26
power_pmic_get(struct unit_test_state * uts,char * name)27 static inline int power_pmic_get(struct unit_test_state *uts, char *name)
28 {
29 struct udevice *dev;
30
31 ut_assertok(pmic_get(name, &dev));
32 ut_assertnonnull(dev);
33
34 /* Check PMIC's name */
35 ut_asserteq_str(name, dev->name);
36
37 return 0;
38 }
39
40 /* Test PMIC get method */
dm_test_power_pmic_get(struct unit_test_state * uts)41 static int dm_test_power_pmic_get(struct unit_test_state *uts)
42 {
43 power_pmic_get(uts, "sandbox_pmic");
44
45 return 0;
46 }
47 DM_TEST(dm_test_power_pmic_get, UT_TESTF_SCAN_FDT);
48
49 /* PMIC get method - MC34708 - for 3 bytes transmission */
dm_test_power_pmic_mc34708_get(struct unit_test_state * uts)50 static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
51 {
52 power_pmic_get(uts, "pmic@41");
53
54 return 0;
55 }
56
57 DM_TEST(dm_test_power_pmic_mc34708_get, UT_TESTF_SCAN_FDT);
58
59 /* Test PMIC I/O */
dm_test_power_pmic_io(struct unit_test_state * uts)60 static int dm_test_power_pmic_io(struct unit_test_state *uts)
61 {
62 const char *name = "sandbox_pmic";
63 uint8_t out_buffer, in_buffer;
64 struct udevice *dev;
65 int reg_count, i;
66
67 ut_assertok(pmic_get(name, &dev));
68
69 reg_count = pmic_reg_count(dev);
70 ut_asserteq(reg_count, SANDBOX_PMIC_REG_COUNT);
71
72 /*
73 * Test PMIC I/O - write and read a loop counter.
74 * usually we can't write to all PMIC's registers in the real hardware,
75 * but we can to the sandbox pmic.
76 */
77 for (i = 0; i < reg_count; i++) {
78 out_buffer = i;
79 ut_assertok(pmic_write(dev, i, &out_buffer, 1));
80 ut_assertok(pmic_read(dev, i, &in_buffer, 1));
81 ut_asserteq(out_buffer, in_buffer);
82 }
83
84 return 0;
85 }
86 DM_TEST(dm_test_power_pmic_io, UT_TESTF_SCAN_FDT);
87
88 #define MC34708_PMIC_REG_COUNT 64
89 #define MC34708_PMIC_TEST_VAL 0x125534
dm_test_power_pmic_mc34708_regs_check(struct unit_test_state * uts)90 static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
91 {
92 struct udevice *dev;
93 int reg_count;
94
95 ut_assertok(pmic_get("pmic@41", &dev));
96
97 /* Check number of PMIC registers */
98 reg_count = pmic_reg_count(dev);
99 ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
100
101 return 0;
102 }
103
104 DM_TEST(dm_test_power_pmic_mc34708_regs_check, UT_TESTF_SCAN_FDT);
105
dm_test_power_pmic_mc34708_rw_val(struct unit_test_state * uts)106 static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
107 {
108 struct udevice *dev;
109 int val;
110
111 ut_assertok(pmic_get("pmic@41", &dev));
112
113 /* Check if single 3 byte read is successful */
114 val = pmic_reg_read(dev, REG_POWER_CTL2);
115 ut_asserteq(val, 0x422100);
116
117 /* Check if RW works */
118 val = 0;
119 ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
120 ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
121 val = pmic_reg_read(dev, REG_RTC_TIME);
122 ut_asserteq(val, MC34708_PMIC_TEST_VAL);
123
124 pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
125 val = pmic_reg_read(dev, REG_POWER_CTL2);
126 ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
127
128 return 0;
129 }
130
131 DM_TEST(dm_test_power_pmic_mc34708_rw_val, UT_TESTF_SCAN_FDT);
132