1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2002
4  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
5  * Marius Groeger <mgroeger@sysgo.de>
6  *
7  * (C) Copyright 2002
8  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
9  * Alex Zuepke <azu@sysgo.de>
10  */
11 
12 #include <common.h>
13 #include <cpu_func.h>
14 #include <init.h>
15 #include <irq_func.h>
16 #include <asm/arch/pxa-regs.h>
17 #include <asm/cache.h>
18 #include <asm/io.h>
19 #include <asm/system.h>
20 #include <command.h>
21 
22 /* Flush I/D-cache */
cache_flush(void)23 static void cache_flush(void)
24 {
25 	unsigned long i = 0;
26 
27 	asm ("mcr p15, 0, %0, c7, c5, 0" : : "r" (i));
28 }
29 
cleanup_before_linux(void)30 int cleanup_before_linux(void)
31 {
32 	/*
33 	 * This function is called just before we call Linux. It prepares
34 	 * the processor for Linux by just disabling everything that can
35 	 * disturb booting Linux.
36 	 */
37 
38 	disable_interrupts();
39 	icache_disable();
40 	dcache_disable();
41 	cache_flush();
42 
43 	return 0;
44 }
45 
writelrb(uint32_t val,uint32_t addr)46 inline void writelrb(uint32_t val, uint32_t addr)
47 {
48 	writel(val, addr);
49 	asm volatile("" : : : "memory");
50 	readl(addr);
51 	asm volatile("" : : : "memory");
52 }
53 
pxa2xx_dram_init(void)54 void pxa2xx_dram_init(void)
55 {
56 	uint32_t tmp;
57 	int i;
58 	/*
59 	 * 1) Initialize Asynchronous static memory controller
60 	 */
61 
62 	writelrb(CONFIG_SYS_MSC0_VAL, MSC0);
63 	writelrb(CONFIG_SYS_MSC1_VAL, MSC1);
64 	writelrb(CONFIG_SYS_MSC2_VAL, MSC2);
65 	/*
66 	 * 2) Initialize Card Interface
67 	 */
68 
69 	/* MECR: Memory Expansion Card Register */
70 	writelrb(CONFIG_SYS_MECR_VAL, MECR);
71 	/* MCMEM0: Card Interface slot 0 timing */
72 	writelrb(CONFIG_SYS_MCMEM0_VAL, MCMEM0);
73 	/* MCMEM1: Card Interface slot 1 timing */
74 	writelrb(CONFIG_SYS_MCMEM1_VAL, MCMEM1);
75 	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
76 	writelrb(CONFIG_SYS_MCATT0_VAL, MCATT0);
77 	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
78 	writelrb(CONFIG_SYS_MCATT1_VAL, MCATT1);
79 	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
80 	writelrb(CONFIG_SYS_MCIO0_VAL, MCIO0);
81 	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
82 	writelrb(CONFIG_SYS_MCIO1_VAL, MCIO1);
83 
84 	/*
85 	 * 3) Configure Fly-By DMA register
86 	 */
87 
88 	writelrb(CONFIG_SYS_FLYCNFG_VAL, FLYCNFG);
89 
90 	/*
91 	 * 4) Initialize Timing for Sync Memory (SDCLK0)
92 	 */
93 
94 	/*
95 	 * Before accessing MDREFR we need a valid DRI field, so we set
96 	 * this to power on defaults + DRI field.
97 	 */
98 
99 	/* Read current MDREFR config and zero out DRI */
100 	tmp = readl(MDREFR) & ~0xfff;
101 	/* Add user-specified DRI */
102 	tmp |= CONFIG_SYS_MDREFR_VAL & 0xfff;
103 	/* Configure important bits */
104 	tmp |= MDREFR_K0RUN | MDREFR_SLFRSH;
105 	tmp &= ~(MDREFR_APD | MDREFR_E1PIN);
106 
107 	/* Write MDREFR back */
108 	writelrb(tmp, MDREFR);
109 
110 	/*
111 	 * 5) Initialize Synchronous Static Memory (Flash/Peripherals)
112 	 */
113 
114 	/* Initialize SXCNFG register. Assert the enable bits.
115 	 *
116 	 * Write SXMRS to cause an MRS command to all enabled banks of
117 	 * synchronous static memory. Note that SXLCR need not be written
118 	 * at this time.
119 	 */
120 	writelrb(CONFIG_SYS_SXCNFG_VAL, SXCNFG);
121 
122 	/*
123 	 * 6) Initialize SDRAM
124 	 */
125 
126 	writelrb(CONFIG_SYS_MDREFR_VAL & ~MDREFR_SLFRSH, MDREFR);
127 	writelrb(CONFIG_SYS_MDREFR_VAL | MDREFR_E1PIN, MDREFR);
128 
129 	/*
130 	 * 7) Write MDCNFG with MDCNFG:DEx deasserted (set to 0), to configure
131 	 *    but not enable each SDRAM partition pair.
132 	 */
133 
134 	writelrb(CONFIG_SYS_MDCNFG_VAL &
135 		~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
136 
137 	/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
138 	writel(0, OSCR);
139 	while (readl(OSCR) < 0x300)
140 		asm volatile("" : : : "memory");
141 
142 	/*
143 	 * 8) Trigger a number (usually 8) refresh cycles by attempting
144 	 *    non-burst read or write accesses to disabled SDRAM, as commonly
145 	 *    specified in the power up sequence documented in SDRAM data
146 	 *    sheets. The address(es) used for this purpose must not be
147 	 *    cacheable.
148 	 */
149 	for (i = 9; i >= 0; i--) {
150 		writel(i, 0xa0000000);
151 		asm volatile("" : : : "memory");
152 	}
153 	/*
154 	 * 9) Write MDCNFG with enable bits asserted (MDCNFG:DEx set to 1).
155 	 */
156 
157 	tmp = CONFIG_SYS_MDCNFG_VAL &
158 		(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3);
159 	tmp |= readl(MDCNFG);
160 	writelrb(tmp, MDCNFG);
161 
162 	/*
163 	 * 10) Write MDMRS.
164 	 */
165 
166 	writelrb(CONFIG_SYS_MDMRS_VAL, MDMRS);
167 
168 	/*
169 	 * 11) Enable APD
170 	 */
171 
172 	if (CONFIG_SYS_MDREFR_VAL & MDREFR_APD) {
173 		tmp = readl(MDREFR);
174 		tmp |= MDREFR_APD;
175 		writelrb(tmp, MDREFR);
176 	}
177 }
178 
pxa_gpio_setup(void)179 void pxa_gpio_setup(void)
180 {
181 	writel(CONFIG_SYS_GPSR0_VAL, GPSR0);
182 	writel(CONFIG_SYS_GPSR1_VAL, GPSR1);
183 	writel(CONFIG_SYS_GPSR2_VAL, GPSR2);
184 #if defined(CONFIG_CPU_PXA27X)
185 	writel(CONFIG_SYS_GPSR3_VAL, GPSR3);
186 #endif
187 
188 	writel(CONFIG_SYS_GPCR0_VAL, GPCR0);
189 	writel(CONFIG_SYS_GPCR1_VAL, GPCR1);
190 	writel(CONFIG_SYS_GPCR2_VAL, GPCR2);
191 #if defined(CONFIG_CPU_PXA27X)
192 	writel(CONFIG_SYS_GPCR3_VAL, GPCR3);
193 #endif
194 
195 	writel(CONFIG_SYS_GPDR0_VAL, GPDR0);
196 	writel(CONFIG_SYS_GPDR1_VAL, GPDR1);
197 	writel(CONFIG_SYS_GPDR2_VAL, GPDR2);
198 #if defined(CONFIG_CPU_PXA27X)
199 	writel(CONFIG_SYS_GPDR3_VAL, GPDR3);
200 #endif
201 
202 	writel(CONFIG_SYS_GAFR0_L_VAL, GAFR0_L);
203 	writel(CONFIG_SYS_GAFR0_U_VAL, GAFR0_U);
204 	writel(CONFIG_SYS_GAFR1_L_VAL, GAFR1_L);
205 	writel(CONFIG_SYS_GAFR1_U_VAL, GAFR1_U);
206 	writel(CONFIG_SYS_GAFR2_L_VAL, GAFR2_L);
207 	writel(CONFIG_SYS_GAFR2_U_VAL, GAFR2_U);
208 #if defined(CONFIG_CPU_PXA27X)
209 	writel(CONFIG_SYS_GAFR3_L_VAL, GAFR3_L);
210 	writel(CONFIG_SYS_GAFR3_U_VAL, GAFR3_U);
211 #endif
212 
213 	writel(CONFIG_SYS_PSSR_VAL, PSSR);
214 }
215 
pxa_interrupt_setup(void)216 void pxa_interrupt_setup(void)
217 {
218 	writel(0, ICLR);
219 	writel(0, ICMR);
220 #if defined(CONFIG_CPU_PXA27X)
221 	writel(0, ICLR2);
222 	writel(0, ICMR2);
223 #endif
224 }
225 
pxa_clock_setup(void)226 void pxa_clock_setup(void)
227 {
228 	writel(CONFIG_SYS_CKEN, CKEN);
229 	writel(CONFIG_SYS_CCCR, CCCR);
230 	asm volatile("mcr	p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
231 
232 	/* enable the 32Khz oscillator for RTC and PowerManager */
233 	writel(OSCC_OON, OSCC);
234 	while (!(readl(OSCC) & OSCC_OOK))
235 		asm volatile("" : : : "memory");
236 }
237 
pxa_wakeup(void)238 void pxa_wakeup(void)
239 {
240 	uint32_t rcsr;
241 
242 	rcsr = readl(RCSR);
243 	writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR);
244 
245 	/* Wakeup */
246 	if (rcsr & RCSR_SMR) {
247 		writel(PSSR_PH, PSSR);
248 		pxa2xx_dram_init();
249 		icache_disable();
250 		dcache_disable();
251 		asm volatile("mov	pc, %0" : : "r"(readl(PSPR)));
252 	}
253 }
254 
arch_cpu_init(void)255 int arch_cpu_init(void)
256 {
257 	pxa_gpio_setup();
258 	pxa_wakeup();
259 	pxa_interrupt_setup();
260 	pxa_clock_setup();
261 	return 0;
262 }
263 
i2c_clk_enable(void)264 void i2c_clk_enable(void)
265 {
266 	/* Set the global I2C clock on */
267 	writel(readl(CKEN) | CKEN14_I2C, CKEN);
268 }
269 
270 void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
271 
reset_cpu(void)272 void reset_cpu(void)
273 {
274 	uint32_t tmp;
275 
276 	setbits_le32(OWER, OWER_WME);
277 
278 	tmp = readl(OSCR);
279 	tmp += 0x1000;
280 	writel(tmp, OSMR3);
281 	writel(MDREFR_SLFRSH, MDREFR);
282 
283 	for (;;)
284 		;
285 }
286 
enable_caches(void)287 void enable_caches(void)
288 {
289 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
290 	icache_enable();
291 #endif
292 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
293 	dcache_enable();
294 #endif
295 }
296