1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Board functions for Bosch Guardian
6 *
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * Copyright (C) 2018 Robert Bosch Power Tools GmbH
9 */
10
11 #include <common.h>
12 #include <cpsw.h>
13 #include <dm.h>
14 #include <env.h>
15 #include <env_internal.h>
16 #include <errno.h>
17 #include <i2c.h>
18 #include <init.h>
19 #include <led.h>
20 #include <miiphy.h>
21 #include <panel.h>
22 #include <asm/global_data.h>
23 #include <power/tps65217.h>
24 #include <power/tps65910.h>
25 #include <spl.h>
26 #include <watchdog.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/ddr_defs.h>
30 #include <asm/arch/gpio.h>
31 #include <asm/arch/hardware.h>
32 #include <asm/arch/mem.h>
33 #include <asm/arch/mmc_host_def.h>
34 #include <asm/arch/omap.h>
35 #include <asm/arch/sys_proto.h>
36 #include <asm/emif.h>
37 #include <asm/gpio.h>
38 #include <asm/io.h>
39 #include "board.h"
40
41 DECLARE_GLOBAL_DATA_PTR;
42
43 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
44 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
45
46 static const struct ddr_data ddr3_data = {
47 .datardsratio0 = MT41K128M16JT125K_RD_DQS,
48 .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
49 .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
50 .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
51 };
52
53 static const struct cmd_control ddr3_cmd_ctrl_data = {
54 .cmd0csratio = MT41K128M16JT125K_RATIO,
55 .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
56
57 .cmd1csratio = MT41K128M16JT125K_RATIO,
58 .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
59
60 .cmd2csratio = MT41K128M16JT125K_RATIO,
61 .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
62 };
63
64 static struct emif_regs ddr3_emif_reg_data = {
65 .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
66 .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
67 .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
68 .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
69 .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
70 .zq_config = MT41K128M16JT125K_ZQ_CFG,
71 .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
72 };
73
74 #define OSC (V_OSCK / 1000000)
75 const struct dpll_params dpll_ddr = {
76 400, OSC - 1, 1, -1, -1, -1, -1};
77
am33xx_spl_board_init(void)78 void am33xx_spl_board_init(void)
79 {
80 int mpu_vdd;
81 int usb_cur_lim;
82
83 /* Get the frequency */
84 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
85
86 if (i2c_probe(TPS65217_CHIP_PM))
87 return;
88
89 /*
90 * Increase USB current limit to 1300mA or 1800mA and set
91 * the MPU voltage controller as needed.
92 */
93 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
94 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
95 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
96 } else {
97 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
98 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
99 }
100
101 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
102 TPS65217_POWER_PATH,
103 usb_cur_lim,
104 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
105 puts("tps65217_reg_write failure\n");
106
107 /* Set DCDC3 (CORE) voltage to 1.125V */
108 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
109 TPS65217_DCDC_VOLT_SEL_1125MV)) {
110 puts("tps65217_voltage_update failure\n");
111 return;
112 }
113
114 /* Set CORE Frequencies to OPP100 */
115 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
116
117 /* Set DCDC2 (MPU) voltage */
118 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
119 puts("tps65217_voltage_update failure\n");
120 return;
121 }
122
123 /*
124 * Set LDO3 to 1.8V and LDO4 to 3.3V
125 */
126 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
127 TPS65217_DEFLS1,
128 TPS65217_LDO_VOLTAGE_OUT_1_8,
129 TPS65217_LDO_MASK))
130 puts("tps65217_reg_write failure\n");
131
132 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
133 TPS65217_DEFLS2,
134 TPS65217_LDO_VOLTAGE_OUT_3_3,
135 TPS65217_LDO_MASK))
136 puts("tps65217_reg_write failure\n");
137
138 /* Set MPU Frequency to what we detected now that voltages are set */
139 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
140 }
141
get_dpll_ddr_params(void)142 const struct dpll_params *get_dpll_ddr_params(void)
143 {
144 enable_i2c0_pin_mux();
145 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
146
147 return &dpll_ddr;
148 }
149
set_uart_mux_conf(void)150 void set_uart_mux_conf(void)
151 {
152 enable_uart0_pin_mux();
153 }
154
set_mux_conf_regs(void)155 void set_mux_conf_regs(void)
156 {
157 enable_board_pin_mux();
158 }
159
160 const struct ctrl_ioregs ioregs = {
161 .cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
162 .cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
163 .cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
164 .dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
165 .dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
166 };
167
sdram_init(void)168 void sdram_init(void)
169 {
170 config_ddr(400, &ioregs,
171 &ddr3_data,
172 &ddr3_cmd_ctrl_data,
173 &ddr3_emif_reg_data, 0);
174 }
175 #endif
176
board_init(void)177 int board_init(void)
178 {
179 save_omap_boot_params();
180
181 #if defined(CONFIG_HW_WATCHDOG)
182 hw_watchdog_init();
183 #endif
184
185 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
186
187 #ifdef CONFIG_MTD_RAW_NAND
188 gpmc_init();
189 #endif
190 return 0;
191 }
192
193 #ifdef CONFIG_BOARD_LATE_INIT
set_bootmode_env(void)194 static void set_bootmode_env(void)
195 {
196 char *boot_device_name = NULL;
197 char *boot_mode_gpio = "gpio@44e07000_14";
198 int ret;
199 int value;
200
201 struct gpio_desc boot_mode_desc;
202
203 switch (gd->arch.omap_boot_device) {
204 case BOOT_DEVICE_NAND:
205 boot_device_name = "nand";
206 break;
207 case BOOT_DEVICE_USBETH:
208 boot_device_name = "usbeth";
209 break;
210 default:
211 break;
212 }
213
214 if (boot_device_name)
215 env_set("boot_device", boot_device_name);
216
217 ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
218 if (ret) {
219 printf("%s is not found\n", boot_mode_gpio);
220 goto err;
221 }
222
223 ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
224 if (ret && ret != -EBUSY) {
225 printf("requesting gpio: %s failed\n", boot_mode_gpio);
226 goto err;
227 }
228
229 value = dm_gpio_get_value(&boot_mode_desc);
230 value ? env_set("swi_status", "0") : env_set("swi_status", "1");
231 return;
232
233 err:
234 env_set("swi_status", "err");
235 }
236
board_late_init(void)237 int board_late_init(void)
238 {
239 #ifdef CONFIG_LED_GPIO
240 led_default_state();
241 #endif
242 set_bootmode_env();
243 return 0;
244 }
245 #endif /* CONFIG_BOARD_LATE_INIT */
246