1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018-2020 NXP
4 *
5 */
6
7 #include <common.h>
8 #include <env.h>
9 #include <fdt_support.h>
10 #include <hwconfig.h>
11 #include <command.h>
12 #include <log.h>
13 #include <net.h>
14 #include <netdev.h>
15 #include <malloc.h>
16 #include <fsl_mdio.h>
17 #include <miiphy.h>
18 #include <phy.h>
19 #include <fm_eth.h>
20 #include <asm/global_data.h>
21 #include <asm/io.h>
22 #include <exports.h>
23 #include <asm/arch/fsl_serdes.h>
24 #include <fsl-mc/fsl_mc.h>
25 #include <fsl-mc/ldpaa_wriop.h>
26 #include <linux/libfdt.h>
27
28 #include "../common/qixis.h"
29
30 DECLARE_GLOBAL_DATA_PTR;
31
32 #ifndef CONFIG_DM_ETH
33 #define EMI_NONE 0
34 #define EMI1 1 /* Mdio Bus 1 */
35 #define EMI2 2 /* Mdio Bus 2 */
36
37 #if defined(CONFIG_FSL_MC_ENET)
38 enum io_slot {
39 IO_SLOT_NONE = 0,
40 IO_SLOT_1,
41 IO_SLOT_2,
42 IO_SLOT_3,
43 IO_SLOT_4,
44 IO_SLOT_5,
45 IO_SLOT_6,
46 IO_SLOT_7,
47 IO_SLOT_8,
48 EMI1_RGMII1,
49 EMI1_RGMII2,
50 IO_SLOT_MAX
51 };
52
53 struct lx2160a_qds_mdio {
54 enum io_slot ioslot : 4;
55 u8 realbusnum : 4;
56 struct mii_dev *realbus;
57 };
58
59 /* structure explaining the phy configuration on 8 lanes of a serdes*/
60 struct serdes_phy_config {
61 u8 serdes; /* serdes protocol */
62 struct phy_config {
63 u8 dpmacid;
64 /* -1 terminated array */
65 int phy_address[WRIOP_MAX_PHY_NUM + 1];
66 u8 mdio_bus;
67 enum io_slot ioslot;
68 } phy_config[SRDS_MAX_LANES];
69 };
70
71 /* Table defining the phy configuration on 8 lanes of a serdes.
72 * Various assumptions have been made while defining this table.
73 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
74 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
75 * And also that this card is connected to IO Slot 1 (could have been connected
76 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
77 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
78 * used in serdes1 protocol 19 (could have selected MDIO 2)
79 * To override these settings "dpmac" environment variable can be used after
80 * defining "dpmac_override" in hwconfig environment variable.
81 * This table has limited serdes protocol entries. It can be expanded as per
82 * requirement.
83 */
84 static const struct serdes_phy_config serdes1_phy_config[] = {
85 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
86 EMI1, IO_SLOT_1},
87 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
88 EMI1, IO_SLOT_1},
89 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
90 EMI1, IO_SLOT_1},
91 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
92 EMI1, IO_SLOT_1} } },
93 {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
94 EMI1, IO_SLOT_1},
95 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
96 EMI1, IO_SLOT_1},
97 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
98 EMI1, IO_SLOT_1},
99 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
100 EMI1, IO_SLOT_1},
101 {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
102 EMI1, IO_SLOT_2},
103 {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
104 EMI1, IO_SLOT_2},
105 {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
106 EMI1, IO_SLOT_2},
107 {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
108 EMI1, IO_SLOT_2} } },
109 {8, {} },
110 {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
111 EMI1, IO_SLOT_1},
112 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
113 EMI1, IO_SLOT_2} } },
114 {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
115 EMI1, IO_SLOT_1} } },
116 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
117 EMI1, IO_SLOT_1},
118 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
119 EMI1, IO_SLOT_1} } },
120 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
121 EMI1, IO_SLOT_1},
122 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
123 EMI1, IO_SLOT_1},
124 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
125 EMI1, IO_SLOT_1},
126 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
127 EMI1, IO_SLOT_1} } },
128 {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
129 EMI1, IO_SLOT_2},
130 {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
131 EMI1, IO_SLOT_1},
132 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
133 EMI1, IO_SLOT_1},
134 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
135 EMI1, IO_SLOT_6},
136 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
137 EMI1, IO_SLOT_6} } },
138 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
139 EMI1, IO_SLOT_1},
140 {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
141 EMI1, IO_SLOT_2} } }
142 };
143
144 static const struct serdes_phy_config serdes2_phy_config[] = {
145 {2, {} },
146 {3, {} },
147 {5, {} },
148 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
149 EMI1, IO_SLOT_7},
150 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
151 EMI1, IO_SLOT_7},
152 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
153 EMI1, IO_SLOT_7},
154 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
155 EMI1, IO_SLOT_8},
156 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
157 EMI1, IO_SLOT_8},
158 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
159 EMI1, IO_SLOT_8} } },
160 };
161
162 static const struct serdes_phy_config serdes3_phy_config[] = {
163 {2, {} },
164 {3, {} }
165 };
166
167 static inline
get_phy_config(u8 serdes,const struct serdes_phy_config * table,u8 table_size)168 const struct phy_config *get_phy_config(u8 serdes,
169 const struct serdes_phy_config *table,
170 u8 table_size)
171 {
172 int i;
173
174 for (i = 0; i < table_size; i++) {
175 if (table[i].serdes == serdes)
176 return table[i].phy_config;
177 }
178
179 return NULL;
180 }
181
182 /* BRDCFG4 controls EMI routing for the board.
183 * Bits Function
184 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
185 * EMI1 00= On-board PHY #1
186 * 01= On-board PHY #2
187 * 10= (reserved)
188 * 11= Slots 1..8 multiplexer and translator.
189 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
190 * EMI1X 000= Slot #1
191 * 001= Slot #2
192 * 010= Slot #3
193 * 011= Slot #4
194 * 100= Slot #5
195 * 101= Slot #6
196 * 110= Slot #7
197 * 111= Slot #8
198 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
199 * EMI2 000= Slot #1 (secondary EMI)
200 * 001= Slot #2 (secondary EMI)
201 * 010= Slot #3 (secondary EMI)
202 * 011= Slot #4 (secondary EMI)
203 * 100= Slot #5 (secondary EMI)
204 * 101= Slot #6 (secondary EMI)
205 * 110= Slot #7 (secondary EMI)
206 * 111= Slot #8 (secondary EMI)
207 */
lx2160a_qds_get_mdio_mux_val(u8 realbusnum,enum io_slot ioslot)208 static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
209 {
210 switch (realbusnum) {
211 case EMI1:
212 switch (ioslot) {
213 case EMI1_RGMII1:
214 return 0;
215 case EMI1_RGMII2:
216 return 0x40;
217 default:
218 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
219 }
220 break;
221 case EMI2:
222 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
223 default:
224 return -1;
225 }
226 }
227
lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio * priv)228 static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
229 {
230 u8 brdcfg4, mux_val, reg;
231
232 brdcfg4 = QIXIS_READ(brdcfg[4]);
233 reg = brdcfg4;
234 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
235
236 switch (priv->realbusnum) {
237 case EMI1:
238 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
239 brdcfg4 |= mux_val;
240 break;
241 case EMI2:
242 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
243 brdcfg4 |= mux_val;
244 break;
245 }
246
247 if (brdcfg4 ^ reg)
248 QIXIS_WRITE(brdcfg[4], brdcfg4);
249 }
250
lx2160a_qds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)251 static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
252 int devad, int regnum)
253 {
254 struct lx2160a_qds_mdio *priv = bus->priv;
255
256 lx2160a_qds_mux_mdio(priv);
257
258 return priv->realbus->read(priv->realbus, addr, devad, regnum);
259 }
260
lx2160a_qds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)261 static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
262 int regnum, u16 value)
263 {
264 struct lx2160a_qds_mdio *priv = bus->priv;
265
266 lx2160a_qds_mux_mdio(priv);
267
268 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
269 }
270
lx2160a_qds_mdio_reset(struct mii_dev * bus)271 static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
272 {
273 struct lx2160a_qds_mdio *priv = bus->priv;
274
275 return priv->realbus->reset(priv->realbus);
276 }
277
lx2160a_qds_mdio_init(u8 realbusnum,enum io_slot ioslot)278 static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
279 {
280 struct lx2160a_qds_mdio *pmdio;
281 struct mii_dev *bus;
282 /*should be within MDIO_NAME_LEN*/
283 char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
284
285 if (realbusnum == EMI2) {
286 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
287 printf("invalid ioslot %d\n", ioslot);
288 return NULL;
289 }
290 } else if (realbusnum == EMI1) {
291 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
292 printf("invalid ioslot %d\n", ioslot);
293 return NULL;
294 }
295 } else {
296 printf("not supported real mdio bus %d\n", realbusnum);
297 return NULL;
298 }
299
300 if (ioslot == EMI1_RGMII1)
301 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
302 else if (ioslot == EMI1_RGMII2)
303 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
304 else
305 sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
306 realbusnum, ioslot);
307 bus = miiphy_get_dev_by_name(dummy_mdio_name);
308
309 if (bus)
310 return bus;
311
312 bus = mdio_alloc();
313 if (!bus) {
314 printf("Failed to allocate %s bus\n", dummy_mdio_name);
315 return NULL;
316 }
317
318 pmdio = malloc(sizeof(*pmdio));
319 if (!pmdio) {
320 printf("Failed to allocate %s private data\n", dummy_mdio_name);
321 free(bus);
322 return NULL;
323 }
324
325 switch (realbusnum) {
326 case EMI1:
327 pmdio->realbus =
328 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
329 break;
330 case EMI2:
331 pmdio->realbus =
332 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
333 break;
334 }
335
336 if (!pmdio->realbus) {
337 printf("No real mdio bus num %d found\n", realbusnum);
338 free(bus);
339 free(pmdio);
340 return NULL;
341 }
342
343 pmdio->realbusnum = realbusnum;
344 pmdio->ioslot = ioslot;
345 bus->read = lx2160a_qds_mdio_read;
346 bus->write = lx2160a_qds_mdio_write;
347 bus->reset = lx2160a_qds_mdio_reset;
348 strcpy(bus->name, dummy_mdio_name);
349 bus->priv = pmdio;
350
351 if (!mdio_register(bus))
352 return bus;
353
354 printf("No bus with name %s\n", dummy_mdio_name);
355 free(bus);
356 free(pmdio);
357 return NULL;
358 }
359
do_phy_config(const struct phy_config * phy_config)360 static inline void do_phy_config(const struct phy_config *phy_config)
361 {
362 struct mii_dev *bus;
363 int i, phy_num, phy_address;
364
365 for (i = 0; i < SRDS_MAX_LANES; i++) {
366 if (!phy_config[i].dpmacid)
367 continue;
368
369 for (phy_num = 0;
370 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
371 phy_num++) {
372 phy_address = phy_config[i].phy_address[phy_num];
373 if (phy_address == -1)
374 break;
375 wriop_set_phy_address(phy_config[i].dpmacid,
376 phy_num, phy_address);
377 }
378 /*Register the muxing front-ends to the MDIO buses*/
379 bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
380 phy_config[i].ioslot);
381 if (!bus)
382 printf("could not get bus for mdio %d ioslot %d\n",
383 phy_config[i].mdio_bus,
384 phy_config[i].ioslot);
385 else
386 wriop_set_mdio(phy_config[i].dpmacid, bus);
387 }
388 }
389
do_dpmac_config(int dpmac,const char * arg_dpmacid,char * env_dpmac)390 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
391 char *env_dpmac)
392 {
393 const char *ret;
394 size_t len;
395 u8 realbusnum, ioslot;
396 struct mii_dev *bus;
397 int phy_num;
398 char *phystr = "phy00";
399
400 /*search phy in dpmac arg*/
401 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
402 sprintf(phystr, "phy%d", phy_num + 1);
403 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
404 if (!ret) {
405 /*look for phy instead of phy1*/
406 if (!phy_num)
407 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
408 &len, env_dpmac);
409 if (!ret)
410 continue;
411 }
412
413 if (len != 4 || strncmp(ret, "0x", 2))
414 printf("invalid phy format in %s variable.\n"
415 "specify phy%d for %s in hex format e.g. 0x12\n",
416 env_dpmac, phy_num + 1, arg_dpmacid);
417 else
418 wriop_set_phy_address(dpmac, phy_num,
419 simple_strtoul(ret, NULL, 16));
420 }
421
422 /*search mdio in dpmac arg*/
423 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
424 if (ret)
425 realbusnum = *ret - '0';
426 else
427 realbusnum = EMI_NONE;
428
429 if (realbusnum) {
430 /*search io in dpmac arg*/
431 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
432 if (ret)
433 ioslot = *ret - '0';
434 else
435 ioslot = IO_SLOT_NONE;
436 /*Register the muxing front-ends to the MDIO buses*/
437 bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
438 if (!bus)
439 printf("could not get bus for mdio %d ioslot %d\n",
440 realbusnum, ioslot);
441 else
442 wriop_set_mdio(dpmac, bus);
443 }
444 }
445
446 #endif
447 #endif /* !CONFIG_DM_ETH */
448
board_eth_init(struct bd_info * bis)449 int board_eth_init(struct bd_info *bis)
450 {
451 #ifndef CONFIG_DM_ETH
452 #if defined(CONFIG_FSL_MC_ENET)
453 struct memac_mdio_info mdio_info;
454 struct memac_mdio_controller *regs;
455 int i;
456 const char *ret;
457 char *env_dpmac;
458 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
459 size_t len;
460 struct mii_dev *bus;
461 const struct phy_config *phy_config;
462 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
463 u32 srds_s1, srds_s2, srds_s3;
464
465 srds_s1 = in_le32(&gur->rcwsr[28]) &
466 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
467 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
468
469 srds_s2 = in_le32(&gur->rcwsr[28]) &
470 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
471 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
472
473 srds_s3 = in_le32(&gur->rcwsr[28]) &
474 FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
475 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
476
477 sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
478
479 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
480 mdio_info.regs = regs;
481 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
482
483 /*Register the EMI 1*/
484 fm_memac_mdio_init(bis, &mdio_info);
485
486 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
487 mdio_info.regs = regs;
488 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
489
490 /*Register the EMI 2*/
491 fm_memac_mdio_init(bis, &mdio_info);
492
493 /* "dpmac" environment variable can be used after
494 * defining "dpmac_override" in hwconfig environment variable.
495 */
496 if (hwconfig("dpmac_override")) {
497 env_dpmac = env_get("dpmac");
498 if (env_dpmac) {
499 ret = hwconfig_arg_f("srds", &len, env_dpmac);
500 if (ret) {
501 if (strncmp(ret, srds, strlen(srds))) {
502 printf("SERDES configuration changed.\n"
503 "previous: %.*s, current: %s.\n"
504 "update dpmac variable.\n",
505 (int)len, ret, srds);
506 }
507 } else {
508 printf("SERDES configuration not found.\n"
509 "Please add srds:%s in dpmac variable\n",
510 srds);
511 }
512
513 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
514 /* Look for dpmac1 to dpmac24(current max) arg
515 * in dpmac environment variable
516 */
517 sprintf(dpmacid, "dpmac%d", i);
518 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
519 if (ret)
520 do_dpmac_config(i, dpmacid, env_dpmac);
521 }
522 } else {
523 printf("Warning: environment dpmac not found.\n"
524 "DPAA network interfaces may not work\n");
525 }
526 } else {
527 /*Look for phy config for serdes1 in phy config table*/
528 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
529 ARRAY_SIZE(serdes1_phy_config));
530 if (!phy_config) {
531 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
532 __func__, srds_s1);
533 } else {
534 do_phy_config(phy_config);
535 }
536 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
537 ARRAY_SIZE(serdes2_phy_config));
538 if (!phy_config) {
539 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
540 __func__, srds_s2);
541 } else {
542 do_phy_config(phy_config);
543 }
544 phy_config = get_phy_config(srds_s3, serdes3_phy_config,
545 ARRAY_SIZE(serdes3_phy_config));
546 if (!phy_config) {
547 printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
548 __func__, srds_s3);
549 } else {
550 do_phy_config(phy_config);
551 }
552 }
553
554 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
555 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
556 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
557 if (!bus)
558 printf("could not get bus for RGMII1\n");
559 else
560 wriop_set_mdio(WRIOP1_DPMAC17, bus);
561 }
562
563 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
564 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
565 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
566 if (!bus)
567 printf("could not get bus for RGMII2\n");
568 else
569 wriop_set_mdio(WRIOP1_DPMAC18, bus);
570 }
571
572 cpu_eth_init(bis);
573 #endif /* CONFIG_FMAN_ENET */
574 #endif /* !CONFIG_DM_ETH */
575
576 #ifdef CONFIG_PHY_AQUANTIA
577 /*
578 * Export functions to be used by AQ firmware
579 * upload application
580 */
581 gd->jt->strcpy = strcpy;
582 gd->jt->mdelay = mdelay;
583 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
584 gd->jt->phy_find_by_mask = phy_find_by_mask;
585 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
586 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
587 #endif
588
589 #ifdef CONFIG_DM_ETH
590 return 0;
591 #else
592 return pci_eth_init(bis);
593 #endif
594 }
595
596 #if defined(CONFIG_RESET_PHY_R)
reset_phy(void)597 void reset_phy(void)
598 {
599 #if defined(CONFIG_FSL_MC_ENET)
600 mc_env_boot();
601 #endif
602 }
603 #endif /* CONFIG_RESET_PHY_R */
604
605 #ifndef CONFIG_DM_ETH
606 #if defined(CONFIG_FSL_MC_ENET)
fdt_fixup_dpmac_phy_handle(void * fdt,int dpmac_id,int node_phandle)607 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
608 {
609 int offset;
610 int ret;
611 char dpmac_str[] = "dpmacs@00";
612 const char *phy_string;
613
614 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
615
616 if (offset < 0)
617 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
618
619 if (offset < 0) {
620 printf("dpmacs node not found in device tree\n");
621 return offset;
622 }
623
624 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
625 debug("dpmac_str = %s\n", dpmac_str);
626
627 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
628 if (offset < 0) {
629 printf("%s node not found in device tree\n", dpmac_str);
630 return offset;
631 }
632
633 phy_string = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
634 if (is_backplane_mode(phy_string)) {
635 /* Backplane KR mode: skip fixups */
636 printf("Interface %d in backplane KR mode\n", dpmac_id);
637 return 0;
638 }
639
640 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
641 if (ret)
642 printf("%d@%s %d\n", __LINE__, __func__, ret);
643
644 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
645 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
646 phy_string);
647 if (ret)
648 printf("%d@%s %d\n", __LINE__, __func__, ret);
649
650 return ret;
651 }
652
fdt_get_ioslot_offset(void * fdt,struct mii_dev * mii_dev,int fpga_offset)653 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
654 {
655 char mdio_ioslot_str[] = "mdio@00";
656 struct lx2160a_qds_mdio *priv;
657 u64 reg;
658 u32 phandle;
659 int offset, mux_val;
660
661 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
662 if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
663 strlen("LX2160A_QDS_MDIO")))
664 return -1;
665
666 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
667 priv = mii_dev->priv;
668
669 debug("real_bus_num = %d, ioslot = %d\n",
670 priv->realbusnum, priv->ioslot);
671
672 if (priv->realbusnum == EMI1)
673 reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
674 else
675 reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
676
677 offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
678 if (offset < 0) {
679 printf("mdio@%llx node not found in device tree\n", reg);
680 return offset;
681 }
682
683 phandle = fdt_get_phandle(fdt, offset);
684 phandle = cpu_to_fdt32(phandle);
685 offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
686 &phandle, 4);
687 if (offset < 0) {
688 printf("mdio-mux-%d node not found in device tree\n",
689 priv->realbusnum == EMI1 ? 1 : 2);
690 return offset;
691 }
692
693 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
694 if (priv->realbusnum == EMI1)
695 mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
696 else
697 mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
698 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
699
700 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
701 if (offset < 0) {
702 printf("%s node not found in device tree\n", mdio_ioslot_str);
703 return offset;
704 }
705
706 return offset;
707 }
708
fdt_create_phy_node(void * fdt,int offset,u8 phyaddr,int * subnodeoffset,struct phy_device * phy_dev,int phandle)709 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
710 struct phy_device *phy_dev, int phandle)
711 {
712 char phy_node_name[] = "ethernet-phy@00";
713 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
714 int ret;
715
716 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
717 debug("phy_node_name = %s\n", phy_node_name);
718
719 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
720 if (*subnodeoffset <= 0) {
721 printf("Could not add subnode %s inside node %s err = %s\n",
722 phy_node_name, fdt_get_name(fdt, offset, NULL),
723 fdt_strerror(*subnodeoffset));
724 return *subnodeoffset;
725 }
726
727 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
728 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
729 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
730
731 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
732 phy_id_compatible_str);
733 if (ret) {
734 printf("%d@%s %d\n", __LINE__, __func__, ret);
735 goto out;
736 }
737
738 if (phy_dev->is_c45) {
739 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
740 "ethernet-phy-ieee802.3-c45");
741 if (ret) {
742 printf("%d@%s %d\n", __LINE__, __func__, ret);
743 goto out;
744 }
745 } else {
746 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
747 "ethernet-phy-ieee802.3-c22");
748 if (ret) {
749 printf("%d@%s %d\n", __LINE__, __func__, ret);
750 goto out;
751 }
752 }
753
754 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
755 if (ret) {
756 printf("%d@%s %d\n", __LINE__, __func__, ret);
757 goto out;
758 }
759
760 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
761 if (ret) {
762 printf("%d@%s %d\n", __LINE__, __func__, ret);
763 goto out;
764 }
765
766 out:
767 if (ret)
768 fdt_del_node(fdt, *subnodeoffset);
769
770 return ret;
771 }
772
fdt_fixup_board_phy(void * fdt)773 int fdt_fixup_board_phy(void *fdt)
774 {
775 int fpga_offset, offset, subnodeoffset;
776 struct mii_dev *mii_dev;
777 struct list_head *mii_devs, *entry;
778 int ret, dpmac_id, phandle, i;
779 struct phy_device *phy_dev;
780 char ethname[ETH_NAME_LEN];
781 phy_interface_t phy_iface;
782
783 ret = 0;
784 /* we know FPGA is connected to i2c0, therefore search path directly,
785 * instead of compatible property, as it saves time
786 */
787 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
788
789 if (fpga_offset < 0)
790 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
791
792 if (fpga_offset < 0) {
793 printf("i2c@2000000/fpga node not found in device tree\n");
794 return fpga_offset;
795 }
796
797 phandle = fdt_alloc_phandle(fdt);
798 mii_devs = mdio_get_list_head();
799
800 list_for_each(entry, mii_devs) {
801 mii_dev = list_entry(entry, struct mii_dev, link);
802 debug("mii_dev name : %s\n", mii_dev->name);
803 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
804 if (offset < 0)
805 continue;
806
807 // Look for phy devices attached to MDIO bus muxing front end
808 // and create their entries with compatible being the device id
809 for (i = 0; i < PHY_MAX_ADDR; i++) {
810 phy_dev = mii_dev->phymap[i];
811 if (!phy_dev)
812 continue;
813
814 // TODO: use sscanf instead of loop
815 dpmac_id = WRIOP1_DPMAC1;
816 while (dpmac_id < NUM_WRIOP_PORTS) {
817 phy_iface = wriop_get_enet_if(dpmac_id);
818 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
819 dpmac_id,
820 phy_string_for_interface(phy_iface));
821 if (strcmp(ethname, phy_dev->dev->name) == 0)
822 break;
823 dpmac_id++;
824 }
825 if (dpmac_id == NUM_WRIOP_PORTS)
826 continue;
827 ret = fdt_create_phy_node(fdt, offset, i,
828 &subnodeoffset,
829 phy_dev, phandle);
830 if (ret)
831 break;
832
833 ret = fdt_fixup_dpmac_phy_handle(fdt,
834 dpmac_id, phandle);
835 if (ret) {
836 fdt_del_node(fdt, subnodeoffset);
837 break;
838 }
839 /* calculate offset again as new node addition may have
840 * changed offset;
841 */
842 offset = fdt_get_ioslot_offset(fdt, mii_dev,
843 fpga_offset);
844 phandle++;
845 }
846
847 if (ret)
848 break;
849 }
850
851 return ret;
852 }
853 #endif // CONFIG_FSL_MC_ENET
854 #endif
855
856 #if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
857
858 /* Structure to hold SERDES protocols supported in case of
859 * CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
860 *
861 * @serdes_block: the index of the SERDES block
862 * @serdes_protocol: the decimal value of the protocol supported
863 * @dts_needed: DTS notes describing the current configuration are needed
864 *
865 * When dts_needed is true, the board_fit_config_name_match() function
866 * will try to exactly match the current configuration of the block with a DTS
867 * name provided.
868 */
869 static struct serdes_configuration {
870 u8 serdes_block;
871 u32 serdes_protocol;
872 bool dts_needed;
873 } supported_protocols[] = {
874 /* Serdes block #1 */
875 {1, 3, true},
876 {1, 7, true},
877 {1, 19, true},
878 {1, 20, true},
879
880 /* Serdes block #2 */
881 {2, 2, false},
882 {2, 3, false},
883 {2, 5, false},
884 {2, 11, true},
885
886 /* Serdes block #3 */
887 {3, 2, false},
888 {3, 3, false},
889 };
890
891 #define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
892
protocol_supported(u8 serdes_block,u32 protocol)893 static bool protocol_supported(u8 serdes_block, u32 protocol)
894 {
895 struct serdes_configuration serdes_conf;
896 int i;
897
898 for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
899 serdes_conf = supported_protocols[i];
900 if (serdes_conf.serdes_block == serdes_block &&
901 serdes_conf.serdes_protocol == protocol)
902 return true;
903 }
904
905 return false;
906 }
907
get_str_protocol(u8 serdes_block,u32 protocol,char * str)908 static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
909 {
910 struct serdes_configuration serdes_conf;
911 int i;
912
913 for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
914 serdes_conf = supported_protocols[i];
915 if (serdes_conf.serdes_block == serdes_block &&
916 serdes_conf.serdes_protocol == protocol) {
917 if (serdes_conf.dts_needed == true)
918 sprintf(str, "%u", protocol);
919 else
920 sprintf(str, "x");
921 return;
922 }
923 }
924 }
925
board_fit_config_name_match(const char * name)926 int board_fit_config_name_match(const char *name)
927 {
928 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
929 u32 rcw_status = in_le32(&gur->rcwsr[28]);
930 char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
931 u32 srds_s1, srds_s2, srds_s3;
932 char expected_dts[100];
933
934 srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
935 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
936
937 srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
938 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
939
940 srds_s3 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
941 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
942
943 /* Check for supported protocols. The default DTS will be used
944 * in this case
945 */
946 if (!protocol_supported(1, srds_s1) ||
947 !protocol_supported(2, srds_s2) ||
948 !protocol_supported(3, srds_s3))
949 return -1;
950
951 get_str_protocol(1, srds_s1, srds_s1_str);
952 get_str_protocol(2, srds_s2, srds_s2_str);
953 get_str_protocol(3, srds_s3, srds_s3_str);
954
955 sprintf(expected_dts, "fsl-lx2160a-qds-%s-%s-%s",
956 srds_s1_str, srds_s2_str, srds_s3_str);
957
958 if (!strcmp(name, expected_dts))
959 return 0;
960
961 return -1;
962 }
963 #endif
964