1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config SPL_MISC 17 bool "Enable Driver Model for Misc drivers in SPL" 18 depends on SPL_DM 19 help 20 Enable driver model for miscellaneous devices. This class is 21 used only for those do not fit other more general classes. A 22 set of generic read, write and ioctl methods may be used to 23 access the device. 24 25config TPL_MISC 26 bool "Enable Driver Model for Misc drivers in TPL" 27 depends on TPL_DM 28 help 29 Enable driver model for miscellaneous devices. This class is 30 used only for those do not fit other more general classes. A 31 set of generic read, write and ioctl methods may be used to 32 access the device. 33 34config ALTERA_SYSID 35 bool "Altera Sysid support" 36 depends on MISC 37 help 38 Select this to enable a sysid for Altera devices. Please find 39 details on the "Embedded Peripherals IP User Guide" of Altera. 40 41config ATSHA204A 42 bool "Support for Atmel ATSHA204A module" 43 depends on MISC 44 help 45 Enable support for I2C connected Atmel's ATSHA204A 46 CryptoAuthentication module found for example on the Turris Omnia 47 board. 48 49config ROCKCHIP_EFUSE 50 bool "Rockchip e-fuse support" 51 depends on MISC 52 help 53 Enable (read-only) access for the e-fuse block found in Rockchip 54 SoCs: accesses can either be made using byte addressing and a length 55 or through child-nodes that are generated based on the e-fuse map 56 retrieved from the DTS. 57 58 This driver currently supports the RK3399 only, but can easily be 59 extended (by porting the read function from the Linux kernel sources) 60 to support other recent Rockchip devices. 61 62config ROCKCHIP_OTP 63 bool "Rockchip OTP Support" 64 depends on MISC 65 help 66 Enable (read-only) access for the one-time-programmable memory block 67 found in Rockchip SoCs: accesses can either be made using byte 68 addressing and a length or through child-nodes that are generated 69 based on the e-fuse map retrieved from the DTS. 70 71config SIFIVE_OTP 72 bool "SiFive eMemory OTP driver" 73 depends on MISC 74 help 75 Enable support for reading and writing the eMemory OTP on the 76 SiFive SoCs. 77 78config VEXPRESS_CONFIG 79 bool "Enable support for Arm Versatile Express config bus" 80 depends on MISC 81 help 82 If you say Y here, you will get support for accessing the 83 configuration bus on the Arm Versatile Express boards via 84 a sysreg driver. 85 86config CMD_CROS_EC 87 bool "Enable crosec command" 88 depends on CROS_EC 89 help 90 Enable command-line access to the Chrome OS EC (Embedded 91 Controller). This provides the 'crosec' command which has 92 a number of sub-commands for performing EC tasks such as 93 updating its flash, accessing a small saved context area 94 and talking to the I2C bus behind the EC (if there is one). 95 96config CROS_EC 97 bool "Enable Chrome OS EC" 98 help 99 Enable access to the Chrome OS EC. This is a separate 100 microcontroller typically available on a SPI bus on Chromebooks. It 101 provides access to the keyboard, some internal storage and may 102 control access to the battery and main PMIC depending on the 103 device. You can use the 'crosec' command to access it. 104 105config SPL_CROS_EC 106 bool "Enable Chrome OS EC in SPL" 107 depends on SPL 108 help 109 Enable access to the Chrome OS EC in SPL. This is a separate 110 microcontroller typically available on a SPI bus on Chromebooks. It 111 provides access to the keyboard, some internal storage and may 112 control access to the battery and main PMIC depending on the 113 device. You can use the 'crosec' command to access it. 114 115config TPL_CROS_EC 116 bool "Enable Chrome OS EC in TPL" 117 depends on TPL 118 help 119 Enable access to the Chrome OS EC in TPL. This is a separate 120 microcontroller typically available on a SPI bus on Chromebooks. It 121 provides access to the keyboard, some internal storage and may 122 control access to the battery and main PMIC depending on the 123 device. You can use the 'crosec' command to access it. 124 125config CROS_EC_I2C 126 bool "Enable Chrome OS EC I2C driver" 127 depends on CROS_EC 128 help 129 Enable I2C access to the Chrome OS EC. This is used on older 130 ARM Chromebooks such as snow and spring before the standard bus 131 changed to SPI. The EC will accept commands across the I2C using 132 a special message protocol, and provide responses. 133 134config CROS_EC_LPC 135 bool "Enable Chrome OS EC LPC driver" 136 depends on CROS_EC 137 help 138 Enable I2C access to the Chrome OS EC. This is used on x86 139 Chromebooks such as link and falco. The keyboard is provided 140 through a legacy port interface, so on x86 machines the main 141 function of the EC is power and thermal management. 142 143config SPL_CROS_EC_LPC 144 bool "Enable Chrome OS EC LPC driver in SPL" 145 depends on CROS_EC 146 help 147 Enable I2C access to the Chrome OS EC. This is used on x86 148 Chromebooks such as link and falco. The keyboard is provided 149 through a legacy port interface, so on x86 machines the main 150 function of the EC is power and thermal management. 151 152config TPL_CROS_EC_LPC 153 bool "Enable Chrome OS EC LPC driver in TPL" 154 depends on CROS_EC 155 help 156 Enable I2C access to the Chrome OS EC. This is used on x86 157 Chromebooks such as link and falco. The keyboard is provided 158 through a legacy port interface, so on x86 machines the main 159 function of the EC is power and thermal management. 160 161config CROS_EC_SANDBOX 162 bool "Enable Chrome OS EC sandbox driver" 163 depends on CROS_EC && SANDBOX 164 help 165 Enable a sandbox emulation of the Chrome OS EC. This supports 166 keyboard (use the -l flag to enable the LCD), verified boot context, 167 EC flash read/write/erase support and a few other things. It is 168 enough to perform a Chrome OS verified boot on sandbox. 169 170config SPL_CROS_EC_SANDBOX 171 bool "Enable Chrome OS EC sandbox driver in SPL" 172 depends on SPL_CROS_EC && SANDBOX 173 help 174 Enable a sandbox emulation of the Chrome OS EC in SPL. This supports 175 keyboard (use the -l flag to enable the LCD), verified boot context, 176 EC flash read/write/erase support and a few other things. It is 177 enough to perform a Chrome OS verified boot on sandbox. 178 179config TPL_CROS_EC_SANDBOX 180 bool "Enable Chrome OS EC sandbox driver in TPL" 181 depends on TPL_CROS_EC && SANDBOX 182 help 183 Enable a sandbox emulation of the Chrome OS EC in TPL. This supports 184 keyboard (use the -l flag to enable the LCD), verified boot context, 185 EC flash read/write/erase support and a few other things. It is 186 enough to perform a Chrome OS verified boot on sandbox. 187 188config CROS_EC_SPI 189 bool "Enable Chrome OS EC SPI driver" 190 depends on CROS_EC 191 help 192 Enable SPI access to the Chrome OS EC. This is used on newer 193 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 194 provides a faster and more robust interface than I2C but the bugs 195 are less interesting. 196 197config DS4510 198 bool "Enable support for DS4510 CPU supervisor" 199 help 200 Enable support for the Maxim DS4510 CPU supervisor. It has an 201 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 202 and a configurable timer for the supervisor function. The device is 203 connected over I2C. 204 205config FSL_SEC_MON 206 bool "Enable FSL SEC_MON Driver" 207 help 208 Freescale Security Monitor block is responsible for monitoring 209 system states. 210 Security Monitor can be transitioned on any security failures, 211 like software violations or hardware security violations. 212 213config IRQ 214 bool "Interrupt controller" 215 help 216 This enables support for interrupt controllers, including ITSS. 217 Some devices have extra features, such as Apollo Lake. The 218 device has its own uclass since there are several operations 219 involved. 220 221config JZ4780_EFUSE 222 bool "Ingenic JZ4780 eFUSE support" 223 depends on ARCH_JZ47XX 224 help 225 This selects support for the eFUSE on Ingenic JZ4780 SoCs. 226 227config MXC_OCOTP 228 bool "Enable MXC OCOTP Driver" 229 depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610 230 default y 231 help 232 If you say Y here, you will get support for the One Time 233 Programmable memory pages that are stored on the some 234 Freescale i.MX processors. 235 236config NUVOTON_NCT6102D 237 bool "Enable Nuvoton NCT6102D Super I/O driver" 238 help 239 If you say Y here, you will get support for the Nuvoton 240 NCT6102D Super I/O driver. This can be used to enable or 241 disable the legacy UART, the watchdog or other devices 242 in the Nuvoton Super IO chips on X86 platforms. 243 244config P2SB 245 bool "Intel Primary to Sideband Bridge" 246 depends on X86 || SANDBOX 247 help 248 This enables support for the Intel Primary to Sideband Bridge, 249 abbreviated to P2SB. The P2SB is used to access various peripherals 250 such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI 251 space. The space is segmented into different channels and peripherals 252 are accessed by device-specific means within those channels. Devices 253 should be added in the device tree as subnodes of the P2SB. A 254 Peripheral Channel Register? (PCR) API is provided to access those 255 devices - see pcr_readl(), etc. 256 257config SPL_P2SB 258 bool "Intel Primary to Sideband Bridge in SPL" 259 depends on SPL && (X86 || SANDBOX) 260 help 261 The Primary to Sideband Bridge is used to access various peripherals 262 through memory-mapped I/O in a large chunk of PCI space. The space is 263 segmented into different channels and peripherals are accessed by 264 device-specific means within those channels. Devices should be added 265 in the device tree as subnodes of the p2sb. 266 267config TPL_P2SB 268 bool "Intel Primary to Sideband Bridge in TPL" 269 depends on TPL && (X86 || SANDBOX) 270 help 271 The Primary to Sideband Bridge is used to access various peripherals 272 through memory-mapped I/O in a large chunk of PCI space. The space is 273 segmented into different channels and peripherals are accessed by 274 device-specific means within those channels. Devices should be added 275 in the device tree as subnodes of the p2sb. 276 277config PWRSEQ 278 bool "Enable power-sequencing drivers" 279 depends on DM 280 help 281 Power-sequencing drivers provide support for controlling power for 282 devices. They are typically referenced by a phandle from another 283 device. When the device is started up, its power sequence can be 284 initiated. 285 286config SPL_PWRSEQ 287 bool "Enable power-sequencing drivers for SPL" 288 depends on PWRSEQ 289 help 290 Power-sequencing drivers provide support for controlling power for 291 devices. They are typically referenced by a phandle from another 292 device. When the device is started up, its power sequence can be 293 initiated. 294 295config PCA9551_LED 296 bool "Enable PCA9551 LED driver" 297 help 298 Enable driver for PCA9551 LED controller. This controller 299 is connected via I2C. So I2C needs to be enabled. 300 301config PCA9551_I2C_ADDR 302 hex "I2C address of PCA9551 LED controller" 303 depends on PCA9551_LED 304 default 0x60 305 help 306 The I2C address of the PCA9551 LED controller. 307 308config STM32MP_FUSE 309 bool "Enable STM32MP fuse wrapper providing the fuse API" 310 depends on ARCH_STM32MP && MISC 311 default y if CMD_FUSE 312 help 313 If you say Y here, you will get support for the fuse API (OTP) 314 for STM32MP architecture. 315 This API is needed for CMD_FUSE. 316 317config STM32_RCC 318 bool "Enable RCC driver for the STM32 SoC's family" 319 depends on (ARCH_STM32 || ARCH_STM32MP) && MISC 320 help 321 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 322 block) is responsible of the management of the clock and reset 323 generation. 324 This driver is similar to an MFD driver in the Linux kernel. 325 326config TEGRA_CAR 327 bool "Enable support for the Tegra CAR driver" 328 depends on TEGRA_NO_BPMP 329 help 330 The Tegra CAR (Clock and Reset Controller) is a HW module that 331 controls almost all clocks and resets in a Tegra SoC. 332 333config TEGRA186_BPMP 334 bool "Enable support for the Tegra186 BPMP driver" 335 depends on TEGRA186 336 help 337 The Tegra BPMP (Boot and Power Management Processor) is a separate 338 auxiliary CPU embedded into Tegra to perform power management work, 339 and controls related features such as clocks, resets, power domains, 340 PMIC I2C bus, etc. This driver provides the core low-level 341 communication path by which feature-specific drivers (such as clock) 342 can make requests to the BPMP. This driver is similar to an MFD 343 driver in the Linux kernel. 344 345config TEST_DRV 346 bool "Enable support for test drivers" 347 default y if SANDBOX 348 help 349 This enables drivers and uclasses that provides a way of testing the 350 operations of memory allocation and driver/uclass methods in driver 351 model. This should only be enabled for testing as it is not useful for 352 anything else. 353 354config TWL4030_LED 355 bool "Enable TWL4030 LED controller" 356 help 357 Enable this to add support for the TWL4030 LED controller. 358 359config WINBOND_W83627 360 bool "Enable Winbond Super I/O driver" 361 help 362 If you say Y here, you will get support for the Winbond 363 W83627 Super I/O driver. This can be used to enable the 364 legacy UART or other devices in the Winbond Super IO chips 365 on X86 platforms. 366 367config QFW 368 bool 369 help 370 Hidden option to enable QEMU fw_cfg interface and uclass. This will 371 be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 372 373config QFW_PIO 374 bool 375 depends on QFW 376 help 377 Hidden option to enable PIO QEMU fw_cfg interface. This will be 378 selected by the appropriate QEMU board. 379 380config QFW_MMIO 381 bool 382 depends on QFW 383 help 384 Hidden option to enable MMIO QEMU fw_cfg interface. This will be 385 selected by the appropriate QEMU board. 386 387config I2C_EEPROM 388 bool "Enable driver for generic I2C-attached EEPROMs" 389 depends on MISC 390 help 391 Enable a generic driver for EEPROMs attached via I2C. 392 393 394config SPL_I2C_EEPROM 395 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 396 depends on MISC && SPL && SPL_DM 397 help 398 This option is an SPL-variant of the I2C_EEPROM option. 399 See the help of I2C_EEPROM for details. 400 401if I2C_EEPROM 402 403config SYS_I2C_EEPROM_ADDR 404 hex "Chip address of the EEPROM device" 405 default 0 406 407config SYS_I2C_EEPROM_BUS 408 int "I2C bus of the EEPROM device." 409 default 0 410 411config SYS_EEPROM_SIZE 412 int "Size in bytes of the EEPROM device" 413 default 256 414 415config SYS_EEPROM_PAGE_WRITE_BITS 416 int "Number of bits used to address bytes in a single page" 417 default 0 418 help 419 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 420 A 64 byte page, for example would require six bits. 421 422config SYS_EEPROM_PAGE_WRITE_DELAY_MS 423 int "Number of milliseconds to delay between page writes" 424 default 0 425 426config SYS_I2C_EEPROM_ADDR_LEN 427 int "Length in bytes of the EEPROM memory array address" 428 default 1 429 help 430 Note: This is NOT the chip address length! 431 432config SYS_I2C_EEPROM_ADDR_OVERFLOW 433 hex "EEPROM Address Overflow" 434 default 0 435 help 436 EEPROM chips that implement "address overflow" are ones 437 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 438 address and the extra bits end up in the "chip address" bit 439 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 440 byte chips. 441 442endif 443 444config GDSYS_RXAUI_CTRL 445 bool "Enable gdsys RXAUI control driver" 446 depends on MISC 447 help 448 Support gdsys FPGA's RXAUI control. 449 450config GDSYS_IOEP 451 bool "Enable gdsys IOEP driver" 452 depends on MISC 453 help 454 Support gdsys FPGA's IO endpoint driver. 455 456config MPC83XX_SERDES 457 bool "Enable MPC83xx serdes driver" 458 depends on MISC 459 help 460 Support for serdes found on MPC83xx SoCs. 461 462config FS_LOADER 463 bool "Enable loader driver for file system" 464 help 465 This is file system generic loader which can be used to load 466 the file image from the storage into target such as memory. 467 468 The consumer driver would then use this loader to program whatever, 469 ie. the FPGA device. 470 471config GDSYS_SOC 472 bool "Enable gdsys SOC driver" 473 depends on MISC 474 help 475 Support for gdsys IHS SOC, a simple bus associated with each gdsys 476 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 477 register maps are contained within the FPGA's register map. 478 479config IHS_FPGA 480 bool "Enable IHS FPGA driver" 481 depends on MISC 482 help 483 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 484 gdsys devices, which supply the majority of the functionality offered 485 by the devices. This driver supports both CON and CPU variants of the 486 devices, depending on the device tree entry. 487config ESM_K3 488 bool "Enable K3 ESM driver" 489 depends on ARCH_K3 490 help 491 Support ESM (Error Signaling Module) on TI K3 SoCs. 492 493config MICROCHIP_FLEXCOM 494 bool "Enable Microchip Flexcom driver" 495 depends on MISC 496 help 497 The Atmel Flexcom is just a wrapper which embeds a SPI controller, 498 an I2C controller and an USART. 499 Only one function can be used at a time and is chosen at boot time 500 according to the device tree. 501 502config K3_AVS0 503 depends on ARCH_K3 && SPL_DM_REGULATOR 504 bool "AVS class 0 support for K3 devices" 505 help 506 K3 devices have the optimized voltage values for the main voltage 507 domains stored in efuse within the VTM IP. This driver reads the 508 optimized voltage from the efuse, so that it can be programmed 509 to the PMIC on board. 510 511config ESM_PMIC 512 bool "Enable PMIC ESM driver" 513 depends on DM_PMIC 514 help 515 Support ESM (Error Signal Monitor) on PMIC devices. ESM is used 516 typically to reboot the board in error condition. 517 518endmenu 519