1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2018 Marvell International Ltd. 4 */ 5 6 #ifndef BGX_H 7 #define BGX_H 8 9 #include <asm/arch/board.h> 10 11 /* PCI device IDs */ 12 #define PCI_DEVICE_ID_OCTEONTX_BGX 0xA026 13 #define PCI_DEVICE_ID_OCTEONTX_RGX 0xA054 14 15 #define MAX_LMAC_PER_BGX 4 16 #define MAX_BGX_CHANS_PER_LMAC 16 17 #define MAX_DMAC_PER_LMAC 8 18 #define MAX_FRAME_SIZE 9216 19 20 #define MAX_DMAC_PER_LMAC_TNS_BYPASS_MODE 2 21 22 #define MAX_LMAC (MAX_BGX_PER_NODE * MAX_LMAC_PER_BGX) 23 24 #define NODE_ID_MASK 0x300000000000 25 #define NODE_ID(x) (((x) & NODE_ID_MASK) >> 44) 26 27 /* Registers */ 28 #define GSERX_CFG(x) (0x87E090000080ull + (x) * 0x1000000ull) 29 #define GSERX_SCRATCH(x) (0x87E090000020ull + (x) * 0x1000000ull) 30 #define GSERX_PHY_CTL(x) (0x87E090000000ull + (x) * 0x1000000ull) 31 #define GSERX_CFG_BGX BIT(2) 32 #define GSER_RX_EIE_DETSTS(x) (0x87E090000150ull + (x) * 0x1000000ull) 33 #define GSER_CDRLOCK (8) 34 #define GSER_BR_RXX_CTL(x, y) (0x87E090000400ull + (x) * 0x1000000ull + \ 35 (y) * 0x80) 36 #define GSER_BR_RXX_CTL_RXT_SWM BIT(2) 37 #define GSER_BR_RXX_EER(x, y) (0x87E090000418ull + (x) * 0x1000000ull + \ 38 (y) * 0x80) 39 #define GSER_BR_RXX_EER_RXT_ESV BIT(14) 40 #define GSER_BR_RXX_EER_RXT_EER BIT(15) 41 #define EER_RXT_ESV (14) 42 43 #define BGX_CMRX_CFG 0x00 44 #define CMR_PKT_TX_EN BIT_ULL(13) 45 #define CMR_PKT_RX_EN BIT_ULL(14) 46 #define CMR_EN BIT_ULL(15) 47 #define BGX_CMR_GLOBAL_CFG 0x08 48 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6) 49 #define BGX_CMRX_RX_ID_MAP 0x60 50 #define BGX_CMRX_RX_STAT0 0x70 51 #define BGX_CMRX_RX_STAT1 0x78 52 #define BGX_CMRX_RX_STAT2 0x80 53 #define BGX_CMRX_RX_STAT3 0x88 54 #define BGX_CMRX_RX_STAT4 0x90 55 #define BGX_CMRX_RX_STAT5 0x98 56 #define BGX_CMRX_RX_STAT6 0xA0 57 #define BGX_CMRX_RX_STAT7 0xA8 58 #define BGX_CMRX_RX_STAT8 0xB0 59 #define BGX_CMRX_RX_STAT9 0xB8 60 #define BGX_CMRX_RX_STAT10 0xC0 61 #define BGX_CMRX_RX_BP_DROP 0xC8 62 #define BGX_CMRX_RX_DMAC_CTL 0x0E8 63 #define BGX_CMR_RX_DMACX_CAM 0x200 64 #define RX_DMACX_CAM_EN BIT_ULL(48) 65 #define RX_DMACX_CAM_LMACID(x) ((x) << 49) 66 #define RX_DMAC_COUNT 32 67 #define BGX_CMR_RX_STREERING 0x300 68 #define RX_TRAFFIC_STEER_RULE_COUNT 8 69 #define BGX_CMR_CHAN_MSK_AND 0x450 70 #define BGX_CMR_BIST_STATUS 0x460 71 #define BGX_CMR_RX_LMACS 0x468 72 #define BGX_CMRX_TX_STAT0 0x600 73 #define BGX_CMRX_TX_STAT1 0x608 74 #define BGX_CMRX_TX_STAT2 0x610 75 #define BGX_CMRX_TX_STAT3 0x618 76 #define BGX_CMRX_TX_STAT4 0x620 77 #define BGX_CMRX_TX_STAT5 0x628 78 #define BGX_CMRX_TX_STAT6 0x630 79 #define BGX_CMRX_TX_STAT7 0x638 80 #define BGX_CMRX_TX_STAT8 0x640 81 #define BGX_CMRX_TX_STAT9 0x648 82 #define BGX_CMRX_TX_STAT10 0x650 83 #define BGX_CMRX_TX_STAT11 0x658 84 #define BGX_CMRX_TX_STAT12 0x660 85 #define BGX_CMRX_TX_STAT13 0x668 86 #define BGX_CMRX_TX_STAT14 0x670 87 #define BGX_CMRX_TX_STAT15 0x678 88 #define BGX_CMRX_TX_STAT16 0x680 89 #define BGX_CMRX_TX_STAT17 0x688 90 #define BGX_CMR_TX_LMACS 0x1000 91 92 #define BGX_SPUX_CONTROL1 0x10000 93 #define SPU_CTL_LOW_POWER BIT_ULL(11) 94 #define SPU_CTL_LOOPBACK BIT_ULL(14) 95 #define SPU_CTL_RESET BIT_ULL(15) 96 #define BGX_SPUX_STATUS1 0x10008 97 #define SPU_STATUS1_RCV_LNK BIT_ULL(2) 98 #define BGX_SPUX_STATUS2 0x10020 99 #define SPU_STATUS2_RCVFLT BIT_ULL(10) 100 #define BGX_SPUX_BX_STATUS 0x10028 101 #define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12) 102 #define BGX_SPUX_BR_STATUS1 0x10030 103 #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0) 104 #define SPU_BR_STATUS_RCV_LNK BIT_ULL(12) 105 #define BGX_SPUX_BR_PMD_CRTL 0x10068 106 #define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1) 107 #define BGX_SPUX_BR_PMD_LP_CUP 0x10078 108 #define BGX_SPUX_BR_PMD_LD_CUP 0x10088 109 #define BGX_SPUX_BR_PMD_LD_REP 0x10090 110 #define BGX_SPUX_FEC_CONTROL 0x100A0 111 #define SPU_FEC_CTL_FEC_EN BIT_ULL(0) 112 #define SPU_FEC_CTL_ERR_EN BIT_ULL(1) 113 #define BGX_SPUX_AN_CONTROL 0x100C8 114 #define SPU_AN_CTL_AN_EN BIT_ULL(12) 115 #define SPU_AN_CTL_XNP_EN BIT_ULL(13) 116 #define SPU_AN_CTL_AN_RESTART BIT_ULL(15) 117 #define BGX_SPUX_AN_STATUS 0x100D0 118 #define SPU_AN_STS_AN_COMPLETE BIT_ULL(5) 119 #define BGX_SPUX_AN_ADV 0x100D8 120 #define BGX_SPUX_MISC_CONTROL 0x10218 121 #define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10) 122 #define SPU_MISC_CTL_RX_DIS BIT_ULL(12) 123 #define BGX_SPUX_INT 0x10220 /* +(0..3) << 20 */ 124 #define BGX_SPUX_INT_W1S 0x10228 125 #define BGX_SPUX_INT_ENA_W1C 0x10230 126 #define BGX_SPUX_INT_ENA_W1S 0x10238 127 #define BGX_SPU_DBG_CONTROL 0x10300 128 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18) 129 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29) 130 131 #define BGX_SMUX_RX_INT 0x20000 132 #define BGX_SMUX_RX_JABBER 0x20030 133 #define BGX_SMUX_RX_CTL 0x20048 134 #define SMU_RX_CTL_STATUS (3ull << 0) 135 #define BGX_SMUX_TX_APPEND 0x20100 136 #define SMU_TX_APPEND_FCS_D BIT_ULL(2) 137 #define BGX_SMUX_TX_MIN_PKT 0x20118 138 #define BGX_SMUX_TX_INT 0x20140 139 #define BGX_SMUX_TX_CTL 0x20178 140 #define SMU_TX_CTL_DIC_EN BIT_ULL(0) 141 #define SMU_TX_CTL_UNI_EN BIT_ULL(1) 142 #define SMU_TX_CTL_LNK_STATUS (3ull << 4) 143 #define BGX_SMUX_TX_THRESH 0x20180 144 #define BGX_SMUX_CTL 0x20200 145 #define SMU_CTL_RX_IDLE BIT_ULL(0) 146 #define SMU_CTL_TX_IDLE BIT_ULL(1) 147 148 #define BGX_GMP_PCS_MRX_CTL 0x30000 149 #define PCS_MRX_CTL_RST_AN BIT_ULL(9) 150 #define PCS_MRX_CTL_PWR_DN BIT_ULL(11) 151 #define PCS_MRX_CTL_AN_EN BIT_ULL(12) 152 #define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14) 153 #define PCS_MRX_CTL_RESET BIT_ULL(15) 154 #define BGX_GMP_PCS_MRX_STATUS 0x30008 155 #define PCS_MRX_STATUS_AN_CPT BIT_ULL(5) 156 #define BGX_GMP_PCS_ANX_AN_RESULTS 0x30020 157 #define BGX_GMP_PCS_SGM_AN_ADV 0x30068 158 #define BGX_GMP_PCS_MISCX_CTL 0x30078 159 #define PCS_MISCX_CTL_DISP_EN BIT_ULL(13) 160 #define PCS_MISC_CTL_GMX_ENO BIT_ULL(11) 161 #define PCS_MISC_CTL_SAMP_PT_MASK 0x7Full 162 #define PCS_MISC_CTL_MODE BIT_ULL(8) 163 #define BGX_GMP_GMI_PRTX_CFG 0x38020 164 #define GMI_PORT_CFG_SPEED BIT_ULL(1) 165 #define GMI_PORT_CFG_DUPLEX BIT_ULL(2) 166 #define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3) 167 #define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8) 168 #define BGX_GMP_GMI_RXX_JABBER 0x38038 169 #define BGX_GMP_GMI_TXX_THRESH 0x38210 170 #define BGX_GMP_GMI_TXX_APPEND 0x38218 171 #define BGX_GMP_GMI_TXX_SLOT 0x38220 172 #define BGX_GMP_GMI_TXX_BURST 0x38228 173 #define BGX_GMP_GMI_TXX_MIN_PKT 0x38240 174 #define BGX_GMP_GMI_TXX_SGMII_CTL 0x38300 175 176 #define BGX_MSIX_VEC_0_29_ADDR 0x400000 /* +(0..29) << 4 */ 177 #define BGX_MSIX_VEC_0_29_CTL 0x400008 178 #define BGX_MSIX_PBA_0 0x4F0000 179 180 /* MSI-X interrupts */ 181 #define BGX_MSIX_VECTORS 30 182 #define BGX_LMAC_VEC_OFFSET 7 183 #define BGX_MSIX_VEC_SHIFT 4 184 185 #define CMRX_INT 0 186 #define SPUX_INT 1 187 #define SMUX_RX_INT 2 188 #define SMUX_TX_INT 3 189 #define GMPX_PCS_INT 4 190 #define GMPX_GMI_RX_INT 5 191 #define GMPX_GMI_TX_INT 6 192 #define CMR_MEM_INT 28 193 #define SPU_MEM_INT 29 194 195 #define LMAC_INTR_LINK_UP BIT(0) 196 #define LMAC_INTR_LINK_DOWN BIT(1) 197 198 /* RX_DMAC_CTL configuration*/ 199 enum MCAST_MODE { 200 MCAST_MODE_REJECT, 201 MCAST_MODE_ACCEPT, 202 MCAST_MODE_CAM_FILTER, 203 RSVD 204 }; 205 206 #define BCAST_ACCEPT 1 207 #define CAM_ACCEPT 1 208 209 int octeontx_bgx_initialize(unsigned int bgx_idx, unsigned int node); 210 void bgx_add_dmac_addr(u64 dmac, int node, int bgx_idx, int lmac); 211 void bgx_get_count(int node, int *bgx_count); 212 int bgx_get_lmac_count(int node, int bgx); 213 void bgx_print_stats(int bgx_idx, int lmac); 214 void xcv_init_hw(void); 215 void xcv_setup_link(bool link_up, int link_speed); 216 217 #undef LINK_INTR_ENABLE 218 219 enum qlm_mode { 220 QLM_MODE_SGMII, /* SGMII, each lane independent */ 221 QLM_MODE_XAUI, /* 1 XAUI or DXAUI, 4 lanes */ 222 QLM_MODE_RXAUI, /* 2 RXAUI, 2 lanes each */ 223 QLM_MODE_XFI, /* 4 XFI, 1 lane each */ 224 QLM_MODE_XLAUI, /* 1 XLAUI, 4 lanes each */ 225 QLM_MODE_10G_KR, /* 4 10GBASE-KR, 1 lane each */ 226 QLM_MODE_40G_KR4, /* 1 40GBASE-KR4, 4 lanes each */ 227 QLM_MODE_QSGMII, /* 4 QSGMII, each lane independent */ 228 QLM_MODE_RGMII, /* 1 RGX */ 229 }; 230 231 struct phy_info { 232 int mdio_bus; 233 int phy_addr; 234 bool autoneg_dis; 235 }; 236 237 struct bgx_board_info { 238 struct phy_info phy_info[MAX_LMAC_PER_BGX]; 239 bool lmac_reg[MAX_LMAC_PER_BGX]; 240 bool lmac_enable[MAX_LMAC_PER_BGX]; 241 }; 242 243 enum LMAC_TYPE { 244 BGX_MODE_SGMII = 0, /* 1 lane, 1.250 Gbaud */ 245 BGX_MODE_XAUI = 1, /* 4 lanes, 3.125 Gbaud */ 246 BGX_MODE_DXAUI = 1, /* 4 lanes, 6.250 Gbaud */ 247 BGX_MODE_RXAUI = 2, /* 2 lanes, 6.250 Gbaud */ 248 BGX_MODE_XFI = 3, /* 1 lane, 10.3125 Gbaud */ 249 BGX_MODE_XLAUI = 4, /* 4 lanes, 10.3125 Gbaud */ 250 BGX_MODE_10G_KR = 3,/* 1 lane, 10.3125 Gbaud */ 251 BGX_MODE_40G_KR = 4,/* 4 lanes, 10.3125 Gbaud */ 252 BGX_MODE_RGMII = 5, 253 BGX_MODE_QSGMII = 6, 254 BGX_MODE_INVALID = 7, 255 }; 256 257 int rxaui_phy_xs_init(struct mii_dev *bus, int phy_addr); 258 259 #endif /* BGX_H */ 260