1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * r8a7791/r8a7743 processor support - PFC hardware block.
4 *
5 * Copyright (C) 2013 Renesas Electronics Corporation
6 * Copyright (C) 2014-2017 Cogent Embedded, Inc.
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <dm/pinctrl.h>
13 #include <linux/kernel.h>
14
15 #include "sh_pfc.h"
16
17 /*
18 * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
19 * which case they support both 3.3V and 1.8V signalling.
20 */
21 #define CPU_ALL_GP(fn, sfx) \
22 PORT_GP_32(0, fn, sfx), \
23 PORT_GP_26(1, fn, sfx), \
24 PORT_GP_32(2, fn, sfx), \
25 PORT_GP_32(3, fn, sfx), \
26 PORT_GP_32(4, fn, sfx), \
27 PORT_GP_32(5, fn, sfx), \
28 PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
29 PORT_GP_1(6, 24, fn, sfx), \
30 PORT_GP_1(6, 25, fn, sfx), \
31 PORT_GP_1(6, 26, fn, sfx), \
32 PORT_GP_1(6, 27, fn, sfx), \
33 PORT_GP_1(6, 28, fn, sfx), \
34 PORT_GP_1(6, 29, fn, sfx), \
35 PORT_GP_1(6, 30, fn, sfx), \
36 PORT_GP_1(6, 31, fn, sfx), \
37 PORT_GP_26(7, fn, sfx)
38
39 enum {
40 PINMUX_RESERVED = 0,
41
42 PINMUX_DATA_BEGIN,
43 GP_ALL(DATA),
44 PINMUX_DATA_END,
45
46 PINMUX_FUNCTION_BEGIN,
47 GP_ALL(FN),
48
49 /* GPSR0 */
50 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
51 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
52 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
53 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
54 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
55 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
56
57 /* GPSR1 */
58 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
59 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
60 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
61 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
62 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
63 FN_IP3_21_20,
64
65 /* GPSR2 */
66 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
67 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
68 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
69 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
70 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
71 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
72 FN_IP6_5_3, FN_IP6_7_6,
73
74 /* GPSR3 */
75 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
76 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
77 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
78 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
79 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
80 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
81 FN_IP9_18_17,
82
83 /* GPSR4 */
84 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
85 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
86 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
87 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
88 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
89 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
90 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
91 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
92
93 /* GPSR5 */
94 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
95 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
96 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
97 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
98 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
99 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
100 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
101
102 /* GPSR6 */
103 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
104 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
105 FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
106 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
107 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
108 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
109 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
110 FN_USB1_OVC, FN_DU0_DOTCLKIN,
111
112 /* GPSR7 */
113 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
114 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
115 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
116 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
117 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
118 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
119
120 /* IPSR0 */
121 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
122 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
123 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
124 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
125 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
126 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
127
128 /* IPSR1 */
129 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
130 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
131 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
132 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
133 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
134 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
135 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
136 FN_A15, FN_BPFCLK_C,
137 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
138 FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
139 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
140
141 /* IPSR2 */
142 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
143 FN_A20, FN_SPCLK,
144 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
145 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
146 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
147 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
148 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
149 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
150 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
151 FN_EX_CS1_N, FN_MSIOF2_SCK,
152 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
153 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
154
155 /* IPSR3 */
156 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
157 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
158 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
159 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
160 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
161 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
162 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
163 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
164 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
165 FN_DREQ0, FN_PWM3, FN_TPU_TO3,
166 FN_DACK0, FN_DRACK0, FN_REMOCON,
167 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
168 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
169 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
170 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
171
172 /* IPSR4 */
173 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
174 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
175 FN_GLO_I0_D,
176 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
177 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
178 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
179 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
180 FN_GLO_Q1_D, FN_HCTS1_N_E,
181 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
182 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
183 FN_SSI_SCK4, FN_GLO_SS_D,
184 FN_SSI_WS4, FN_GLO_RFON_D,
185 FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
186 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
187 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
188
189 /* IPSR5 */
190 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
191 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
192 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
193 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
194 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
195 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
196 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
197 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
198 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
199 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
200 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
201 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
202 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
203 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
204 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
205
206 /* IPSR6 */
207 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
208 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
209 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
210 FN_SCIFA2_RXD, FN_FMIN_E,
211 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
212 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
213 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
214 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
215 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
216 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
217 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
218 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
219 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
220 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
221
222 /* IPSR7 */
223 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
224 FN_SCIF_CLK_B, FN_GPS_MAG_D,
225 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
226 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
227 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
228 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
229 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
230 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
231 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
232 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
233 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
234 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
235 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
236 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
237 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
238 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
239 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
240 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
241
242 /* IPSR8 */
243 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
244 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
245 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
246 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
247 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
248 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
249 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
250 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
251 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
252 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
253 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
254 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
255 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
256 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
257 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
258 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
259 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
260
261 /* IPSR9 */
262 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
263 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
264 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
265 FN_DU1_DOTCLKOUT0, FN_QCLK,
266 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
267 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
268 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
269 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
270 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
271 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
272 FN_DU1_DISP, FN_QPOLA,
273 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
274 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
275 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
276 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
277 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
278 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
279 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
280 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
281
282 /* IPSR10 */
283 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
284 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
285 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
286 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
287 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
288 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
289 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
290 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
291 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
292 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
293 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
294 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
295 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
296 FN_TS_SDATA0_C, FN_ATACS11_N,
297 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
298 FN_TS_SCK0_C, FN_ATAG1_N,
299 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
300 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
301 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
302
303 /* IPSR11 */
304 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
305 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
306 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
307 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
308 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
309 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
310 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
311 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
312 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
313 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
314 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
315 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
316 FN_VI1_DATA7, FN_AVB_MDC,
317 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
318 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
319
320 /* IPSR12 */
321 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
322 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
323 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
324 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
325 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
326 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
327 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
328 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
329 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
330 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
331 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
332 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
333 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
334 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
335 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
336 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
337 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
338
339 /* IPSR13 */
340 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
341 FN_ADICLK_B, FN_MSIOF0_SS1_C,
342 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
343 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
344 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
345 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
346 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
347 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
348 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
349 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
350 FN_SCIFA5_TXD_B, FN_TX3_C,
351 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
352 FN_SCIFA5_RXD_B, FN_RX3_C,
353 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
354 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
355 FN_SD1_DATA3, FN_IERX_B,
356 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
357
358 /* IPSR14 */
359 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
360 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
361 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
362 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
363 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
364 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
365 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
366 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
367 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
368 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
369 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
370 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
371 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
372 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
373
374 /* IPSR15 */
375 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
376 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
377 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
378 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
379 FN_PWM5_B, FN_SCIFA3_TXD_C,
380 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
381 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
382 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
383 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
384 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
385 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
386 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
387 FN_TCLK2, FN_VI1_DATA3_C,
388 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
389 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
390
391 /* IPSR16 */
392 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
393 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
394 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
395 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
396 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
397
398 /* MOD_SEL */
399 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
400 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
401 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
402 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
403 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
404 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
405 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
406 FN_SEL_QSP_0, FN_SEL_QSP_1,
407 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
408 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
409 FN_SEL_HSCIF1_4,
410 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
411 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
412 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
413 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
414 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
415
416 /* MOD_SEL2 */
417 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
418 FN_SEL_SCIF0_4,
419 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
420 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
421 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
422 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
423 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
424 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
425 FN_SEL_ADG_0, FN_SEL_ADG_1,
426 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
427 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
428 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
429 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
430 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
431 FN_SEL_SIM_0, FN_SEL_SIM_1,
432 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
433
434 /* MOD_SEL3 */
435 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
436 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
437 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
438 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
439 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
440 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
441 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
442 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
443 FN_SEL_MMC_0, FN_SEL_MMC_1,
444 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
445 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
446 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
447 FN_SEL_I2C1_4,
448 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
449
450 /* MOD_SEL4 */
451 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
452 FN_SEL_SOF1_4,
453 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
454 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
455 FN_SEL_RAD_0, FN_SEL_RAD_1,
456 FN_SEL_RCN_0, FN_SEL_RCN_1,
457 FN_SEL_RSP_0, FN_SEL_RSP_1,
458 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
459 FN_SEL_SCIF2_4,
460 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
461 FN_SEL_SOF2_4,
462 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
463 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
464 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
465 PINMUX_FUNCTION_END,
466
467 PINMUX_MARK_BEGIN,
468
469 EX_CS0_N_MARK, RD_N_MARK,
470
471 AUDIO_CLKA_MARK,
472
473 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
474 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
475 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
476
477 SD1_CLK_MARK,
478
479 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
480 DU0_DOTCLKIN_MARK,
481
482 /* IPSR0 */
483 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
484 D6_MARK, D7_MARK, D8_MARK,
485 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
486 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
487 PWM2_B_MARK,
488 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
489 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
490 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
491
492 /* IPSR1 */
493 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
494 A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
495 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
496 A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
497 A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
498 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
499 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
500 A15_MARK, BPFCLK_C_MARK,
501 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
502 A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
503 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
504
505 /* IPSR2 */
506 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
507 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
508 A20_MARK, SPCLK_MARK,
509 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
510 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
511 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
512 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
513 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
514 RX1_MARK, SCIFA1_RXD_MARK,
515 CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
516 CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
517 EX_CS1_N_MARK, MSIOF2_SCK_MARK,
518 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
519 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
520 ATAG0_N_MARK, EX_WAIT1_MARK,
521
522 /* IPSR3 */
523 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
524 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
525 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
526 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
527 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
528 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
529 SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
530 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
531 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
532 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
533 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
534 DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
535 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
536 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
537 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
538 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
539 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
540 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
541
542 /* IPSR4 */
543 SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
544 SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
545 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
546 SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
547 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
548 SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
549 SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
550 HSCK1_E_MARK,
551 SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
552 GLO_Q1_D_MARK, HCTS1_N_E_MARK,
553 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
554 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
555 SSI_SCK4_MARK, GLO_SS_D_MARK,
556 SSI_WS4_MARK, GLO_RFON_D_MARK,
557 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
558 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
559 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
560
561 /* IPSR5 */
562 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
563 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
564 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
565 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
566 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
567 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
568 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
569 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
570 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
571 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
572 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
573 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
574 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
575 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
576 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
577
578 /* IPSR6 */
579 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
580 SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
581 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
582 SCIFA2_RXD_MARK, FMIN_E_MARK,
583 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
584 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
585 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
586 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
587 IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
588 IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
589 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
590 IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
591 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
592 I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
593 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
594 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
595 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
596 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
597
598 /* IPSR7 */
599 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
600 SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
601 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
602 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
603 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
604 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
605 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
606 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
607 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
608 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
609 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
610 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
611 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
612 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
613 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
614 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
615 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
616 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
617
618 /* IPSR8 */
619 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
620 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
621 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
622 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
623 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
624 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
625 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
626 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
627 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
628 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
629 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
630 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
631 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
632 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
633 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
634 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
635 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
636 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
637
638 /* IPSR9 */
639 DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
640 DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
641 SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
642 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
643 DU1_DOTCLKOUT0_MARK, QCLK_MARK,
644 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
645 TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
646 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
647 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
648 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
649 CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
650 DU1_DISP_MARK, QPOLA_MARK,
651 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
652 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
653 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
654 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
655 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
656 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
657 VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
658 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
659
660 /* IPSR10 */
661 VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
662 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
663 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
664 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
665 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
666 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
667 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
668 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
669 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
670 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
671 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
672 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
673 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
674 TS_SDATA0_C_MARK, ATACS11_N_MARK,
675 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
676 TS_SCK0_C_MARK, ATAG1_N_MARK,
677 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
678 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
679 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
680 I2C1_SCL_D_MARK,
681
682 /* IPSR11 */
683 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
684 I2C1_SDA_D_MARK,
685 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
686 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
687 I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
688 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
689 TX4_B_MARK, SCIFA4_TXD_B_MARK,
690 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
691 RX4_B_MARK, SCIFA4_RXD_B_MARK,
692 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
693 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
694 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
695 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
696 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
697 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
698 VI1_DATA7_MARK, AVB_MDC_MARK,
699 ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
700 ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
701
702 /* IPSR12 */
703 ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
704 ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
705 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
706 I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
707 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
708 I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
709 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
710 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
711 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
712 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
713 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
714 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
715 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
716 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
717 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
718 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
719 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
720 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
721
722 /* IPSR13 */
723 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
724 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
725 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
726 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
727 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
728 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
729 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
730 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
731 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
732 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
733 SCIFA5_TXD_B_MARK, TX3_C_MARK,
734 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
735 SCIFA5_RXD_B_MARK, RX3_C_MARK,
736 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
737 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
738 SD1_DATA3_MARK, IERX_B_MARK,
739 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
740
741 /* IPSR14 */
742 SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
743 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
744 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
745 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
746 SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
747 SCIFA5_TXD_C_MARK,
748 SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
749 SCIFA5_RXD_C_MARK,
750 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
751 VI1_CLK_C_MARK, VI1_G0_B_MARK,
752 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
753 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
754 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
755 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
756 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
757 VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
758 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
759 VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
760
761 /* IPSR15 */
762 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
763 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
764 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
765 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
766 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
767 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
768 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
769 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
770 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
771 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
772 TCLK1_MARK, VI1_DATA1_C_MARK,
773 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
774 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
775 TCLK2_MARK, VI1_DATA3_C_MARK,
776 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
777 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
778 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
779 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
780
781 /* IPSR16 */
782 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
783 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
784 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
785 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
786 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
787 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
788 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
789 PINMUX_MARK_END,
790 };
791
792 static const u16 pinmux_data[] = {
793 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
794
795 PINMUX_SINGLE(EX_CS0_N),
796 PINMUX_SINGLE(RD_N),
797 PINMUX_SINGLE(AUDIO_CLKA),
798 PINMUX_SINGLE(VI0_CLK),
799 PINMUX_SINGLE(VI0_DATA0_VI0_B0),
800 PINMUX_SINGLE(VI0_DATA1_VI0_B1),
801 PINMUX_SINGLE(VI0_DATA2_VI0_B2),
802 PINMUX_SINGLE(VI0_DATA4_VI0_B4),
803 PINMUX_SINGLE(VI0_DATA5_VI0_B5),
804 PINMUX_SINGLE(VI0_DATA6_VI0_B6),
805 PINMUX_SINGLE(VI0_DATA7_VI0_B7),
806 PINMUX_SINGLE(USB0_PWEN),
807 PINMUX_SINGLE(USB0_OVC),
808 PINMUX_SINGLE(USB1_PWEN),
809 PINMUX_SINGLE(USB1_OVC),
810 PINMUX_SINGLE(DU0_DOTCLKIN),
811 PINMUX_SINGLE(SD1_CLK),
812
813 /* IPSR0 */
814 PINMUX_IPSR_GPSR(IP0_0, D0),
815 PINMUX_IPSR_GPSR(IP0_1, D1),
816 PINMUX_IPSR_GPSR(IP0_2, D2),
817 PINMUX_IPSR_GPSR(IP0_3, D3),
818 PINMUX_IPSR_GPSR(IP0_4, D4),
819 PINMUX_IPSR_GPSR(IP0_5, D5),
820 PINMUX_IPSR_GPSR(IP0_6, D6),
821 PINMUX_IPSR_GPSR(IP0_7, D7),
822 PINMUX_IPSR_GPSR(IP0_8, D8),
823 PINMUX_IPSR_GPSR(IP0_9, D9),
824 PINMUX_IPSR_GPSR(IP0_10, D10),
825 PINMUX_IPSR_GPSR(IP0_11, D11),
826 PINMUX_IPSR_GPSR(IP0_12, D12),
827 PINMUX_IPSR_GPSR(IP0_13, D13),
828 PINMUX_IPSR_GPSR(IP0_14, D14),
829 PINMUX_IPSR_GPSR(IP0_15, D15),
830 PINMUX_IPSR_GPSR(IP0_18_16, A0),
831 PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
832 PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
833 PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
834 PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
835 PINMUX_IPSR_GPSR(IP0_20_19, A1),
836 PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
837 PINMUX_IPSR_GPSR(IP0_22_21, A2),
838 PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
839 PINMUX_IPSR_GPSR(IP0_24_23, A3),
840 PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
841 PINMUX_IPSR_GPSR(IP0_26_25, A4),
842 PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
843 PINMUX_IPSR_GPSR(IP0_28_27, A5),
844 PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
845 PINMUX_IPSR_GPSR(IP0_30_29, A6),
846 PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
847
848 /* IPSR1 */
849 PINMUX_IPSR_GPSR(IP1_1_0, A7),
850 PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
851 PINMUX_IPSR_GPSR(IP1_3_2, A8),
852 PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
853 PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
854 PINMUX_IPSR_GPSR(IP1_5_4, A9),
855 PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
856 PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
857 PINMUX_IPSR_GPSR(IP1_7_6, A10),
858 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
859 PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
860 PINMUX_IPSR_GPSR(IP1_10_8, A11),
861 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
862 PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
863 PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
864 PINMUX_IPSR_GPSR(IP1_13_11, A12),
865 PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
866 PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
867 PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
868 PINMUX_IPSR_GPSR(IP1_16_14, A13),
869 PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
870 PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
871 PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
872 PINMUX_IPSR_GPSR(IP1_19_17, A14),
873 PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
874 PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
875 PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
876 PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
877 PINMUX_IPSR_GPSR(IP1_22_20, A15),
878 PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
879 PINMUX_IPSR_GPSR(IP1_25_23, A16),
880 PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
881 PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
882 PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
883 PINMUX_IPSR_GPSR(IP1_28_26, A17),
884 PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
885 PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
886 PINMUX_IPSR_GPSR(IP1_31_29, A18),
887 PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
888 PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
889 PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
890
891 /* IPSR2 */
892 PINMUX_IPSR_GPSR(IP2_2_0, A19),
893 PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
894 PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
895 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
896 PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
897 PINMUX_IPSR_GPSR(IP2_2_0, A20),
898 PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
899 PINMUX_IPSR_GPSR(IP2_6_5, A21),
900 PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
901 PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
902 PINMUX_IPSR_GPSR(IP2_9_7, A22),
903 PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
904 PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
905 PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
906 PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
907 PINMUX_IPSR_GPSR(IP2_12_10, A23),
908 PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
909 PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
910 PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
911 PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
912 PINMUX_IPSR_GPSR(IP2_15_13, A24),
913 PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
914 PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
915 PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
916 PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
917 PINMUX_IPSR_GPSR(IP2_18_16, A25),
918 PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
919 PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
920 PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
921 PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
922 PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
923 PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
924 PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
925 PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
926 PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
927 PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
928 PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
929 PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
930 PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
931 PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
932 PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
933 PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
934 PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
935 PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
936 PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
937 PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
938 PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
939
940 /* IPSR3 */
941 PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
942 PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
943 PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
944 PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
945 PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
946 PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
947 PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
948 PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
949 PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
950 PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
951 PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
952 PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
953 PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
954 PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
955 PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
956 PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
957 PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
958 PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
959 PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
960 PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
961 PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
962 PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
963 PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
964 PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
965 PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
966 PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
967 PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
968 PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
969 PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
970 PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
971 PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
972 PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
973 PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
974 PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
975 PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
976 PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
977 PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
978 PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
979 PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
980 PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
981 PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
982 PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
983 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
984 PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
985 PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
986 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
987 PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
988 PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
989 PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
990 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
991 PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
992 PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
993 PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
994 PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
995 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
996 PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
997
998 /* IPSR4 */
999 PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
1000 PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
1001 PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
1002 PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
1003 PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
1004 PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
1005 PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
1006 PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
1007 PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
1008 PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
1009 PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
1010 PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
1011 PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
1012 PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
1013 PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
1014 PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
1015 PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
1016 PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
1017 PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
1018 PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
1019 PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
1020 PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1021 PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
1022 PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
1023 PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
1024 PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1025 PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
1026 PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1027 PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
1028 PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
1029 PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1030 PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
1031 PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
1032 PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
1033 PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
1034 PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
1035 PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
1036 PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1037 PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
1038 PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1039 PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
1040 PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1041 PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
1042 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1043 PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1044 PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
1045 PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1046 PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
1047
1048 /* IPSR5 */
1049 PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
1050 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1051 PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1052 PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
1053 PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1054 PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
1055 PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
1056 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1057 PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1058 PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
1059 PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1060 PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
1061 PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
1062 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1063 PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1064 PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
1065 PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1066 PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
1067 PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
1068 PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1069 PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1070 PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
1071 PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
1072 PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1073 PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1074 PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
1075 PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1076 PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1077 PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
1078 PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1079 PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
1080 PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1081 PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
1082 PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1083 PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
1084 PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1085 PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1086 PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
1087 PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1088 PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1089 PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
1090 PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1091 PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1092 PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
1093 PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1094 PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1095 PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1096 PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
1097 PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1098
1099 /* IPSR6 */
1100 PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1101 PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1102 PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1103 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1104 PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
1105 PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
1106 PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
1107 PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1108 PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1109 PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
1110 PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1111 PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
1112 PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
1113 PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1114 PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
1115 PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1116 PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
1117 PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1118 PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
1119 PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
1120 PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1121 PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
1122 PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
1123 PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1124 PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
1125 PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
1126 PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
1127 PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1128 PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
1129 PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
1130 PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1131 PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
1132 PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1133 PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
1134 PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
1135 PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1136 PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
1137 PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1138 PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
1139 PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1140 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1141 PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
1142 PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1143 PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
1144 PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1145 PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1146 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1147 PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1148 PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
1149 PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1150 PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1151 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1152 PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1153
1154 /* IPSR7 */
1155 PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
1156 PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1157 PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1158 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1159 PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1160 PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1161 PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
1162 PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
1163 PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1164 PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
1165 PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1166 PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1167 PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
1168 PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
1169 PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1170 PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
1171 PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1172 PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1173 PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
1174 PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
1175 PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1176 PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
1177 PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
1178 PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1179 PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
1180 PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
1181 PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1182 PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
1183 PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
1184 PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1185 PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
1186 PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
1187 PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1188 PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
1189 PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
1190 PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1191 PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
1192 PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
1193 PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1194 PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
1195 PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1196 PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1197 PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
1198 PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
1199 PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1200 PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
1201 PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1202 PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1203 PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
1204 PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
1205 PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1206 PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
1207 PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1208 PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1209
1210 /* IPSR8 */
1211 PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
1212 PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
1213 PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1214 PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1215 PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
1216 PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
1217 PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1218 PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1219 PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1220 PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1221 PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
1222 PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
1223 PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1224 PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1225 PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1226 PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1227 PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
1228 PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
1229 PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1230 PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1231 PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1232 PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
1233 PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
1234 PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1235 PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1236 PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1237 PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
1238 PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
1239 PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1240 PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
1241 PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1242 PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1243 PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
1244 PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
1245 PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1246 PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1248 PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1249 PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
1250 PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
1251 PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1252 PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
1253 PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1254 PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1255 PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
1256 PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
1257 PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1258 PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
1259 PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
1260 PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1261 PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1262 PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
1263 PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
1264 PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
1265 PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1266 PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1267
1268 /* IPSR9 */
1269 PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
1270 PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
1271 PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
1272 PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
1273 PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1274 PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
1275 PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
1276 PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
1277 PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1278 PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1279 PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1280 PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
1281 PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
1282 PINMUX_IPSR_GPSR(IP9_7, QCLK),
1283 PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
1284 PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
1285 PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1286 PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
1287 PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
1288 PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
1289 PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1290 PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
1291 PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1292 PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
1293 PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1294 PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
1295 PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1296 PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
1297 PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
1298 PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
1299 PINMUX_IPSR_GPSR(IP9_16, QPOLA),
1300 PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
1301 PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
1302 PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
1303 PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
1304 PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
1305 PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1306 PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1307 PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
1308 PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
1309 PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1310 PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1311 PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
1312 PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
1313 PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1314 PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1315 PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
1316 PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
1317 PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1318 PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1319 PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
1320 PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1321 PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1322 PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
1323 PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
1324 PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1325 PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
1326 PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1327 PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1328 PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
1329
1330 /* IPSR10 */
1331 PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
1332 PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
1333 PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1334 PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
1335 PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1336 PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1337 PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
1338 PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
1339 PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
1340 PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1341 PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
1342 PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1343 PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1344 PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
1345 PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
1346 PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
1347 PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1348 PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
1349 PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
1350 PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1351 PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
1352 PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
1353 PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
1354 PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1355 PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
1356 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1357 PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1358 PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
1359 PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
1360 PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1361 PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
1362 PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1363 PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1364 PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1365 PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
1366 PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
1367 PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
1368 PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
1369 PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
1370 PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
1371 PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
1372 PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
1373 PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1374 PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1375 PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
1376 PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
1377 PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
1378 PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1379 PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1380 PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
1381 PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
1382 PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
1383 PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1384 PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1385 PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
1386 PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
1387 PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1388 PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1389 PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
1390 PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
1391 PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1392 PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
1393 PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
1394
1395 /* IPSR11 */
1396 PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
1397 PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
1398 PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1399 PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
1400 PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
1401 PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
1402 PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
1403 PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1404 PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
1405 PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
1406 PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
1407 PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1408 PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
1409 PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1410 PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
1411 PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1412 PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1413 PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1414 PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
1415 PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1416 PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
1417 PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1418 PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1419 PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
1420 PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1421 PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
1422 PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1423 PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1424 PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
1425 PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1426 PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1427 PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
1428 PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1429 PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
1430 PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
1431 PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
1432 PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
1433 PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
1434 PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
1435 PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
1436 PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
1437 PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
1438 PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
1439 PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
1440 PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
1441 PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
1442 PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
1443 PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
1444 PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
1445 PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
1446 PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
1447 PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
1448 PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
1449 PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
1450 PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
1451 PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
1452 PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
1453
1454 /* IPSR12 */
1455 PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
1456 PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
1457 PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
1458 PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
1459 PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
1460 PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
1461 PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
1462 PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
1463 PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
1464 PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
1465 PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1466 PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
1467 PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1468 PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
1469 PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
1470 PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1471 PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
1472 PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1473 PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
1474 PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
1475 PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1476 PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1477 PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1478 PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
1479 PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
1480 PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1481 PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1482 PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1483 PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
1484 PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
1485 PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1486 PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1487 PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
1488 PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
1489 PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
1490 PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
1491 PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
1492 PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
1493 PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
1494 PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
1495 PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
1496 PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1497 PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
1498 PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1499 PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1500 PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1501 PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1502 PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
1503 PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1504 PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1505 PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1506
1507 /* IPSR13 */
1508 PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1509 PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
1510 PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1511 PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
1512 PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1513 PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1514 PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
1515 PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1516 PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1517 PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1518 PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
1519 PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1520 PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1521 PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1522 PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
1523 PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
1524 PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1525 PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1526 PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
1527 PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
1528 PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
1529 PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1530 PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
1531 PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
1532 PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
1533 PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
1534 PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
1535 PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
1536 PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
1537 PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
1538 PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
1539 PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1540 PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1541 PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1542 PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1543 PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
1544 PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
1545 PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1546 PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1547 PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1548 PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1549 PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
1550 PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
1551 PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
1552 PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
1553 PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1554 PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
1555 PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
1556 PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
1557 PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
1558 PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
1559 PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
1560 PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
1561 PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
1562 PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
1563 PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
1564
1565 /* IPSR14 */
1566 PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
1567 PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
1568 PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
1569 PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
1570 PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
1571 PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
1572 PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
1573 PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
1574 PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
1575 PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
1576 PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
1577 PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
1578 PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
1579 PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
1580 PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
1581 PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
1582 PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
1583 PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
1584 PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
1585 PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1586 PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
1587 PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
1588 PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
1589 PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
1590 PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1591 PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1592 PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
1593 PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
1594 PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1595 PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
1596 PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1597 PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
1598 PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1599 PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1600 PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
1601 PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1602 PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
1603 PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1604 PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
1605 PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1606 PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
1607 PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1608 PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
1609 PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1610 PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
1611 PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
1612 PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
1613 PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1614 PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
1615 PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
1616 PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1617 PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
1618 PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
1619 PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
1620 PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1621 PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
1622 PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
1623
1624 /* IPSR15 */
1625 PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
1626 PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
1627 PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1628 PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
1629 PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
1630 PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1631 PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
1632 PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
1633 PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1634 PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
1635 PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1636 PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1637 PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
1638 PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1639 PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1640 PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
1641 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1642 PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
1643 PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
1644 PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1645 PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
1646 PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
1647 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1648 PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
1649 PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
1650 PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1651 PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1652 PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1653 PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1654 PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
1655 PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1656 PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1657 PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1658 PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1659 PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1660 PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1661 PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1662 PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1663 PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1664 PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
1665 PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1666 PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
1667 PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1668 PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1669 PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1670 PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1671 PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
1672 PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1673 PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1674 PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1675 PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1676
1677 /* IPSR16 */
1678 PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
1679 PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1680 PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
1681 PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1682 PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1683 PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
1684 PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1685 PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
1686 PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1687 PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1688 PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1689 PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1690 PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
1691 PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1692 PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1693 PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
1694 PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
1695 PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1696 PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1697 PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
1698 PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
1699 PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1700 };
1701
1702 static const struct sh_pfc_pin pinmux_pins[] = {
1703 PINMUX_GPIO_GP_ALL(),
1704 };
1705
1706 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
1707 /* - ADI -------------------------------------------------------------------- */
1708 static const unsigned int adi_common_pins[] = {
1709 /* ADIDATA, ADICS/SAMP, ADICLK */
1710 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
1711 };
1712 static const unsigned int adi_common_mux[] = {
1713 /* ADIDATA, ADICS/SAMP, ADICLK */
1714 ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
1715 };
1716 static const unsigned int adi_chsel0_pins[] = {
1717 /* ADICHS 0 */
1718 RCAR_GP_PIN(6, 27),
1719 };
1720 static const unsigned int adi_chsel0_mux[] = {
1721 /* ADICHS 0 */
1722 ADICHS0_MARK,
1723 };
1724 static const unsigned int adi_chsel1_pins[] = {
1725 /* ADICHS 1 */
1726 RCAR_GP_PIN(6, 28),
1727 };
1728 static const unsigned int adi_chsel1_mux[] = {
1729 /* ADICHS 1 */
1730 ADICHS1_MARK,
1731 };
1732 static const unsigned int adi_chsel2_pins[] = {
1733 /* ADICHS 2 */
1734 RCAR_GP_PIN(6, 29),
1735 };
1736 static const unsigned int adi_chsel2_mux[] = {
1737 /* ADICHS 2 */
1738 ADICHS2_MARK,
1739 };
1740 static const unsigned int adi_common_b_pins[] = {
1741 /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1742 RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1743 };
1744 static const unsigned int adi_common_b_mux[] = {
1745 /* ADIDATA B, ADICS/SAMP B, ADICLK B */
1746 ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
1747 };
1748 static const unsigned int adi_chsel0_b_pins[] = {
1749 /* ADICHS B 0 */
1750 RCAR_GP_PIN(5, 28),
1751 };
1752 static const unsigned int adi_chsel0_b_mux[] = {
1753 /* ADICHS B 0 */
1754 ADICHS0_B_MARK,
1755 };
1756 static const unsigned int adi_chsel1_b_pins[] = {
1757 /* ADICHS B 1 */
1758 RCAR_GP_PIN(5, 29),
1759 };
1760 static const unsigned int adi_chsel1_b_mux[] = {
1761 /* ADICHS B 1 */
1762 ADICHS1_B_MARK,
1763 };
1764 static const unsigned int adi_chsel2_b_pins[] = {
1765 /* ADICHS B 2 */
1766 RCAR_GP_PIN(5, 30),
1767 };
1768 static const unsigned int adi_chsel2_b_mux[] = {
1769 /* ADICHS B 2 */
1770 ADICHS2_B_MARK,
1771 };
1772 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
1773
1774 /* - Audio Clock ------------------------------------------------------------ */
1775 static const unsigned int audio_clk_a_pins[] = {
1776 /* CLK */
1777 RCAR_GP_PIN(2, 28),
1778 };
1779
1780 static const unsigned int audio_clk_a_mux[] = {
1781 AUDIO_CLKA_MARK,
1782 };
1783
1784 static const unsigned int audio_clk_b_pins[] = {
1785 /* CLK */
1786 RCAR_GP_PIN(2, 29),
1787 };
1788
1789 static const unsigned int audio_clk_b_mux[] = {
1790 AUDIO_CLKB_MARK,
1791 };
1792
1793 static const unsigned int audio_clk_b_b_pins[] = {
1794 /* CLK */
1795 RCAR_GP_PIN(7, 20),
1796 };
1797
1798 static const unsigned int audio_clk_b_b_mux[] = {
1799 AUDIO_CLKB_B_MARK,
1800 };
1801
1802 static const unsigned int audio_clk_c_pins[] = {
1803 /* CLK */
1804 RCAR_GP_PIN(2, 30),
1805 };
1806
1807 static const unsigned int audio_clk_c_mux[] = {
1808 AUDIO_CLKC_MARK,
1809 };
1810
1811 static const unsigned int audio_clkout_pins[] = {
1812 /* CLK */
1813 RCAR_GP_PIN(2, 31),
1814 };
1815
1816 static const unsigned int audio_clkout_mux[] = {
1817 AUDIO_CLKOUT_MARK,
1818 };
1819
1820 /* - AVB -------------------------------------------------------------------- */
1821 static const unsigned int avb_link_pins[] = {
1822 RCAR_GP_PIN(5, 14),
1823 };
1824 static const unsigned int avb_link_mux[] = {
1825 AVB_LINK_MARK,
1826 };
1827 static const unsigned int avb_magic_pins[] = {
1828 RCAR_GP_PIN(5, 11),
1829 };
1830 static const unsigned int avb_magic_mux[] = {
1831 AVB_MAGIC_MARK,
1832 };
1833 static const unsigned int avb_phy_int_pins[] = {
1834 RCAR_GP_PIN(5, 16),
1835 };
1836 static const unsigned int avb_phy_int_mux[] = {
1837 AVB_PHY_INT_MARK,
1838 };
1839 static const unsigned int avb_mdio_pins[] = {
1840 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
1841 };
1842 static const unsigned int avb_mdio_mux[] = {
1843 AVB_MDC_MARK, AVB_MDIO_MARK,
1844 };
1845 static const unsigned int avb_mii_pins[] = {
1846 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1847 RCAR_GP_PIN(5, 21),
1848
1849 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1850 RCAR_GP_PIN(5, 3),
1851
1852 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1853 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
1854 RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
1855 };
1856 static const unsigned int avb_mii_mux[] = {
1857 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1858 AVB_TXD3_MARK,
1859
1860 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1861 AVB_RXD3_MARK,
1862
1863 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1864 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1865 AVB_TX_CLK_MARK, AVB_COL_MARK,
1866 };
1867 static const unsigned int avb_gmii_pins[] = {
1868 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
1869 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1870 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1871
1872 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1873 RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
1874 RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
1875
1876 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
1877 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
1878 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
1879 RCAR_GP_PIN(5, 29),
1880 };
1881 static const unsigned int avb_gmii_mux[] = {
1882 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1883 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1884 AVB_TXD6_MARK, AVB_TXD7_MARK,
1885
1886 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1887 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1888 AVB_RXD6_MARK, AVB_RXD7_MARK,
1889
1890 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1891 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1892 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1893 AVB_COL_MARK,
1894 };
1895
1896 /* - CAN -------------------------------------------------------------------- */
1897
1898 static const unsigned int can0_data_pins[] = {
1899 /* TX, RX */
1900 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1901 };
1902
1903 static const unsigned int can0_data_mux[] = {
1904 CAN0_TX_MARK, CAN0_RX_MARK,
1905 };
1906
1907 static const unsigned int can0_data_b_pins[] = {
1908 /* TX, RX */
1909 RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
1910 };
1911
1912 static const unsigned int can0_data_b_mux[] = {
1913 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1914 };
1915
1916 static const unsigned int can0_data_c_pins[] = {
1917 /* TX, RX */
1918 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1919 };
1920
1921 static const unsigned int can0_data_c_mux[] = {
1922 CAN0_TX_C_MARK, CAN0_RX_C_MARK,
1923 };
1924
1925 static const unsigned int can0_data_d_pins[] = {
1926 /* TX, RX */
1927 RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
1928 };
1929
1930 static const unsigned int can0_data_d_mux[] = {
1931 CAN0_TX_D_MARK, CAN0_RX_D_MARK,
1932 };
1933
1934 static const unsigned int can0_data_e_pins[] = {
1935 /* TX, RX */
1936 RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
1937 };
1938
1939 static const unsigned int can0_data_e_mux[] = {
1940 CAN0_TX_E_MARK, CAN0_RX_E_MARK,
1941 };
1942
1943 static const unsigned int can0_data_f_pins[] = {
1944 /* TX, RX */
1945 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1946 };
1947
1948 static const unsigned int can0_data_f_mux[] = {
1949 CAN0_TX_F_MARK, CAN0_RX_F_MARK,
1950 };
1951
1952 static const unsigned int can1_data_pins[] = {
1953 /* TX, RX */
1954 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
1955 };
1956
1957 static const unsigned int can1_data_mux[] = {
1958 CAN1_TX_MARK, CAN1_RX_MARK,
1959 };
1960
1961 static const unsigned int can1_data_b_pins[] = {
1962 /* TX, RX */
1963 RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
1964 };
1965
1966 static const unsigned int can1_data_b_mux[] = {
1967 CAN1_TX_B_MARK, CAN1_RX_B_MARK,
1968 };
1969
1970 static const unsigned int can1_data_c_pins[] = {
1971 /* TX, RX */
1972 RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
1973 };
1974
1975 static const unsigned int can1_data_c_mux[] = {
1976 CAN1_TX_C_MARK, CAN1_RX_C_MARK,
1977 };
1978
1979 static const unsigned int can1_data_d_pins[] = {
1980 /* TX, RX */
1981 RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
1982 };
1983
1984 static const unsigned int can1_data_d_mux[] = {
1985 CAN1_TX_D_MARK, CAN1_RX_D_MARK,
1986 };
1987
1988 static const unsigned int can_clk_pins[] = {
1989 /* CLK */
1990 RCAR_GP_PIN(7, 2),
1991 };
1992
1993 static const unsigned int can_clk_mux[] = {
1994 CAN_CLK_MARK,
1995 };
1996
1997 static const unsigned int can_clk_b_pins[] = {
1998 /* CLK */
1999 RCAR_GP_PIN(5, 21),
2000 };
2001
2002 static const unsigned int can_clk_b_mux[] = {
2003 CAN_CLK_B_MARK,
2004 };
2005
2006 static const unsigned int can_clk_c_pins[] = {
2007 /* CLK */
2008 RCAR_GP_PIN(4, 30),
2009 };
2010
2011 static const unsigned int can_clk_c_mux[] = {
2012 CAN_CLK_C_MARK,
2013 };
2014
2015 static const unsigned int can_clk_d_pins[] = {
2016 /* CLK */
2017 RCAR_GP_PIN(7, 19),
2018 };
2019
2020 static const unsigned int can_clk_d_mux[] = {
2021 CAN_CLK_D_MARK,
2022 };
2023
2024 /* - DU --------------------------------------------------------------------- */
2025 static const unsigned int du_rgb666_pins[] = {
2026 /* R[7:2], G[7:2], B[7:2] */
2027 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2028 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2029 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2030 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2031 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2032 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2033 };
2034 static const unsigned int du_rgb666_mux[] = {
2035 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2036 DU1_DR3_MARK, DU1_DR2_MARK,
2037 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2038 DU1_DG3_MARK, DU1_DG2_MARK,
2039 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2040 DU1_DB3_MARK, DU1_DB2_MARK,
2041 };
2042 static const unsigned int du_rgb888_pins[] = {
2043 /* R[7:0], G[7:0], B[7:0] */
2044 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
2045 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
2046 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2047 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2048 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
2049 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2050 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2051 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
2052 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2053 };
2054 static const unsigned int du_rgb888_mux[] = {
2055 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
2056 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
2057 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
2058 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
2059 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
2060 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
2061 };
2062 static const unsigned int du_clk_out_0_pins[] = {
2063 /* CLKOUT */
2064 RCAR_GP_PIN(3, 25),
2065 };
2066 static const unsigned int du_clk_out_0_mux[] = {
2067 DU1_DOTCLKOUT0_MARK
2068 };
2069 static const unsigned int du_clk_out_1_pins[] = {
2070 /* CLKOUT */
2071 RCAR_GP_PIN(3, 26),
2072 };
2073 static const unsigned int du_clk_out_1_mux[] = {
2074 DU1_DOTCLKOUT1_MARK
2075 };
2076 static const unsigned int du_sync_pins[] = {
2077 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2078 RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
2079 };
2080 static const unsigned int du_sync_mux[] = {
2081 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
2082 };
2083 static const unsigned int du_oddf_pins[] = {
2084 /* EXDISP/EXODDF/EXCDE */
2085 RCAR_GP_PIN(3, 29),
2086 };
2087 static const unsigned int du_oddf_mux[] = {
2088 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
2089 };
2090 static const unsigned int du_cde_pins[] = {
2091 /* CDE */
2092 RCAR_GP_PIN(3, 31),
2093 };
2094 static const unsigned int du_cde_mux[] = {
2095 DU1_CDE_MARK,
2096 };
2097 static const unsigned int du_disp_pins[] = {
2098 /* DISP */
2099 RCAR_GP_PIN(3, 30),
2100 };
2101 static const unsigned int du_disp_mux[] = {
2102 DU1_DISP_MARK,
2103 };
2104 static const unsigned int du0_clk_in_pins[] = {
2105 /* CLKIN */
2106 RCAR_GP_PIN(6, 31),
2107 };
2108 static const unsigned int du0_clk_in_mux[] = {
2109 DU0_DOTCLKIN_MARK
2110 };
2111 static const unsigned int du1_clk_in_pins[] = {
2112 /* CLKIN */
2113 RCAR_GP_PIN(3, 24),
2114 };
2115 static const unsigned int du1_clk_in_mux[] = {
2116 DU1_DOTCLKIN_MARK
2117 };
2118 static const unsigned int du1_clk_in_b_pins[] = {
2119 /* CLKIN */
2120 RCAR_GP_PIN(7, 19),
2121 };
2122 static const unsigned int du1_clk_in_b_mux[] = {
2123 DU1_DOTCLKIN_B_MARK,
2124 };
2125 static const unsigned int du1_clk_in_c_pins[] = {
2126 /* CLKIN */
2127 RCAR_GP_PIN(7, 20),
2128 };
2129 static const unsigned int du1_clk_in_c_mux[] = {
2130 DU1_DOTCLKIN_C_MARK,
2131 };
2132 /* - ETH -------------------------------------------------------------------- */
2133 static const unsigned int eth_link_pins[] = {
2134 /* LINK */
2135 RCAR_GP_PIN(5, 18),
2136 };
2137 static const unsigned int eth_link_mux[] = {
2138 ETH_LINK_MARK,
2139 };
2140 static const unsigned int eth_magic_pins[] = {
2141 /* MAGIC */
2142 RCAR_GP_PIN(5, 22),
2143 };
2144 static const unsigned int eth_magic_mux[] = {
2145 ETH_MAGIC_MARK,
2146 };
2147 static const unsigned int eth_mdio_pins[] = {
2148 /* MDC, MDIO */
2149 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
2150 };
2151 static const unsigned int eth_mdio_mux[] = {
2152 ETH_MDC_MARK, ETH_MDIO_MARK,
2153 };
2154 static const unsigned int eth_rmii_pins[] = {
2155 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
2156 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
2157 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
2158 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
2159 };
2160 static const unsigned int eth_rmii_mux[] = {
2161 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2162 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
2163 };
2164
2165 /* - HSCIF0 ----------------------------------------------------------------- */
2166 static const unsigned int hscif0_data_pins[] = {
2167 /* RX, TX */
2168 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2169 };
2170 static const unsigned int hscif0_data_mux[] = {
2171 HRX0_MARK, HTX0_MARK,
2172 };
2173 static const unsigned int hscif0_clk_pins[] = {
2174 /* SCK */
2175 RCAR_GP_PIN(7, 2),
2176 };
2177 static const unsigned int hscif0_clk_mux[] = {
2178 HSCK0_MARK,
2179 };
2180 static const unsigned int hscif0_ctrl_pins[] = {
2181 /* RTS, CTS */
2182 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2183 };
2184 static const unsigned int hscif0_ctrl_mux[] = {
2185 HRTS0_N_MARK, HCTS0_N_MARK,
2186 };
2187 static const unsigned int hscif0_data_b_pins[] = {
2188 /* RX, TX */
2189 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
2190 };
2191 static const unsigned int hscif0_data_b_mux[] = {
2192 HRX0_B_MARK, HTX0_B_MARK,
2193 };
2194 static const unsigned int hscif0_ctrl_b_pins[] = {
2195 /* RTS, CTS */
2196 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
2197 };
2198 static const unsigned int hscif0_ctrl_b_mux[] = {
2199 HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2200 };
2201 static const unsigned int hscif0_data_c_pins[] = {
2202 /* RX, TX */
2203 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2204 };
2205 static const unsigned int hscif0_data_c_mux[] = {
2206 HRX0_C_MARK, HTX0_C_MARK,
2207 };
2208 static const unsigned int hscif0_clk_c_pins[] = {
2209 /* SCK */
2210 RCAR_GP_PIN(5, 31),
2211 };
2212 static const unsigned int hscif0_clk_c_mux[] = {
2213 HSCK0_C_MARK,
2214 };
2215 /* - HSCIF1 ----------------------------------------------------------------- */
2216 static const unsigned int hscif1_data_pins[] = {
2217 /* RX, TX */
2218 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2219 };
2220 static const unsigned int hscif1_data_mux[] = {
2221 HRX1_MARK, HTX1_MARK,
2222 };
2223 static const unsigned int hscif1_clk_pins[] = {
2224 /* SCK */
2225 RCAR_GP_PIN(7, 7),
2226 };
2227 static const unsigned int hscif1_clk_mux[] = {
2228 HSCK1_MARK,
2229 };
2230 static const unsigned int hscif1_ctrl_pins[] = {
2231 /* RTS, CTS */
2232 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2233 };
2234 static const unsigned int hscif1_ctrl_mux[] = {
2235 HRTS1_N_MARK, HCTS1_N_MARK,
2236 };
2237 static const unsigned int hscif1_data_b_pins[] = {
2238 /* RX, TX */
2239 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2240 };
2241 static const unsigned int hscif1_data_b_mux[] = {
2242 HRX1_B_MARK, HTX1_B_MARK,
2243 };
2244 static const unsigned int hscif1_data_c_pins[] = {
2245 /* RX, TX */
2246 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2247 };
2248 static const unsigned int hscif1_data_c_mux[] = {
2249 HRX1_C_MARK, HTX1_C_MARK,
2250 };
2251 static const unsigned int hscif1_clk_c_pins[] = {
2252 /* SCK */
2253 RCAR_GP_PIN(7, 16),
2254 };
2255 static const unsigned int hscif1_clk_c_mux[] = {
2256 HSCK1_C_MARK,
2257 };
2258 static const unsigned int hscif1_ctrl_c_pins[] = {
2259 /* RTS, CTS */
2260 RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
2261 };
2262 static const unsigned int hscif1_ctrl_c_mux[] = {
2263 HRTS1_N_C_MARK, HCTS1_N_C_MARK,
2264 };
2265 static const unsigned int hscif1_data_d_pins[] = {
2266 /* RX, TX */
2267 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2268 };
2269 static const unsigned int hscif1_data_d_mux[] = {
2270 HRX1_D_MARK, HTX1_D_MARK,
2271 };
2272 static const unsigned int hscif1_data_e_pins[] = {
2273 /* RX, TX */
2274 RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
2275 };
2276 static const unsigned int hscif1_data_e_mux[] = {
2277 HRX1_C_MARK, HTX1_C_MARK,
2278 };
2279 static const unsigned int hscif1_clk_e_pins[] = {
2280 /* SCK */
2281 RCAR_GP_PIN(2, 6),
2282 };
2283 static const unsigned int hscif1_clk_e_mux[] = {
2284 HSCK1_E_MARK,
2285 };
2286 static const unsigned int hscif1_ctrl_e_pins[] = {
2287 /* RTS, CTS */
2288 RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
2289 };
2290 static const unsigned int hscif1_ctrl_e_mux[] = {
2291 HRTS1_N_E_MARK, HCTS1_N_E_MARK,
2292 };
2293 /* - HSCIF2 ----------------------------------------------------------------- */
2294 static const unsigned int hscif2_data_pins[] = {
2295 /* RX, TX */
2296 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2297 };
2298 static const unsigned int hscif2_data_mux[] = {
2299 HRX2_MARK, HTX2_MARK,
2300 };
2301 static const unsigned int hscif2_clk_pins[] = {
2302 /* SCK */
2303 RCAR_GP_PIN(4, 15),
2304 };
2305 static const unsigned int hscif2_clk_mux[] = {
2306 HSCK2_MARK,
2307 };
2308 static const unsigned int hscif2_ctrl_pins[] = {
2309 /* RTS, CTS */
2310 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2311 };
2312 static const unsigned int hscif2_ctrl_mux[] = {
2313 HRTS2_N_MARK, HCTS2_N_MARK,
2314 };
2315 static const unsigned int hscif2_data_b_pins[] = {
2316 /* RX, TX */
2317 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
2318 };
2319 static const unsigned int hscif2_data_b_mux[] = {
2320 HRX2_B_MARK, HTX2_B_MARK,
2321 };
2322 static const unsigned int hscif2_ctrl_b_pins[] = {
2323 /* RTS, CTS */
2324 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
2325 };
2326 static const unsigned int hscif2_ctrl_b_mux[] = {
2327 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2328 };
2329 static const unsigned int hscif2_data_c_pins[] = {
2330 /* RX, TX */
2331 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2332 };
2333 static const unsigned int hscif2_data_c_mux[] = {
2334 HRX2_C_MARK, HTX2_C_MARK,
2335 };
2336 static const unsigned int hscif2_clk_c_pins[] = {
2337 /* SCK */
2338 RCAR_GP_PIN(5, 31),
2339 };
2340 static const unsigned int hscif2_clk_c_mux[] = {
2341 HSCK2_C_MARK,
2342 };
2343 static const unsigned int hscif2_data_d_pins[] = {
2344 /* RX, TX */
2345 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
2346 };
2347 static const unsigned int hscif2_data_d_mux[] = {
2348 HRX2_B_MARK, HTX2_D_MARK,
2349 };
2350 /* - I2C0 ------------------------------------------------------------------- */
2351 static const unsigned int i2c0_pins[] = {
2352 /* SCL, SDA */
2353 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2354 };
2355 static const unsigned int i2c0_mux[] = {
2356 I2C0_SCL_MARK, I2C0_SDA_MARK,
2357 };
2358 static const unsigned int i2c0_b_pins[] = {
2359 /* SCL, SDA */
2360 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2361 };
2362 static const unsigned int i2c0_b_mux[] = {
2363 I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
2364 };
2365 static const unsigned int i2c0_c_pins[] = {
2366 /* SCL, SDA */
2367 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
2368 };
2369 static const unsigned int i2c0_c_mux[] = {
2370 I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
2371 };
2372 /* - I2C1 ------------------------------------------------------------------- */
2373 static const unsigned int i2c1_pins[] = {
2374 /* SCL, SDA */
2375 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
2376 };
2377 static const unsigned int i2c1_mux[] = {
2378 I2C1_SCL_MARK, I2C1_SDA_MARK,
2379 };
2380 static const unsigned int i2c1_b_pins[] = {
2381 /* SCL, SDA */
2382 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2383 };
2384 static const unsigned int i2c1_b_mux[] = {
2385 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2386 };
2387 static const unsigned int i2c1_c_pins[] = {
2388 /* SCL, SDA */
2389 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
2390 };
2391 static const unsigned int i2c1_c_mux[] = {
2392 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2393 };
2394 static const unsigned int i2c1_d_pins[] = {
2395 /* SCL, SDA */
2396 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2397 };
2398 static const unsigned int i2c1_d_mux[] = {
2399 I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
2400 };
2401 static const unsigned int i2c1_e_pins[] = {
2402 /* SCL, SDA */
2403 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
2404 };
2405 static const unsigned int i2c1_e_mux[] = {
2406 I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
2407 };
2408 /* - I2C2 ------------------------------------------------------------------- */
2409 static const unsigned int i2c2_pins[] = {
2410 /* SCL, SDA */
2411 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
2412 };
2413 static const unsigned int i2c2_mux[] = {
2414 I2C2_SCL_MARK, I2C2_SDA_MARK,
2415 };
2416 static const unsigned int i2c2_b_pins[] = {
2417 /* SCL, SDA */
2418 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
2419 };
2420 static const unsigned int i2c2_b_mux[] = {
2421 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2422 };
2423 static const unsigned int i2c2_c_pins[] = {
2424 /* SCL, SDA */
2425 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2426 };
2427 static const unsigned int i2c2_c_mux[] = {
2428 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2429 };
2430 static const unsigned int i2c2_d_pins[] = {
2431 /* SCL, SDA */
2432 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
2433 };
2434 static const unsigned int i2c2_d_mux[] = {
2435 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2436 };
2437 /* - I2C3 ------------------------------------------------------------------- */
2438 static const unsigned int i2c3_pins[] = {
2439 /* SCL, SDA */
2440 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2441 };
2442 static const unsigned int i2c3_mux[] = {
2443 I2C3_SCL_MARK, I2C3_SDA_MARK,
2444 };
2445 static const unsigned int i2c3_b_pins[] = {
2446 /* SCL, SDA */
2447 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2448 };
2449 static const unsigned int i2c3_b_mux[] = {
2450 I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
2451 };
2452 static const unsigned int i2c3_c_pins[] = {
2453 /* SCL, SDA */
2454 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2455 };
2456 static const unsigned int i2c3_c_mux[] = {
2457 I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
2458 };
2459 static const unsigned int i2c3_d_pins[] = {
2460 /* SCL, SDA */
2461 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
2462 };
2463 static const unsigned int i2c3_d_mux[] = {
2464 I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
2465 };
2466 /* - I2C4 ------------------------------------------------------------------- */
2467 static const unsigned int i2c4_pins[] = {
2468 /* SCL, SDA */
2469 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2470 };
2471 static const unsigned int i2c4_mux[] = {
2472 I2C4_SCL_MARK, I2C4_SDA_MARK,
2473 };
2474 static const unsigned int i2c4_b_pins[] = {
2475 /* SCL, SDA */
2476 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2477 };
2478 static const unsigned int i2c4_b_mux[] = {
2479 I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2480 };
2481 static const unsigned int i2c4_c_pins[] = {
2482 /* SCL, SDA */
2483 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
2484 };
2485 static const unsigned int i2c4_c_mux[] = {
2486 I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2487 };
2488 /* - I2C7 ------------------------------------------------------------------- */
2489 static const unsigned int i2c7_pins[] = {
2490 /* SCL, SDA */
2491 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2492 };
2493 static const unsigned int i2c7_mux[] = {
2494 IIC0_SCL_MARK, IIC0_SDA_MARK,
2495 };
2496 static const unsigned int i2c7_b_pins[] = {
2497 /* SCL, SDA */
2498 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
2499 };
2500 static const unsigned int i2c7_b_mux[] = {
2501 IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
2502 };
2503 static const unsigned int i2c7_c_pins[] = {
2504 /* SCL, SDA */
2505 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2506 };
2507 static const unsigned int i2c7_c_mux[] = {
2508 IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
2509 };
2510 /* - I2C8 ------------------------------------------------------------------- */
2511 static const unsigned int i2c8_pins[] = {
2512 /* SCL, SDA */
2513 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2514 };
2515 static const unsigned int i2c8_mux[] = {
2516 IIC1_SCL_MARK, IIC1_SDA_MARK,
2517 };
2518 static const unsigned int i2c8_b_pins[] = {
2519 /* SCL, SDA */
2520 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
2521 };
2522 static const unsigned int i2c8_b_mux[] = {
2523 IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2524 };
2525 static const unsigned int i2c8_c_pins[] = {
2526 /* SCL, SDA */
2527 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2528 };
2529 static const unsigned int i2c8_c_mux[] = {
2530 IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2531 };
2532 /* - INTC ------------------------------------------------------------------- */
2533 static const unsigned int intc_irq0_pins[] = {
2534 /* IRQ */
2535 RCAR_GP_PIN(7, 10),
2536 };
2537 static const unsigned int intc_irq0_mux[] = {
2538 IRQ0_MARK,
2539 };
2540 static const unsigned int intc_irq1_pins[] = {
2541 /* IRQ */
2542 RCAR_GP_PIN(7, 11),
2543 };
2544 static const unsigned int intc_irq1_mux[] = {
2545 IRQ1_MARK,
2546 };
2547 static const unsigned int intc_irq2_pins[] = {
2548 /* IRQ */
2549 RCAR_GP_PIN(7, 12),
2550 };
2551 static const unsigned int intc_irq2_mux[] = {
2552 IRQ2_MARK,
2553 };
2554 static const unsigned int intc_irq3_pins[] = {
2555 /* IRQ */
2556 RCAR_GP_PIN(7, 13),
2557 };
2558 static const unsigned int intc_irq3_mux[] = {
2559 IRQ3_MARK,
2560 };
2561
2562 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
2563 /* - MLB+ ------------------------------------------------------------------- */
2564 static const unsigned int mlb_3pin_pins[] = {
2565 RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
2566 };
2567 static const unsigned int mlb_3pin_mux[] = {
2568 MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2569 };
2570 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
2571
2572 /* - MMCIF ------------------------------------------------------------------ */
2573 static const unsigned int mmc_data1_pins[] = {
2574 /* D[0] */
2575 RCAR_GP_PIN(6, 18),
2576 };
2577 static const unsigned int mmc_data1_mux[] = {
2578 MMC_D0_MARK,
2579 };
2580 static const unsigned int mmc_data4_pins[] = {
2581 /* D[0:3] */
2582 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2583 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2584 };
2585 static const unsigned int mmc_data4_mux[] = {
2586 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2587 };
2588 static const unsigned int mmc_data8_pins[] = {
2589 /* D[0:7] */
2590 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2591 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2592 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2593 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2594 };
2595 static const unsigned int mmc_data8_mux[] = {
2596 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2597 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2598 };
2599 static const unsigned int mmc_data8_b_pins[] = {
2600 /* D[0:7] */
2601 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2602 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2603 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2604 RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
2605 };
2606 static const unsigned int mmc_data8_b_mux[] = {
2607 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2608 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
2609 };
2610 static const unsigned int mmc_ctrl_pins[] = {
2611 /* CLK, CMD */
2612 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2613 };
2614 static const unsigned int mmc_ctrl_mux[] = {
2615 MMC_CLK_MARK, MMC_CMD_MARK,
2616 };
2617 /* - MSIOF0 ----------------------------------------------------------------- */
2618 static const unsigned int msiof0_clk_pins[] = {
2619 /* SCK */
2620 RCAR_GP_PIN(6, 24),
2621 };
2622 static const unsigned int msiof0_clk_mux[] = {
2623 MSIOF0_SCK_MARK,
2624 };
2625 static const unsigned int msiof0_sync_pins[] = {
2626 /* SYNC */
2627 RCAR_GP_PIN(6, 25),
2628 };
2629 static const unsigned int msiof0_sync_mux[] = {
2630 MSIOF0_SYNC_MARK,
2631 };
2632 static const unsigned int msiof0_ss1_pins[] = {
2633 /* SS1 */
2634 RCAR_GP_PIN(6, 28),
2635 };
2636 static const unsigned int msiof0_ss1_mux[] = {
2637 MSIOF0_SS1_MARK,
2638 };
2639 static const unsigned int msiof0_ss2_pins[] = {
2640 /* SS2 */
2641 RCAR_GP_PIN(6, 29),
2642 };
2643 static const unsigned int msiof0_ss2_mux[] = {
2644 MSIOF0_SS2_MARK,
2645 };
2646 static const unsigned int msiof0_rx_pins[] = {
2647 /* RXD */
2648 RCAR_GP_PIN(6, 27),
2649 };
2650 static const unsigned int msiof0_rx_mux[] = {
2651 MSIOF0_RXD_MARK,
2652 };
2653 static const unsigned int msiof0_tx_pins[] = {
2654 /* TXD */
2655 RCAR_GP_PIN(6, 26),
2656 };
2657 static const unsigned int msiof0_tx_mux[] = {
2658 MSIOF0_TXD_MARK,
2659 };
2660
2661 static const unsigned int msiof0_clk_b_pins[] = {
2662 /* SCK */
2663 RCAR_GP_PIN(0, 16),
2664 };
2665 static const unsigned int msiof0_clk_b_mux[] = {
2666 MSIOF0_SCK_B_MARK,
2667 };
2668 static const unsigned int msiof0_sync_b_pins[] = {
2669 /* SYNC */
2670 RCAR_GP_PIN(0, 17),
2671 };
2672 static const unsigned int msiof0_sync_b_mux[] = {
2673 MSIOF0_SYNC_B_MARK,
2674 };
2675 static const unsigned int msiof0_ss1_b_pins[] = {
2676 /* SS1 */
2677 RCAR_GP_PIN(0, 18),
2678 };
2679 static const unsigned int msiof0_ss1_b_mux[] = {
2680 MSIOF0_SS1_B_MARK,
2681 };
2682 static const unsigned int msiof0_ss2_b_pins[] = {
2683 /* SS2 */
2684 RCAR_GP_PIN(0, 19),
2685 };
2686 static const unsigned int msiof0_ss2_b_mux[] = {
2687 MSIOF0_SS2_B_MARK,
2688 };
2689 static const unsigned int msiof0_rx_b_pins[] = {
2690 /* RXD */
2691 RCAR_GP_PIN(0, 21),
2692 };
2693 static const unsigned int msiof0_rx_b_mux[] = {
2694 MSIOF0_RXD_B_MARK,
2695 };
2696 static const unsigned int msiof0_tx_b_pins[] = {
2697 /* TXD */
2698 RCAR_GP_PIN(0, 20),
2699 };
2700 static const unsigned int msiof0_tx_b_mux[] = {
2701 MSIOF0_TXD_B_MARK,
2702 };
2703
2704 static const unsigned int msiof0_clk_c_pins[] = {
2705 /* SCK */
2706 RCAR_GP_PIN(5, 26),
2707 };
2708 static const unsigned int msiof0_clk_c_mux[] = {
2709 MSIOF0_SCK_C_MARK,
2710 };
2711 static const unsigned int msiof0_sync_c_pins[] = {
2712 /* SYNC */
2713 RCAR_GP_PIN(5, 25),
2714 };
2715 static const unsigned int msiof0_sync_c_mux[] = {
2716 MSIOF0_SYNC_C_MARK,
2717 };
2718 static const unsigned int msiof0_ss1_c_pins[] = {
2719 /* SS1 */
2720 RCAR_GP_PIN(5, 27),
2721 };
2722 static const unsigned int msiof0_ss1_c_mux[] = {
2723 MSIOF0_SS1_C_MARK,
2724 };
2725 static const unsigned int msiof0_ss2_c_pins[] = {
2726 /* SS2 */
2727 RCAR_GP_PIN(5, 28),
2728 };
2729 static const unsigned int msiof0_ss2_c_mux[] = {
2730 MSIOF0_SS2_C_MARK,
2731 };
2732 static const unsigned int msiof0_rx_c_pins[] = {
2733 /* RXD */
2734 RCAR_GP_PIN(5, 29),
2735 };
2736 static const unsigned int msiof0_rx_c_mux[] = {
2737 MSIOF0_RXD_C_MARK,
2738 };
2739 static const unsigned int msiof0_tx_c_pins[] = {
2740 /* TXD */
2741 RCAR_GP_PIN(5, 30),
2742 };
2743 static const unsigned int msiof0_tx_c_mux[] = {
2744 MSIOF0_TXD_C_MARK,
2745 };
2746 /* - MSIOF1 ----------------------------------------------------------------- */
2747 static const unsigned int msiof1_clk_pins[] = {
2748 /* SCK */
2749 RCAR_GP_PIN(0, 22),
2750 };
2751 static const unsigned int msiof1_clk_mux[] = {
2752 MSIOF1_SCK_MARK,
2753 };
2754 static const unsigned int msiof1_sync_pins[] = {
2755 /* SYNC */
2756 RCAR_GP_PIN(0, 23),
2757 };
2758 static const unsigned int msiof1_sync_mux[] = {
2759 MSIOF1_SYNC_MARK,
2760 };
2761 static const unsigned int msiof1_ss1_pins[] = {
2762 /* SS1 */
2763 RCAR_GP_PIN(0, 24),
2764 };
2765 static const unsigned int msiof1_ss1_mux[] = {
2766 MSIOF1_SS1_MARK,
2767 };
2768 static const unsigned int msiof1_ss2_pins[] = {
2769 /* SS2 */
2770 RCAR_GP_PIN(0, 25),
2771 };
2772 static const unsigned int msiof1_ss2_mux[] = {
2773 MSIOF1_SS2_MARK,
2774 };
2775 static const unsigned int msiof1_rx_pins[] = {
2776 /* RXD */
2777 RCAR_GP_PIN(0, 27),
2778 };
2779 static const unsigned int msiof1_rx_mux[] = {
2780 MSIOF1_RXD_MARK,
2781 };
2782 static const unsigned int msiof1_tx_pins[] = {
2783 /* TXD */
2784 RCAR_GP_PIN(0, 26),
2785 };
2786 static const unsigned int msiof1_tx_mux[] = {
2787 MSIOF1_TXD_MARK,
2788 };
2789
2790 static const unsigned int msiof1_clk_b_pins[] = {
2791 /* SCK */
2792 RCAR_GP_PIN(2, 29),
2793 };
2794 static const unsigned int msiof1_clk_b_mux[] = {
2795 MSIOF1_SCK_B_MARK,
2796 };
2797 static const unsigned int msiof1_sync_b_pins[] = {
2798 /* SYNC */
2799 RCAR_GP_PIN(2, 30),
2800 };
2801 static const unsigned int msiof1_sync_b_mux[] = {
2802 MSIOF1_SYNC_B_MARK,
2803 };
2804 static const unsigned int msiof1_ss1_b_pins[] = {
2805 /* SS1 */
2806 RCAR_GP_PIN(2, 31),
2807 };
2808 static const unsigned int msiof1_ss1_b_mux[] = {
2809 MSIOF1_SS1_B_MARK,
2810 };
2811 static const unsigned int msiof1_ss2_b_pins[] = {
2812 /* SS2 */
2813 RCAR_GP_PIN(7, 16),
2814 };
2815 static const unsigned int msiof1_ss2_b_mux[] = {
2816 MSIOF1_SS2_B_MARK,
2817 };
2818 static const unsigned int msiof1_rx_b_pins[] = {
2819 /* RXD */
2820 RCAR_GP_PIN(7, 18),
2821 };
2822 static const unsigned int msiof1_rx_b_mux[] = {
2823 MSIOF1_RXD_B_MARK,
2824 };
2825 static const unsigned int msiof1_tx_b_pins[] = {
2826 /* TXD */
2827 RCAR_GP_PIN(7, 17),
2828 };
2829 static const unsigned int msiof1_tx_b_mux[] = {
2830 MSIOF1_TXD_B_MARK,
2831 };
2832
2833 static const unsigned int msiof1_clk_c_pins[] = {
2834 /* SCK */
2835 RCAR_GP_PIN(2, 15),
2836 };
2837 static const unsigned int msiof1_clk_c_mux[] = {
2838 MSIOF1_SCK_C_MARK,
2839 };
2840 static const unsigned int msiof1_sync_c_pins[] = {
2841 /* SYNC */
2842 RCAR_GP_PIN(2, 16),
2843 };
2844 static const unsigned int msiof1_sync_c_mux[] = {
2845 MSIOF1_SYNC_C_MARK,
2846 };
2847 static const unsigned int msiof1_rx_c_pins[] = {
2848 /* RXD */
2849 RCAR_GP_PIN(2, 18),
2850 };
2851 static const unsigned int msiof1_rx_c_mux[] = {
2852 MSIOF1_RXD_C_MARK,
2853 };
2854 static const unsigned int msiof1_tx_c_pins[] = {
2855 /* TXD */
2856 RCAR_GP_PIN(2, 17),
2857 };
2858 static const unsigned int msiof1_tx_c_mux[] = {
2859 MSIOF1_TXD_C_MARK,
2860 };
2861
2862 static const unsigned int msiof1_clk_d_pins[] = {
2863 /* SCK */
2864 RCAR_GP_PIN(0, 28),
2865 };
2866 static const unsigned int msiof1_clk_d_mux[] = {
2867 MSIOF1_SCK_D_MARK,
2868 };
2869 static const unsigned int msiof1_sync_d_pins[] = {
2870 /* SYNC */
2871 RCAR_GP_PIN(0, 30),
2872 };
2873 static const unsigned int msiof1_sync_d_mux[] = {
2874 MSIOF1_SYNC_D_MARK,
2875 };
2876 static const unsigned int msiof1_ss1_d_pins[] = {
2877 /* SS1 */
2878 RCAR_GP_PIN(0, 29),
2879 };
2880 static const unsigned int msiof1_ss1_d_mux[] = {
2881 MSIOF1_SS1_D_MARK,
2882 };
2883 static const unsigned int msiof1_rx_d_pins[] = {
2884 /* RXD */
2885 RCAR_GP_PIN(0, 27),
2886 };
2887 static const unsigned int msiof1_rx_d_mux[] = {
2888 MSIOF1_RXD_D_MARK,
2889 };
2890 static const unsigned int msiof1_tx_d_pins[] = {
2891 /* TXD */
2892 RCAR_GP_PIN(0, 26),
2893 };
2894 static const unsigned int msiof1_tx_d_mux[] = {
2895 MSIOF1_TXD_D_MARK,
2896 };
2897
2898 static const unsigned int msiof1_clk_e_pins[] = {
2899 /* SCK */
2900 RCAR_GP_PIN(5, 18),
2901 };
2902 static const unsigned int msiof1_clk_e_mux[] = {
2903 MSIOF1_SCK_E_MARK,
2904 };
2905 static const unsigned int msiof1_sync_e_pins[] = {
2906 /* SYNC */
2907 RCAR_GP_PIN(5, 19),
2908 };
2909 static const unsigned int msiof1_sync_e_mux[] = {
2910 MSIOF1_SYNC_E_MARK,
2911 };
2912 static const unsigned int msiof1_rx_e_pins[] = {
2913 /* RXD */
2914 RCAR_GP_PIN(5, 17),
2915 };
2916 static const unsigned int msiof1_rx_e_mux[] = {
2917 MSIOF1_RXD_E_MARK,
2918 };
2919 static const unsigned int msiof1_tx_e_pins[] = {
2920 /* TXD */
2921 RCAR_GP_PIN(5, 20),
2922 };
2923 static const unsigned int msiof1_tx_e_mux[] = {
2924 MSIOF1_TXD_E_MARK,
2925 };
2926 /* - MSIOF2 ----------------------------------------------------------------- */
2927 static const unsigned int msiof2_clk_pins[] = {
2928 /* SCK */
2929 RCAR_GP_PIN(1, 13),
2930 };
2931 static const unsigned int msiof2_clk_mux[] = {
2932 MSIOF2_SCK_MARK,
2933 };
2934 static const unsigned int msiof2_sync_pins[] = {
2935 /* SYNC */
2936 RCAR_GP_PIN(1, 14),
2937 };
2938 static const unsigned int msiof2_sync_mux[] = {
2939 MSIOF2_SYNC_MARK,
2940 };
2941 static const unsigned int msiof2_ss1_pins[] = {
2942 /* SS1 */
2943 RCAR_GP_PIN(1, 17),
2944 };
2945 static const unsigned int msiof2_ss1_mux[] = {
2946 MSIOF2_SS1_MARK,
2947 };
2948 static const unsigned int msiof2_ss2_pins[] = {
2949 /* SS2 */
2950 RCAR_GP_PIN(1, 18),
2951 };
2952 static const unsigned int msiof2_ss2_mux[] = {
2953 MSIOF2_SS2_MARK,
2954 };
2955 static const unsigned int msiof2_rx_pins[] = {
2956 /* RXD */
2957 RCAR_GP_PIN(1, 16),
2958 };
2959 static const unsigned int msiof2_rx_mux[] = {
2960 MSIOF2_RXD_MARK,
2961 };
2962 static const unsigned int msiof2_tx_pins[] = {
2963 /* TXD */
2964 RCAR_GP_PIN(1, 15),
2965 };
2966 static const unsigned int msiof2_tx_mux[] = {
2967 MSIOF2_TXD_MARK,
2968 };
2969
2970 static const unsigned int msiof2_clk_b_pins[] = {
2971 /* SCK */
2972 RCAR_GP_PIN(3, 0),
2973 };
2974 static const unsigned int msiof2_clk_b_mux[] = {
2975 MSIOF2_SCK_B_MARK,
2976 };
2977 static const unsigned int msiof2_sync_b_pins[] = {
2978 /* SYNC */
2979 RCAR_GP_PIN(3, 1),
2980 };
2981 static const unsigned int msiof2_sync_b_mux[] = {
2982 MSIOF2_SYNC_B_MARK,
2983 };
2984 static const unsigned int msiof2_ss1_b_pins[] = {
2985 /* SS1 */
2986 RCAR_GP_PIN(3, 8),
2987 };
2988 static const unsigned int msiof2_ss1_b_mux[] = {
2989 MSIOF2_SS1_B_MARK,
2990 };
2991 static const unsigned int msiof2_ss2_b_pins[] = {
2992 /* SS2 */
2993 RCAR_GP_PIN(3, 9),
2994 };
2995 static const unsigned int msiof2_ss2_b_mux[] = {
2996 MSIOF2_SS2_B_MARK,
2997 };
2998 static const unsigned int msiof2_rx_b_pins[] = {
2999 /* RXD */
3000 RCAR_GP_PIN(3, 17),
3001 };
3002 static const unsigned int msiof2_rx_b_mux[] = {
3003 MSIOF2_RXD_B_MARK,
3004 };
3005 static const unsigned int msiof2_tx_b_pins[] = {
3006 /* TXD */
3007 RCAR_GP_PIN(3, 16),
3008 };
3009 static const unsigned int msiof2_tx_b_mux[] = {
3010 MSIOF2_TXD_B_MARK,
3011 };
3012
3013 static const unsigned int msiof2_clk_c_pins[] = {
3014 /* SCK */
3015 RCAR_GP_PIN(2, 2),
3016 };
3017 static const unsigned int msiof2_clk_c_mux[] = {
3018 MSIOF2_SCK_C_MARK,
3019 };
3020 static const unsigned int msiof2_sync_c_pins[] = {
3021 /* SYNC */
3022 RCAR_GP_PIN(2, 3),
3023 };
3024 static const unsigned int msiof2_sync_c_mux[] = {
3025 MSIOF2_SYNC_C_MARK,
3026 };
3027 static const unsigned int msiof2_rx_c_pins[] = {
3028 /* RXD */
3029 RCAR_GP_PIN(2, 5),
3030 };
3031 static const unsigned int msiof2_rx_c_mux[] = {
3032 MSIOF2_RXD_C_MARK,
3033 };
3034 static const unsigned int msiof2_tx_c_pins[] = {
3035 /* TXD */
3036 RCAR_GP_PIN(2, 4),
3037 };
3038 static const unsigned int msiof2_tx_c_mux[] = {
3039 MSIOF2_TXD_C_MARK,
3040 };
3041
3042 static const unsigned int msiof2_clk_d_pins[] = {
3043 /* SCK */
3044 RCAR_GP_PIN(2, 14),
3045 };
3046 static const unsigned int msiof2_clk_d_mux[] = {
3047 MSIOF2_SCK_D_MARK,
3048 };
3049 static const unsigned int msiof2_sync_d_pins[] = {
3050 /* SYNC */
3051 RCAR_GP_PIN(2, 15),
3052 };
3053 static const unsigned int msiof2_sync_d_mux[] = {
3054 MSIOF2_SYNC_D_MARK,
3055 };
3056 static const unsigned int msiof2_ss1_d_pins[] = {
3057 /* SS1 */
3058 RCAR_GP_PIN(2, 17),
3059 };
3060 static const unsigned int msiof2_ss1_d_mux[] = {
3061 MSIOF2_SS1_D_MARK,
3062 };
3063 static const unsigned int msiof2_ss2_d_pins[] = {
3064 /* SS2 */
3065 RCAR_GP_PIN(2, 19),
3066 };
3067 static const unsigned int msiof2_ss2_d_mux[] = {
3068 MSIOF2_SS2_D_MARK,
3069 };
3070 static const unsigned int msiof2_rx_d_pins[] = {
3071 /* RXD */
3072 RCAR_GP_PIN(2, 18),
3073 };
3074 static const unsigned int msiof2_rx_d_mux[] = {
3075 MSIOF2_RXD_D_MARK,
3076 };
3077 static const unsigned int msiof2_tx_d_pins[] = {
3078 /* TXD */
3079 RCAR_GP_PIN(2, 16),
3080 };
3081 static const unsigned int msiof2_tx_d_mux[] = {
3082 MSIOF2_TXD_D_MARK,
3083 };
3084
3085 static const unsigned int msiof2_clk_e_pins[] = {
3086 /* SCK */
3087 RCAR_GP_PIN(7, 15),
3088 };
3089 static const unsigned int msiof2_clk_e_mux[] = {
3090 MSIOF2_SCK_E_MARK,
3091 };
3092 static const unsigned int msiof2_sync_e_pins[] = {
3093 /* SYNC */
3094 RCAR_GP_PIN(7, 16),
3095 };
3096 static const unsigned int msiof2_sync_e_mux[] = {
3097 MSIOF2_SYNC_E_MARK,
3098 };
3099 static const unsigned int msiof2_rx_e_pins[] = {
3100 /* RXD */
3101 RCAR_GP_PIN(7, 14),
3102 };
3103 static const unsigned int msiof2_rx_e_mux[] = {
3104 MSIOF2_RXD_E_MARK,
3105 };
3106 static const unsigned int msiof2_tx_e_pins[] = {
3107 /* TXD */
3108 RCAR_GP_PIN(7, 13),
3109 };
3110 static const unsigned int msiof2_tx_e_mux[] = {
3111 MSIOF2_TXD_E_MARK,
3112 };
3113 /* - PWM -------------------------------------------------------------------- */
3114 static const unsigned int pwm0_pins[] = {
3115 RCAR_GP_PIN(6, 14),
3116 };
3117 static const unsigned int pwm0_mux[] = {
3118 PWM0_MARK,
3119 };
3120 static const unsigned int pwm0_b_pins[] = {
3121 RCAR_GP_PIN(5, 30),
3122 };
3123 static const unsigned int pwm0_b_mux[] = {
3124 PWM0_B_MARK,
3125 };
3126 static const unsigned int pwm1_pins[] = {
3127 RCAR_GP_PIN(1, 17),
3128 };
3129 static const unsigned int pwm1_mux[] = {
3130 PWM1_MARK,
3131 };
3132 static const unsigned int pwm1_b_pins[] = {
3133 RCAR_GP_PIN(6, 15),
3134 };
3135 static const unsigned int pwm1_b_mux[] = {
3136 PWM1_B_MARK,
3137 };
3138 static const unsigned int pwm2_pins[] = {
3139 RCAR_GP_PIN(1, 18),
3140 };
3141 static const unsigned int pwm2_mux[] = {
3142 PWM2_MARK,
3143 };
3144 static const unsigned int pwm2_b_pins[] = {
3145 RCAR_GP_PIN(0, 16),
3146 };
3147 static const unsigned int pwm2_b_mux[] = {
3148 PWM2_B_MARK,
3149 };
3150 static const unsigned int pwm3_pins[] = {
3151 RCAR_GP_PIN(1, 24),
3152 };
3153 static const unsigned int pwm3_mux[] = {
3154 PWM3_MARK,
3155 };
3156 static const unsigned int pwm4_pins[] = {
3157 RCAR_GP_PIN(3, 26),
3158 };
3159 static const unsigned int pwm4_mux[] = {
3160 PWM4_MARK,
3161 };
3162 static const unsigned int pwm4_b_pins[] = {
3163 RCAR_GP_PIN(3, 31),
3164 };
3165 static const unsigned int pwm4_b_mux[] = {
3166 PWM4_B_MARK,
3167 };
3168 static const unsigned int pwm5_pins[] = {
3169 RCAR_GP_PIN(7, 21),
3170 };
3171 static const unsigned int pwm5_mux[] = {
3172 PWM5_MARK,
3173 };
3174 static const unsigned int pwm5_b_pins[] = {
3175 RCAR_GP_PIN(7, 20),
3176 };
3177 static const unsigned int pwm5_b_mux[] = {
3178 PWM5_B_MARK,
3179 };
3180 static const unsigned int pwm6_pins[] = {
3181 RCAR_GP_PIN(7, 22),
3182 };
3183 static const unsigned int pwm6_mux[] = {
3184 PWM6_MARK,
3185 };
3186 /* - QSPI ------------------------------------------------------------------- */
3187 static const unsigned int qspi_ctrl_pins[] = {
3188 /* SPCLK, SSL */
3189 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
3190 };
3191 static const unsigned int qspi_ctrl_mux[] = {
3192 SPCLK_MARK, SSL_MARK,
3193 };
3194 static const unsigned int qspi_data2_pins[] = {
3195 /* MOSI_IO0, MISO_IO1 */
3196 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3197 };
3198 static const unsigned int qspi_data2_mux[] = {
3199 MOSI_IO0_MARK, MISO_IO1_MARK,
3200 };
3201 static const unsigned int qspi_data4_pins[] = {
3202 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3203 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3204 RCAR_GP_PIN(1, 8),
3205 };
3206 static const unsigned int qspi_data4_mux[] = {
3207 MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
3208 };
3209
3210 static const unsigned int qspi_ctrl_b_pins[] = {
3211 /* SPCLK, SSL */
3212 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
3213 };
3214 static const unsigned int qspi_ctrl_b_mux[] = {
3215 SPCLK_B_MARK, SSL_B_MARK,
3216 };
3217 static const unsigned int qspi_data2_b_pins[] = {
3218 /* MOSI_IO0, MISO_IO1 */
3219 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
3220 };
3221 static const unsigned int qspi_data2_b_mux[] = {
3222 MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
3223 };
3224 static const unsigned int qspi_data4_b_pins[] = {
3225 /* MOSI_IO0, MISO_IO1, IO2, IO3 */
3226 RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3227 RCAR_GP_PIN(6, 4),
3228 };
3229 static const unsigned int qspi_data4_b_mux[] = {
3230 MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
3231 };
3232 /* - SCIF0 ------------------------------------------------------------------ */
3233 static const unsigned int scif0_data_pins[] = {
3234 /* RX, TX */
3235 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3236 };
3237 static const unsigned int scif0_data_mux[] = {
3238 RX0_MARK, TX0_MARK,
3239 };
3240 static const unsigned int scif0_data_b_pins[] = {
3241 /* RX, TX */
3242 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3243 };
3244 static const unsigned int scif0_data_b_mux[] = {
3245 RX0_B_MARK, TX0_B_MARK,
3246 };
3247 static const unsigned int scif0_data_c_pins[] = {
3248 /* RX, TX */
3249 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
3250 };
3251 static const unsigned int scif0_data_c_mux[] = {
3252 RX0_C_MARK, TX0_C_MARK,
3253 };
3254 static const unsigned int scif0_data_d_pins[] = {
3255 /* RX, TX */
3256 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
3257 };
3258 static const unsigned int scif0_data_d_mux[] = {
3259 RX0_D_MARK, TX0_D_MARK,
3260 };
3261 static const unsigned int scif0_data_e_pins[] = {
3262 /* RX, TX */
3263 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
3264 };
3265 static const unsigned int scif0_data_e_mux[] = {
3266 RX0_E_MARK, TX0_E_MARK,
3267 };
3268 /* - SCIF1 ------------------------------------------------------------------ */
3269 static const unsigned int scif1_data_pins[] = {
3270 /* RX, TX */
3271 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3272 };
3273 static const unsigned int scif1_data_mux[] = {
3274 RX1_MARK, TX1_MARK,
3275 };
3276 static const unsigned int scif1_data_b_pins[] = {
3277 /* RX, TX */
3278 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3279 };
3280 static const unsigned int scif1_data_b_mux[] = {
3281 RX1_B_MARK, TX1_B_MARK,
3282 };
3283 static const unsigned int scif1_clk_b_pins[] = {
3284 /* SCK */
3285 RCAR_GP_PIN(3, 10),
3286 };
3287 static const unsigned int scif1_clk_b_mux[] = {
3288 SCIF1_SCK_B_MARK,
3289 };
3290 static const unsigned int scif1_data_c_pins[] = {
3291 /* RX, TX */
3292 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
3293 };
3294 static const unsigned int scif1_data_c_mux[] = {
3295 RX1_C_MARK, TX1_C_MARK,
3296 };
3297 static const unsigned int scif1_data_d_pins[] = {
3298 /* RX, TX */
3299 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
3300 };
3301 static const unsigned int scif1_data_d_mux[] = {
3302 RX1_D_MARK, TX1_D_MARK,
3303 };
3304 /* - SCIF2 ------------------------------------------------------------------ */
3305 static const unsigned int scif2_data_pins[] = {
3306 /* RX, TX */
3307 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3308 };
3309 static const unsigned int scif2_data_mux[] = {
3310 RX2_MARK, TX2_MARK,
3311 };
3312 static const unsigned int scif2_data_b_pins[] = {
3313 /* RX, TX */
3314 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3315 };
3316 static const unsigned int scif2_data_b_mux[] = {
3317 RX2_B_MARK, TX2_B_MARK,
3318 };
3319 static const unsigned int scif2_clk_b_pins[] = {
3320 /* SCK */
3321 RCAR_GP_PIN(3, 18),
3322 };
3323 static const unsigned int scif2_clk_b_mux[] = {
3324 SCIF2_SCK_B_MARK,
3325 };
3326 static const unsigned int scif2_data_c_pins[] = {
3327 /* RX, TX */
3328 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3329 };
3330 static const unsigned int scif2_data_c_mux[] = {
3331 RX2_C_MARK, TX2_C_MARK,
3332 };
3333 static const unsigned int scif2_data_e_pins[] = {
3334 /* RX, TX */
3335 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3336 };
3337 static const unsigned int scif2_data_e_mux[] = {
3338 RX2_E_MARK, TX2_E_MARK,
3339 };
3340 /* - SCIF3 ------------------------------------------------------------------ */
3341 static const unsigned int scif3_data_pins[] = {
3342 /* RX, TX */
3343 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3344 };
3345 static const unsigned int scif3_data_mux[] = {
3346 RX3_MARK, TX3_MARK,
3347 };
3348 static const unsigned int scif3_clk_pins[] = {
3349 /* SCK */
3350 RCAR_GP_PIN(3, 23),
3351 };
3352 static const unsigned int scif3_clk_mux[] = {
3353 SCIF3_SCK_MARK,
3354 };
3355 static const unsigned int scif3_data_b_pins[] = {
3356 /* RX, TX */
3357 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
3358 };
3359 static const unsigned int scif3_data_b_mux[] = {
3360 RX3_B_MARK, TX3_B_MARK,
3361 };
3362 static const unsigned int scif3_clk_b_pins[] = {
3363 /* SCK */
3364 RCAR_GP_PIN(4, 8),
3365 };
3366 static const unsigned int scif3_clk_b_mux[] = {
3367 SCIF3_SCK_B_MARK,
3368 };
3369 static const unsigned int scif3_data_c_pins[] = {
3370 /* RX, TX */
3371 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3372 };
3373 static const unsigned int scif3_data_c_mux[] = {
3374 RX3_C_MARK, TX3_C_MARK,
3375 };
3376 static const unsigned int scif3_data_d_pins[] = {
3377 /* RX, TX */
3378 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
3379 };
3380 static const unsigned int scif3_data_d_mux[] = {
3381 RX3_D_MARK, TX3_D_MARK,
3382 };
3383 /* - SCIF4 ------------------------------------------------------------------ */
3384 static const unsigned int scif4_data_pins[] = {
3385 /* RX, TX */
3386 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3387 };
3388 static const unsigned int scif4_data_mux[] = {
3389 RX4_MARK, TX4_MARK,
3390 };
3391 static const unsigned int scif4_data_b_pins[] = {
3392 /* RX, TX */
3393 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3394 };
3395 static const unsigned int scif4_data_b_mux[] = {
3396 RX4_B_MARK, TX4_B_MARK,
3397 };
3398 static const unsigned int scif4_data_c_pins[] = {
3399 /* RX, TX */
3400 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3401 };
3402 static const unsigned int scif4_data_c_mux[] = {
3403 RX4_C_MARK, TX4_C_MARK,
3404 };
3405 /* - SCIF5 ------------------------------------------------------------------ */
3406 static const unsigned int scif5_data_pins[] = {
3407 /* RX, TX */
3408 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3409 };
3410 static const unsigned int scif5_data_mux[] = {
3411 RX5_MARK, TX5_MARK,
3412 };
3413 static const unsigned int scif5_data_b_pins[] = {
3414 /* RX, TX */
3415 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3416 };
3417 static const unsigned int scif5_data_b_mux[] = {
3418 RX5_B_MARK, TX5_B_MARK,
3419 };
3420 /* - SCIFA0 ----------------------------------------------------------------- */
3421 static const unsigned int scifa0_data_pins[] = {
3422 /* RXD, TXD */
3423 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
3424 };
3425 static const unsigned int scifa0_data_mux[] = {
3426 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
3427 };
3428 static const unsigned int scifa0_data_b_pins[] = {
3429 /* RXD, TXD */
3430 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
3431 };
3432 static const unsigned int scifa0_data_b_mux[] = {
3433 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
3434 };
3435 /* - SCIFA1 ----------------------------------------------------------------- */
3436 static const unsigned int scifa1_data_pins[] = {
3437 /* RXD, TXD */
3438 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
3439 };
3440 static const unsigned int scifa1_data_mux[] = {
3441 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
3442 };
3443 static const unsigned int scifa1_clk_pins[] = {
3444 /* SCK */
3445 RCAR_GP_PIN(3, 10),
3446 };
3447 static const unsigned int scifa1_clk_mux[] = {
3448 SCIFA1_SCK_MARK,
3449 };
3450 static const unsigned int scifa1_data_b_pins[] = {
3451 /* RXD, TXD */
3452 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
3453 };
3454 static const unsigned int scifa1_data_b_mux[] = {
3455 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
3456 };
3457 static const unsigned int scifa1_clk_b_pins[] = {
3458 /* SCK */
3459 RCAR_GP_PIN(1, 0),
3460 };
3461 static const unsigned int scifa1_clk_b_mux[] = {
3462 SCIFA1_SCK_B_MARK,
3463 };
3464 static const unsigned int scifa1_data_c_pins[] = {
3465 /* RXD, TXD */
3466 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3467 };
3468 static const unsigned int scifa1_data_c_mux[] = {
3469 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
3470 };
3471 /* - SCIFA2 ----------------------------------------------------------------- */
3472 static const unsigned int scifa2_data_pins[] = {
3473 /* RXD, TXD */
3474 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
3475 };
3476 static const unsigned int scifa2_data_mux[] = {
3477 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
3478 };
3479 static const unsigned int scifa2_clk_pins[] = {
3480 /* SCK */
3481 RCAR_GP_PIN(3, 18),
3482 };
3483 static const unsigned int scifa2_clk_mux[] = {
3484 SCIFA2_SCK_MARK,
3485 };
3486 static const unsigned int scifa2_data_b_pins[] = {
3487 /* RXD, TXD */
3488 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
3489 };
3490 static const unsigned int scifa2_data_b_mux[] = {
3491 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3492 };
3493 /* - SCIFA3 ----------------------------------------------------------------- */
3494 static const unsigned int scifa3_data_pins[] = {
3495 /* RXD, TXD */
3496 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
3497 };
3498 static const unsigned int scifa3_data_mux[] = {
3499 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
3500 };
3501 static const unsigned int scifa3_clk_pins[] = {
3502 /* SCK */
3503 RCAR_GP_PIN(3, 23),
3504 };
3505 static const unsigned int scifa3_clk_mux[] = {
3506 SCIFA3_SCK_MARK,
3507 };
3508 static const unsigned int scifa3_data_b_pins[] = {
3509 /* RXD, TXD */
3510 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
3511 };
3512 static const unsigned int scifa3_data_b_mux[] = {
3513 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
3514 };
3515 static const unsigned int scifa3_clk_b_pins[] = {
3516 /* SCK */
3517 RCAR_GP_PIN(4, 8),
3518 };
3519 static const unsigned int scifa3_clk_b_mux[] = {
3520 SCIFA3_SCK_B_MARK,
3521 };
3522 static const unsigned int scifa3_data_c_pins[] = {
3523 /* RXD, TXD */
3524 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
3525 };
3526 static const unsigned int scifa3_data_c_mux[] = {
3527 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
3528 };
3529 static const unsigned int scifa3_clk_c_pins[] = {
3530 /* SCK */
3531 RCAR_GP_PIN(7, 22),
3532 };
3533 static const unsigned int scifa3_clk_c_mux[] = {
3534 SCIFA3_SCK_C_MARK,
3535 };
3536 /* - SCIFA4 ----------------------------------------------------------------- */
3537 static const unsigned int scifa4_data_pins[] = {
3538 /* RXD, TXD */
3539 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
3540 };
3541 static const unsigned int scifa4_data_mux[] = {
3542 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
3543 };
3544 static const unsigned int scifa4_data_b_pins[] = {
3545 /* RXD, TXD */
3546 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
3547 };
3548 static const unsigned int scifa4_data_b_mux[] = {
3549 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
3550 };
3551 static const unsigned int scifa4_data_c_pins[] = {
3552 /* RXD, TXD */
3553 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
3554 };
3555 static const unsigned int scifa4_data_c_mux[] = {
3556 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
3557 };
3558 /* - SCIFA5 ----------------------------------------------------------------- */
3559 static const unsigned int scifa5_data_pins[] = {
3560 /* RXD, TXD */
3561 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
3562 };
3563 static const unsigned int scifa5_data_mux[] = {
3564 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
3565 };
3566 static const unsigned int scifa5_data_b_pins[] = {
3567 /* RXD, TXD */
3568 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
3569 };
3570 static const unsigned int scifa5_data_b_mux[] = {
3571 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
3572 };
3573 static const unsigned int scifa5_data_c_pins[] = {
3574 /* RXD, TXD */
3575 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
3576 };
3577 static const unsigned int scifa5_data_c_mux[] = {
3578 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
3579 };
3580 /* - SCIFB0 ----------------------------------------------------------------- */
3581 static const unsigned int scifb0_data_pins[] = {
3582 /* RXD, TXD */
3583 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
3584 };
3585 static const unsigned int scifb0_data_mux[] = {
3586 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3587 };
3588 static const unsigned int scifb0_clk_pins[] = {
3589 /* SCK */
3590 RCAR_GP_PIN(7, 2),
3591 };
3592 static const unsigned int scifb0_clk_mux[] = {
3593 SCIFB0_SCK_MARK,
3594 };
3595 static const unsigned int scifb0_ctrl_pins[] = {
3596 /* RTS, CTS */
3597 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
3598 };
3599 static const unsigned int scifb0_ctrl_mux[] = {
3600 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3601 };
3602 static const unsigned int scifb0_data_b_pins[] = {
3603 /* RXD, TXD */
3604 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
3605 };
3606 static const unsigned int scifb0_data_b_mux[] = {
3607 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3608 };
3609 static const unsigned int scifb0_clk_b_pins[] = {
3610 /* SCK */
3611 RCAR_GP_PIN(5, 31),
3612 };
3613 static const unsigned int scifb0_clk_b_mux[] = {
3614 SCIFB0_SCK_B_MARK,
3615 };
3616 static const unsigned int scifb0_ctrl_b_pins[] = {
3617 /* RTS, CTS */
3618 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
3619 };
3620 static const unsigned int scifb0_ctrl_b_mux[] = {
3621 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3622 };
3623 static const unsigned int scifb0_data_c_pins[] = {
3624 /* RXD, TXD */
3625 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3626 };
3627 static const unsigned int scifb0_data_c_mux[] = {
3628 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3629 };
3630 static const unsigned int scifb0_clk_c_pins[] = {
3631 /* SCK */
3632 RCAR_GP_PIN(2, 30),
3633 };
3634 static const unsigned int scifb0_clk_c_mux[] = {
3635 SCIFB0_SCK_C_MARK,
3636 };
3637 static const unsigned int scifb0_data_d_pins[] = {
3638 /* RXD, TXD */
3639 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
3640 };
3641 static const unsigned int scifb0_data_d_mux[] = {
3642 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
3643 };
3644 static const unsigned int scifb0_clk_d_pins[] = {
3645 /* SCK */
3646 RCAR_GP_PIN(4, 17),
3647 };
3648 static const unsigned int scifb0_clk_d_mux[] = {
3649 SCIFB0_SCK_D_MARK,
3650 };
3651 /* - SCIFB1 ----------------------------------------------------------------- */
3652 static const unsigned int scifb1_data_pins[] = {
3653 /* RXD, TXD */
3654 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
3655 };
3656 static const unsigned int scifb1_data_mux[] = {
3657 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3658 };
3659 static const unsigned int scifb1_clk_pins[] = {
3660 /* SCK */
3661 RCAR_GP_PIN(7, 7),
3662 };
3663 static const unsigned int scifb1_clk_mux[] = {
3664 SCIFB1_SCK_MARK,
3665 };
3666 static const unsigned int scifb1_ctrl_pins[] = {
3667 /* RTS, CTS */
3668 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
3669 };
3670 static const unsigned int scifb1_ctrl_mux[] = {
3671 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3672 };
3673 static const unsigned int scifb1_data_b_pins[] = {
3674 /* RXD, TXD */
3675 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
3676 };
3677 static const unsigned int scifb1_data_b_mux[] = {
3678 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3679 };
3680 static const unsigned int scifb1_clk_b_pins[] = {
3681 /* SCK */
3682 RCAR_GP_PIN(1, 3),
3683 };
3684 static const unsigned int scifb1_clk_b_mux[] = {
3685 SCIFB1_SCK_B_MARK,
3686 };
3687 static const unsigned int scifb1_data_c_pins[] = {
3688 /* RXD, TXD */
3689 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3690 };
3691 static const unsigned int scifb1_data_c_mux[] = {
3692 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3693 };
3694 static const unsigned int scifb1_clk_c_pins[] = {
3695 /* SCK */
3696 RCAR_GP_PIN(7, 11),
3697 };
3698 static const unsigned int scifb1_clk_c_mux[] = {
3699 SCIFB1_SCK_C_MARK,
3700 };
3701 static const unsigned int scifb1_data_d_pins[] = {
3702 /* RXD, TXD */
3703 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
3704 };
3705 static const unsigned int scifb1_data_d_mux[] = {
3706 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3707 };
3708 /* - SCIFB2 ----------------------------------------------------------------- */
3709 static const unsigned int scifb2_data_pins[] = {
3710 /* RXD, TXD */
3711 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
3712 };
3713 static const unsigned int scifb2_data_mux[] = {
3714 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3715 };
3716 static const unsigned int scifb2_clk_pins[] = {
3717 /* SCK */
3718 RCAR_GP_PIN(4, 15),
3719 };
3720 static const unsigned int scifb2_clk_mux[] = {
3721 SCIFB2_SCK_MARK,
3722 };
3723 static const unsigned int scifb2_ctrl_pins[] = {
3724 /* RTS, CTS */
3725 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
3726 };
3727 static const unsigned int scifb2_ctrl_mux[] = {
3728 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3729 };
3730 static const unsigned int scifb2_data_b_pins[] = {
3731 /* RXD, TXD */
3732 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3733 };
3734 static const unsigned int scifb2_data_b_mux[] = {
3735 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3736 };
3737 static const unsigned int scifb2_clk_b_pins[] = {
3738 /* SCK */
3739 RCAR_GP_PIN(5, 31),
3740 };
3741 static const unsigned int scifb2_clk_b_mux[] = {
3742 SCIFB2_SCK_B_MARK,
3743 };
3744 static const unsigned int scifb2_ctrl_b_pins[] = {
3745 /* RTS, CTS */
3746 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
3747 };
3748 static const unsigned int scifb2_ctrl_b_mux[] = {
3749 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3750 };
3751 static const unsigned int scifb2_data_c_pins[] = {
3752 /* RXD, TXD */
3753 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3754 };
3755 static const unsigned int scifb2_data_c_mux[] = {
3756 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3757 };
3758 static const unsigned int scifb2_clk_c_pins[] = {
3759 /* SCK */
3760 RCAR_GP_PIN(5, 27),
3761 };
3762 static const unsigned int scifb2_clk_c_mux[] = {
3763 SCIFB2_SCK_C_MARK,
3764 };
3765 static const unsigned int scifb2_data_d_pins[] = {
3766 /* RXD, TXD */
3767 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
3768 };
3769 static const unsigned int scifb2_data_d_mux[] = {
3770 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
3771 };
3772
3773 /* - SCIF Clock ------------------------------------------------------------- */
3774 static const unsigned int scif_clk_pins[] = {
3775 /* SCIF_CLK */
3776 RCAR_GP_PIN(2, 29),
3777 };
3778 static const unsigned int scif_clk_mux[] = {
3779 SCIF_CLK_MARK,
3780 };
3781 static const unsigned int scif_clk_b_pins[] = {
3782 /* SCIF_CLK */
3783 RCAR_GP_PIN(7, 19),
3784 };
3785 static const unsigned int scif_clk_b_mux[] = {
3786 SCIF_CLK_B_MARK,
3787 };
3788
3789 /* - SDHI0 ------------------------------------------------------------------ */
3790 static const unsigned int sdhi0_data1_pins[] = {
3791 /* D0 */
3792 RCAR_GP_PIN(6, 2),
3793 };
3794 static const unsigned int sdhi0_data1_mux[] = {
3795 SD0_DATA0_MARK,
3796 };
3797 static const unsigned int sdhi0_data4_pins[] = {
3798 /* D[0:3] */
3799 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
3800 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
3801 };
3802 static const unsigned int sdhi0_data4_mux[] = {
3803 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
3804 };
3805 static const unsigned int sdhi0_ctrl_pins[] = {
3806 /* CLK, CMD */
3807 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3808 };
3809 static const unsigned int sdhi0_ctrl_mux[] = {
3810 SD0_CLK_MARK, SD0_CMD_MARK,
3811 };
3812 static const unsigned int sdhi0_cd_pins[] = {
3813 /* CD */
3814 RCAR_GP_PIN(6, 6),
3815 };
3816 static const unsigned int sdhi0_cd_mux[] = {
3817 SD0_CD_MARK,
3818 };
3819 static const unsigned int sdhi0_wp_pins[] = {
3820 /* WP */
3821 RCAR_GP_PIN(6, 7),
3822 };
3823 static const unsigned int sdhi0_wp_mux[] = {
3824 SD0_WP_MARK,
3825 };
3826 /* - SDHI1 ------------------------------------------------------------------ */
3827 static const unsigned int sdhi1_data1_pins[] = {
3828 /* D0 */
3829 RCAR_GP_PIN(6, 10),
3830 };
3831 static const unsigned int sdhi1_data1_mux[] = {
3832 SD1_DATA0_MARK,
3833 };
3834 static const unsigned int sdhi1_data4_pins[] = {
3835 /* D[0:3] */
3836 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
3837 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
3838 };
3839 static const unsigned int sdhi1_data4_mux[] = {
3840 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
3841 };
3842 static const unsigned int sdhi1_ctrl_pins[] = {
3843 /* CLK, CMD */
3844 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3845 };
3846 static const unsigned int sdhi1_ctrl_mux[] = {
3847 SD1_CLK_MARK, SD1_CMD_MARK,
3848 };
3849 static const unsigned int sdhi1_cd_pins[] = {
3850 /* CD */
3851 RCAR_GP_PIN(6, 14),
3852 };
3853 static const unsigned int sdhi1_cd_mux[] = {
3854 SD1_CD_MARK,
3855 };
3856 static const unsigned int sdhi1_wp_pins[] = {
3857 /* WP */
3858 RCAR_GP_PIN(6, 15),
3859 };
3860 static const unsigned int sdhi1_wp_mux[] = {
3861 SD1_WP_MARK,
3862 };
3863 /* - SDHI2 ------------------------------------------------------------------ */
3864 static const unsigned int sdhi2_data1_pins[] = {
3865 /* D0 */
3866 RCAR_GP_PIN(6, 18),
3867 };
3868 static const unsigned int sdhi2_data1_mux[] = {
3869 SD2_DATA0_MARK,
3870 };
3871 static const unsigned int sdhi2_data4_pins[] = {
3872 /* D[0:3] */
3873 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
3874 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
3875 };
3876 static const unsigned int sdhi2_data4_mux[] = {
3877 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
3878 };
3879 static const unsigned int sdhi2_ctrl_pins[] = {
3880 /* CLK, CMD */
3881 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
3882 };
3883 static const unsigned int sdhi2_ctrl_mux[] = {
3884 SD2_CLK_MARK, SD2_CMD_MARK,
3885 };
3886 static const unsigned int sdhi2_cd_pins[] = {
3887 /* CD */
3888 RCAR_GP_PIN(6, 22),
3889 };
3890 static const unsigned int sdhi2_cd_mux[] = {
3891 SD2_CD_MARK,
3892 };
3893 static const unsigned int sdhi2_wp_pins[] = {
3894 /* WP */
3895 RCAR_GP_PIN(6, 23),
3896 };
3897 static const unsigned int sdhi2_wp_mux[] = {
3898 SD2_WP_MARK,
3899 };
3900
3901 /* - SSI -------------------------------------------------------------------- */
3902 static const unsigned int ssi0_data_pins[] = {
3903 /* SDATA */
3904 RCAR_GP_PIN(2, 2),
3905 };
3906
3907 static const unsigned int ssi0_data_mux[] = {
3908 SSI_SDATA0_MARK,
3909 };
3910
3911 static const unsigned int ssi0_data_b_pins[] = {
3912 /* SDATA */
3913 RCAR_GP_PIN(3, 4),
3914 };
3915
3916 static const unsigned int ssi0_data_b_mux[] = {
3917 SSI_SDATA0_B_MARK,
3918 };
3919
3920 static const unsigned int ssi0129_ctrl_pins[] = {
3921 /* SCK, WS */
3922 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
3923 };
3924
3925 static const unsigned int ssi0129_ctrl_mux[] = {
3926 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3927 };
3928
3929 static const unsigned int ssi0129_ctrl_b_pins[] = {
3930 /* SCK, WS */
3931 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3932 };
3933
3934 static const unsigned int ssi0129_ctrl_b_mux[] = {
3935 SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
3936 };
3937
3938 static const unsigned int ssi1_data_pins[] = {
3939 /* SDATA */
3940 RCAR_GP_PIN(2, 5),
3941 };
3942
3943 static const unsigned int ssi1_data_mux[] = {
3944 SSI_SDATA1_MARK,
3945 };
3946
3947 static const unsigned int ssi1_data_b_pins[] = {
3948 /* SDATA */
3949 RCAR_GP_PIN(3, 7),
3950 };
3951
3952 static const unsigned int ssi1_data_b_mux[] = {
3953 SSI_SDATA1_B_MARK,
3954 };
3955
3956 static const unsigned int ssi1_ctrl_pins[] = {
3957 /* SCK, WS */
3958 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3959 };
3960
3961 static const unsigned int ssi1_ctrl_mux[] = {
3962 SSI_SCK1_MARK, SSI_WS1_MARK,
3963 };
3964
3965 static const unsigned int ssi1_ctrl_b_pins[] = {
3966 /* SCK, WS */
3967 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3968 };
3969
3970 static const unsigned int ssi1_ctrl_b_mux[] = {
3971 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3972 };
3973
3974 static const unsigned int ssi2_data_pins[] = {
3975 /* SDATA */
3976 RCAR_GP_PIN(2, 8),
3977 };
3978
3979 static const unsigned int ssi2_data_mux[] = {
3980 SSI_SDATA2_MARK,
3981 };
3982
3983 static const unsigned int ssi2_ctrl_pins[] = {
3984 /* SCK, WS */
3985 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3986 };
3987
3988 static const unsigned int ssi2_ctrl_mux[] = {
3989 SSI_SCK2_MARK, SSI_WS2_MARK,
3990 };
3991
3992 static const unsigned int ssi3_data_pins[] = {
3993 /* SDATA */
3994 RCAR_GP_PIN(2, 11),
3995 };
3996
3997 static const unsigned int ssi3_data_mux[] = {
3998 SSI_SDATA3_MARK,
3999 };
4000
4001 static const unsigned int ssi34_ctrl_pins[] = {
4002 /* SCK, WS */
4003 RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
4004 };
4005
4006 static const unsigned int ssi34_ctrl_mux[] = {
4007 SSI_SCK34_MARK, SSI_WS34_MARK,
4008 };
4009
4010 static const unsigned int ssi4_data_pins[] = {
4011 /* SDATA */
4012 RCAR_GP_PIN(2, 14),
4013 };
4014
4015 static const unsigned int ssi4_data_mux[] = {
4016 SSI_SDATA4_MARK,
4017 };
4018
4019 static const unsigned int ssi4_ctrl_pins[] = {
4020 /* SCK, WS */
4021 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
4022 };
4023
4024 static const unsigned int ssi4_ctrl_mux[] = {
4025 SSI_SCK4_MARK, SSI_WS4_MARK,
4026 };
4027
4028 static const unsigned int ssi5_data_pins[] = {
4029 /* SDATA */
4030 RCAR_GP_PIN(2, 17),
4031 };
4032
4033 static const unsigned int ssi5_data_mux[] = {
4034 SSI_SDATA5_MARK,
4035 };
4036
4037 static const unsigned int ssi5_ctrl_pins[] = {
4038 /* SCK, WS */
4039 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4040 };
4041
4042 static const unsigned int ssi5_ctrl_mux[] = {
4043 SSI_SCK5_MARK, SSI_WS5_MARK,
4044 };
4045
4046 static const unsigned int ssi6_data_pins[] = {
4047 /* SDATA */
4048 RCAR_GP_PIN(2, 20),
4049 };
4050
4051 static const unsigned int ssi6_data_mux[] = {
4052 SSI_SDATA6_MARK,
4053 };
4054
4055 static const unsigned int ssi6_ctrl_pins[] = {
4056 /* SCK, WS */
4057 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
4058 };
4059
4060 static const unsigned int ssi6_ctrl_mux[] = {
4061 SSI_SCK6_MARK, SSI_WS6_MARK,
4062 };
4063
4064 static const unsigned int ssi7_data_pins[] = {
4065 /* SDATA */
4066 RCAR_GP_PIN(2, 23),
4067 };
4068
4069 static const unsigned int ssi7_data_mux[] = {
4070 SSI_SDATA7_MARK,
4071 };
4072
4073 static const unsigned int ssi7_data_b_pins[] = {
4074 /* SDATA */
4075 RCAR_GP_PIN(3, 12),
4076 };
4077
4078 static const unsigned int ssi7_data_b_mux[] = {
4079 SSI_SDATA7_B_MARK,
4080 };
4081
4082 static const unsigned int ssi78_ctrl_pins[] = {
4083 /* SCK, WS */
4084 RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
4085 };
4086
4087 static const unsigned int ssi78_ctrl_mux[] = {
4088 SSI_SCK78_MARK, SSI_WS78_MARK,
4089 };
4090
4091 static const unsigned int ssi78_ctrl_b_pins[] = {
4092 /* SCK, WS */
4093 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4094 };
4095
4096 static const unsigned int ssi78_ctrl_b_mux[] = {
4097 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
4098 };
4099
4100 static const unsigned int ssi8_data_pins[] = {
4101 /* SDATA */
4102 RCAR_GP_PIN(2, 24),
4103 };
4104
4105 static const unsigned int ssi8_data_mux[] = {
4106 SSI_SDATA8_MARK,
4107 };
4108
4109 static const unsigned int ssi8_data_b_pins[] = {
4110 /* SDATA */
4111 RCAR_GP_PIN(3, 13),
4112 };
4113
4114 static const unsigned int ssi8_data_b_mux[] = {
4115 SSI_SDATA8_B_MARK,
4116 };
4117
4118 static const unsigned int ssi9_data_pins[] = {
4119 /* SDATA */
4120 RCAR_GP_PIN(2, 27),
4121 };
4122
4123 static const unsigned int ssi9_data_mux[] = {
4124 SSI_SDATA9_MARK,
4125 };
4126
4127 static const unsigned int ssi9_data_b_pins[] = {
4128 /* SDATA */
4129 RCAR_GP_PIN(3, 18),
4130 };
4131
4132 static const unsigned int ssi9_data_b_mux[] = {
4133 SSI_SDATA9_B_MARK,
4134 };
4135
4136 static const unsigned int ssi9_ctrl_pins[] = {
4137 /* SCK, WS */
4138 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
4139 };
4140
4141 static const unsigned int ssi9_ctrl_mux[] = {
4142 SSI_SCK9_MARK, SSI_WS9_MARK,
4143 };
4144
4145 static const unsigned int ssi9_ctrl_b_pins[] = {
4146 /* SCK, WS */
4147 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
4148 };
4149
4150 static const unsigned int ssi9_ctrl_b_mux[] = {
4151 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
4152 };
4153
4154 /* - TPU -------------------------------------------------------------------- */
4155 static const unsigned int tpu_to0_pins[] = {
4156 RCAR_GP_PIN(6, 14),
4157 };
4158 static const unsigned int tpu_to0_mux[] = {
4159 TPU_TO0_MARK,
4160 };
4161 static const unsigned int tpu_to1_pins[] = {
4162 RCAR_GP_PIN(1, 17),
4163 };
4164 static const unsigned int tpu_to1_mux[] = {
4165 TPU_TO1_MARK,
4166 };
4167 static const unsigned int tpu_to2_pins[] = {
4168 RCAR_GP_PIN(1, 18),
4169 };
4170 static const unsigned int tpu_to2_mux[] = {
4171 TPU_TO2_MARK,
4172 };
4173 static const unsigned int tpu_to3_pins[] = {
4174 RCAR_GP_PIN(1, 24),
4175 };
4176 static const unsigned int tpu_to3_mux[] = {
4177 TPU_TO3_MARK,
4178 };
4179
4180 /* - USB0 ------------------------------------------------------------------- */
4181 static const unsigned int usb0_pins[] = {
4182 RCAR_GP_PIN(7, 23), /* PWEN */
4183 RCAR_GP_PIN(7, 24), /* OVC */
4184 };
4185 static const unsigned int usb0_mux[] = {
4186 USB0_PWEN_MARK,
4187 USB0_OVC_MARK,
4188 };
4189 /* - USB1 ------------------------------------------------------------------- */
4190 static const unsigned int usb1_pins[] = {
4191 RCAR_GP_PIN(7, 25), /* PWEN */
4192 RCAR_GP_PIN(6, 30), /* OVC */
4193 };
4194 static const unsigned int usb1_mux[] = {
4195 USB1_PWEN_MARK,
4196 USB1_OVC_MARK,
4197 };
4198 /* - VIN0 ------------------------------------------------------------------- */
4199 static const union vin_data vin0_data_pins = {
4200 .data24 = {
4201 /* B */
4202 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
4203 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4204 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4205 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4206 /* G */
4207 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
4208 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4209 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4210 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4211 /* R */
4212 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
4213 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4214 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4215 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4216 },
4217 };
4218 static const union vin_data vin0_data_mux = {
4219 .data24 = {
4220 /* B */
4221 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
4222 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4223 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4224 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4225 /* G */
4226 VI0_G0_MARK, VI0_G1_MARK,
4227 VI0_G2_MARK, VI0_G3_MARK,
4228 VI0_G4_MARK, VI0_G5_MARK,
4229 VI0_G6_MARK, VI0_G7_MARK,
4230 /* R */
4231 VI0_R0_MARK, VI0_R1_MARK,
4232 VI0_R2_MARK, VI0_R3_MARK,
4233 VI0_R4_MARK, VI0_R5_MARK,
4234 VI0_R6_MARK, VI0_R7_MARK,
4235 },
4236 };
4237 static const unsigned int vin0_data18_pins[] = {
4238 /* B */
4239 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
4240 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
4241 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
4242 /* G */
4243 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
4244 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
4245 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
4246 /* R */
4247 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
4248 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
4249 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
4250 };
4251 static const unsigned int vin0_data18_mux[] = {
4252 /* B */
4253 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
4254 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
4255 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
4256 /* G */
4257 VI0_G2_MARK, VI0_G3_MARK,
4258 VI0_G4_MARK, VI0_G5_MARK,
4259 VI0_G6_MARK, VI0_G7_MARK,
4260 /* R */
4261 VI0_R2_MARK, VI0_R3_MARK,
4262 VI0_R4_MARK, VI0_R5_MARK,
4263 VI0_R6_MARK, VI0_R7_MARK,
4264 };
4265 static const unsigned int vin0_sync_pins[] = {
4266 RCAR_GP_PIN(4, 3), /* HSYNC */
4267 RCAR_GP_PIN(4, 4), /* VSYNC */
4268 };
4269 static const unsigned int vin0_sync_mux[] = {
4270 VI0_HSYNC_N_MARK,
4271 VI0_VSYNC_N_MARK,
4272 };
4273 static const unsigned int vin0_field_pins[] = {
4274 RCAR_GP_PIN(4, 2),
4275 };
4276 static const unsigned int vin0_field_mux[] = {
4277 VI0_FIELD_MARK,
4278 };
4279 static const unsigned int vin0_clkenb_pins[] = {
4280 RCAR_GP_PIN(4, 1),
4281 };
4282 static const unsigned int vin0_clkenb_mux[] = {
4283 VI0_CLKENB_MARK,
4284 };
4285 static const unsigned int vin0_clk_pins[] = {
4286 RCAR_GP_PIN(4, 0),
4287 };
4288 static const unsigned int vin0_clk_mux[] = {
4289 VI0_CLK_MARK,
4290 };
4291 /* - VIN1 ----------------------------------------------------------------- */
4292 static const unsigned int vin1_data8_pins[] = {
4293 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
4294 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
4295 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
4296 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
4297 };
4298 static const unsigned int vin1_data8_mux[] = {
4299 VI1_DATA0_MARK, VI1_DATA1_MARK,
4300 VI1_DATA2_MARK, VI1_DATA3_MARK,
4301 VI1_DATA4_MARK, VI1_DATA5_MARK,
4302 VI1_DATA6_MARK, VI1_DATA7_MARK,
4303 };
4304 static const unsigned int vin1_sync_pins[] = {
4305 RCAR_GP_PIN(5, 0), /* HSYNC */
4306 RCAR_GP_PIN(5, 1), /* VSYNC */
4307 };
4308 static const unsigned int vin1_sync_mux[] = {
4309 VI1_HSYNC_N_MARK,
4310 VI1_VSYNC_N_MARK,
4311 };
4312 static const unsigned int vin1_field_pins[] = {
4313 RCAR_GP_PIN(5, 3),
4314 };
4315 static const unsigned int vin1_field_mux[] = {
4316 VI1_FIELD_MARK,
4317 };
4318 static const unsigned int vin1_clkenb_pins[] = {
4319 RCAR_GP_PIN(5, 2),
4320 };
4321 static const unsigned int vin1_clkenb_mux[] = {
4322 VI1_CLKENB_MARK,
4323 };
4324 static const unsigned int vin1_clk_pins[] = {
4325 RCAR_GP_PIN(5, 4),
4326 };
4327 static const unsigned int vin1_clk_mux[] = {
4328 VI1_CLK_MARK,
4329 };
4330 static const union vin_data vin1_data_b_pins = {
4331 .data24 = {
4332 /* B */
4333 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
4334 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4335 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4336 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4337 /* G */
4338 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
4339 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4340 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4341 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4342 /* R */
4343 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
4344 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4345 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4346 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4347 },
4348 };
4349 static const union vin_data vin1_data_b_mux = {
4350 .data24 = {
4351 /* B */
4352 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
4353 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4354 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4355 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4356 /* G */
4357 VI1_G0_B_MARK, VI1_G1_B_MARK,
4358 VI1_G2_B_MARK, VI1_G3_B_MARK,
4359 VI1_G4_B_MARK, VI1_G5_B_MARK,
4360 VI1_G6_B_MARK, VI1_G7_B_MARK,
4361 /* R */
4362 VI1_R0_B_MARK, VI1_R1_B_MARK,
4363 VI1_R2_B_MARK, VI1_R3_B_MARK,
4364 VI1_R4_B_MARK, VI1_R5_B_MARK,
4365 VI1_R6_B_MARK, VI1_R7_B_MARK,
4366 },
4367 };
4368 static const unsigned int vin1_data18_b_pins[] = {
4369 /* B */
4370 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
4371 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
4372 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
4373 /* G */
4374 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
4375 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
4376 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
4377 /* R */
4378 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
4379 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
4380 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
4381 };
4382 static const unsigned int vin1_data18_b_mux[] = {
4383 /* B */
4384 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
4385 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
4386 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
4387 /* G */
4388 VI1_G2_B_MARK, VI1_G3_B_MARK,
4389 VI1_G4_B_MARK, VI1_G5_B_MARK,
4390 VI1_G6_B_MARK, VI1_G7_B_MARK,
4391 /* R */
4392 VI1_R2_B_MARK, VI1_R3_B_MARK,
4393 VI1_R4_B_MARK, VI1_R5_B_MARK,
4394 VI1_R6_B_MARK, VI1_R7_B_MARK,
4395 };
4396 static const unsigned int vin1_sync_b_pins[] = {
4397 RCAR_GP_PIN(3, 17), /* HSYNC */
4398 RCAR_GP_PIN(3, 18), /* VSYNC */
4399 };
4400 static const unsigned int vin1_sync_b_mux[] = {
4401 VI1_HSYNC_N_B_MARK,
4402 VI1_VSYNC_N_B_MARK,
4403 };
4404 static const unsigned int vin1_field_b_pins[] = {
4405 RCAR_GP_PIN(3, 20),
4406 };
4407 static const unsigned int vin1_field_b_mux[] = {
4408 VI1_FIELD_B_MARK,
4409 };
4410 static const unsigned int vin1_clkenb_b_pins[] = {
4411 RCAR_GP_PIN(3, 19),
4412 };
4413 static const unsigned int vin1_clkenb_b_mux[] = {
4414 VI1_CLKENB_B_MARK,
4415 };
4416 static const unsigned int vin1_clk_b_pins[] = {
4417 RCAR_GP_PIN(3, 16),
4418 };
4419 static const unsigned int vin1_clk_b_mux[] = {
4420 VI1_CLK_B_MARK,
4421 };
4422 /* - VIN2 ----------------------------------------------------------------- */
4423 static const unsigned int vin2_data8_pins[] = {
4424 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
4425 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
4426 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
4427 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
4428 };
4429 static const unsigned int vin2_data8_mux[] = {
4430 VI2_DATA0_MARK, VI2_DATA1_MARK,
4431 VI2_DATA2_MARK, VI2_DATA3_MARK,
4432 VI2_DATA4_MARK, VI2_DATA5_MARK,
4433 VI2_DATA6_MARK, VI2_DATA7_MARK,
4434 };
4435 static const unsigned int vin2_sync_pins[] = {
4436 RCAR_GP_PIN(4, 15), /* HSYNC */
4437 RCAR_GP_PIN(4, 16), /* VSYNC */
4438 };
4439 static const unsigned int vin2_sync_mux[] = {
4440 VI2_HSYNC_N_MARK,
4441 VI2_VSYNC_N_MARK,
4442 };
4443 static const unsigned int vin2_field_pins[] = {
4444 RCAR_GP_PIN(4, 18),
4445 };
4446 static const unsigned int vin2_field_mux[] = {
4447 VI2_FIELD_MARK,
4448 };
4449 static const unsigned int vin2_clkenb_pins[] = {
4450 RCAR_GP_PIN(4, 17),
4451 };
4452 static const unsigned int vin2_clkenb_mux[] = {
4453 VI2_CLKENB_MARK,
4454 };
4455 static const unsigned int vin2_clk_pins[] = {
4456 RCAR_GP_PIN(4, 19),
4457 };
4458 static const unsigned int vin2_clk_mux[] = {
4459 VI2_CLK_MARK,
4460 };
4461
4462 static const struct {
4463 struct sh_pfc_pin_group common[346];
4464 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4465 struct sh_pfc_pin_group automotive[9];
4466 #endif
4467 } pinmux_groups = {
4468 .common = {
4469 SH_PFC_PIN_GROUP(audio_clk_a),
4470 SH_PFC_PIN_GROUP(audio_clk_b),
4471 SH_PFC_PIN_GROUP(audio_clk_b_b),
4472 SH_PFC_PIN_GROUP(audio_clk_c),
4473 SH_PFC_PIN_GROUP(audio_clkout),
4474 SH_PFC_PIN_GROUP(avb_link),
4475 SH_PFC_PIN_GROUP(avb_magic),
4476 SH_PFC_PIN_GROUP(avb_phy_int),
4477 SH_PFC_PIN_GROUP(avb_mdio),
4478 SH_PFC_PIN_GROUP(avb_mii),
4479 SH_PFC_PIN_GROUP(avb_gmii),
4480 SH_PFC_PIN_GROUP(can0_data),
4481 SH_PFC_PIN_GROUP(can0_data_b),
4482 SH_PFC_PIN_GROUP(can0_data_c),
4483 SH_PFC_PIN_GROUP(can0_data_d),
4484 SH_PFC_PIN_GROUP(can0_data_e),
4485 SH_PFC_PIN_GROUP(can0_data_f),
4486 SH_PFC_PIN_GROUP(can1_data),
4487 SH_PFC_PIN_GROUP(can1_data_b),
4488 SH_PFC_PIN_GROUP(can1_data_c),
4489 SH_PFC_PIN_GROUP(can1_data_d),
4490 SH_PFC_PIN_GROUP(can_clk),
4491 SH_PFC_PIN_GROUP(can_clk_b),
4492 SH_PFC_PIN_GROUP(can_clk_c),
4493 SH_PFC_PIN_GROUP(can_clk_d),
4494 SH_PFC_PIN_GROUP(du_rgb666),
4495 SH_PFC_PIN_GROUP(du_rgb888),
4496 SH_PFC_PIN_GROUP(du_clk_out_0),
4497 SH_PFC_PIN_GROUP(du_clk_out_1),
4498 SH_PFC_PIN_GROUP(du_sync),
4499 SH_PFC_PIN_GROUP(du_oddf),
4500 SH_PFC_PIN_GROUP(du_cde),
4501 SH_PFC_PIN_GROUP(du_disp),
4502 SH_PFC_PIN_GROUP(du0_clk_in),
4503 SH_PFC_PIN_GROUP(du1_clk_in),
4504 SH_PFC_PIN_GROUP(du1_clk_in_b),
4505 SH_PFC_PIN_GROUP(du1_clk_in_c),
4506 SH_PFC_PIN_GROUP(eth_link),
4507 SH_PFC_PIN_GROUP(eth_magic),
4508 SH_PFC_PIN_GROUP(eth_mdio),
4509 SH_PFC_PIN_GROUP(eth_rmii),
4510 SH_PFC_PIN_GROUP(hscif0_data),
4511 SH_PFC_PIN_GROUP(hscif0_clk),
4512 SH_PFC_PIN_GROUP(hscif0_ctrl),
4513 SH_PFC_PIN_GROUP(hscif0_data_b),
4514 SH_PFC_PIN_GROUP(hscif0_ctrl_b),
4515 SH_PFC_PIN_GROUP(hscif0_data_c),
4516 SH_PFC_PIN_GROUP(hscif0_clk_c),
4517 SH_PFC_PIN_GROUP(hscif1_data),
4518 SH_PFC_PIN_GROUP(hscif1_clk),
4519 SH_PFC_PIN_GROUP(hscif1_ctrl),
4520 SH_PFC_PIN_GROUP(hscif1_data_b),
4521 SH_PFC_PIN_GROUP(hscif1_data_c),
4522 SH_PFC_PIN_GROUP(hscif1_clk_c),
4523 SH_PFC_PIN_GROUP(hscif1_ctrl_c),
4524 SH_PFC_PIN_GROUP(hscif1_data_d),
4525 SH_PFC_PIN_GROUP(hscif1_data_e),
4526 SH_PFC_PIN_GROUP(hscif1_clk_e),
4527 SH_PFC_PIN_GROUP(hscif1_ctrl_e),
4528 SH_PFC_PIN_GROUP(hscif2_data),
4529 SH_PFC_PIN_GROUP(hscif2_clk),
4530 SH_PFC_PIN_GROUP(hscif2_ctrl),
4531 SH_PFC_PIN_GROUP(hscif2_data_b),
4532 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4533 SH_PFC_PIN_GROUP(hscif2_data_c),
4534 SH_PFC_PIN_GROUP(hscif2_clk_c),
4535 SH_PFC_PIN_GROUP(hscif2_data_d),
4536 SH_PFC_PIN_GROUP(i2c0),
4537 SH_PFC_PIN_GROUP(i2c0_b),
4538 SH_PFC_PIN_GROUP(i2c0_c),
4539 SH_PFC_PIN_GROUP(i2c1),
4540 SH_PFC_PIN_GROUP(i2c1_b),
4541 SH_PFC_PIN_GROUP(i2c1_c),
4542 SH_PFC_PIN_GROUP(i2c1_d),
4543 SH_PFC_PIN_GROUP(i2c1_e),
4544 SH_PFC_PIN_GROUP(i2c2),
4545 SH_PFC_PIN_GROUP(i2c2_b),
4546 SH_PFC_PIN_GROUP(i2c2_c),
4547 SH_PFC_PIN_GROUP(i2c2_d),
4548 SH_PFC_PIN_GROUP(i2c3),
4549 SH_PFC_PIN_GROUP(i2c3_b),
4550 SH_PFC_PIN_GROUP(i2c3_c),
4551 SH_PFC_PIN_GROUP(i2c3_d),
4552 SH_PFC_PIN_GROUP(i2c4),
4553 SH_PFC_PIN_GROUP(i2c4_b),
4554 SH_PFC_PIN_GROUP(i2c4_c),
4555 SH_PFC_PIN_GROUP(i2c7),
4556 SH_PFC_PIN_GROUP(i2c7_b),
4557 SH_PFC_PIN_GROUP(i2c7_c),
4558 SH_PFC_PIN_GROUP(i2c8),
4559 SH_PFC_PIN_GROUP(i2c8_b),
4560 SH_PFC_PIN_GROUP(i2c8_c),
4561 SH_PFC_PIN_GROUP(intc_irq0),
4562 SH_PFC_PIN_GROUP(intc_irq1),
4563 SH_PFC_PIN_GROUP(intc_irq2),
4564 SH_PFC_PIN_GROUP(intc_irq3),
4565 SH_PFC_PIN_GROUP(mmc_data1),
4566 SH_PFC_PIN_GROUP(mmc_data4),
4567 SH_PFC_PIN_GROUP(mmc_data8),
4568 SH_PFC_PIN_GROUP(mmc_data8_b),
4569 SH_PFC_PIN_GROUP(mmc_ctrl),
4570 SH_PFC_PIN_GROUP(msiof0_clk),
4571 SH_PFC_PIN_GROUP(msiof0_sync),
4572 SH_PFC_PIN_GROUP(msiof0_ss1),
4573 SH_PFC_PIN_GROUP(msiof0_ss2),
4574 SH_PFC_PIN_GROUP(msiof0_rx),
4575 SH_PFC_PIN_GROUP(msiof0_tx),
4576 SH_PFC_PIN_GROUP(msiof0_clk_b),
4577 SH_PFC_PIN_GROUP(msiof0_sync_b),
4578 SH_PFC_PIN_GROUP(msiof0_ss1_b),
4579 SH_PFC_PIN_GROUP(msiof0_ss2_b),
4580 SH_PFC_PIN_GROUP(msiof0_rx_b),
4581 SH_PFC_PIN_GROUP(msiof0_tx_b),
4582 SH_PFC_PIN_GROUP(msiof0_clk_c),
4583 SH_PFC_PIN_GROUP(msiof0_sync_c),
4584 SH_PFC_PIN_GROUP(msiof0_ss1_c),
4585 SH_PFC_PIN_GROUP(msiof0_ss2_c),
4586 SH_PFC_PIN_GROUP(msiof0_rx_c),
4587 SH_PFC_PIN_GROUP(msiof0_tx_c),
4588 SH_PFC_PIN_GROUP(msiof1_clk),
4589 SH_PFC_PIN_GROUP(msiof1_sync),
4590 SH_PFC_PIN_GROUP(msiof1_ss1),
4591 SH_PFC_PIN_GROUP(msiof1_ss2),
4592 SH_PFC_PIN_GROUP(msiof1_rx),
4593 SH_PFC_PIN_GROUP(msiof1_tx),
4594 SH_PFC_PIN_GROUP(msiof1_clk_b),
4595 SH_PFC_PIN_GROUP(msiof1_sync_b),
4596 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4597 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4598 SH_PFC_PIN_GROUP(msiof1_rx_b),
4599 SH_PFC_PIN_GROUP(msiof1_tx_b),
4600 SH_PFC_PIN_GROUP(msiof1_clk_c),
4601 SH_PFC_PIN_GROUP(msiof1_sync_c),
4602 SH_PFC_PIN_GROUP(msiof1_rx_c),
4603 SH_PFC_PIN_GROUP(msiof1_tx_c),
4604 SH_PFC_PIN_GROUP(msiof1_clk_d),
4605 SH_PFC_PIN_GROUP(msiof1_sync_d),
4606 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4607 SH_PFC_PIN_GROUP(msiof1_rx_d),
4608 SH_PFC_PIN_GROUP(msiof1_tx_d),
4609 SH_PFC_PIN_GROUP(msiof1_clk_e),
4610 SH_PFC_PIN_GROUP(msiof1_sync_e),
4611 SH_PFC_PIN_GROUP(msiof1_rx_e),
4612 SH_PFC_PIN_GROUP(msiof1_tx_e),
4613 SH_PFC_PIN_GROUP(msiof2_clk),
4614 SH_PFC_PIN_GROUP(msiof2_sync),
4615 SH_PFC_PIN_GROUP(msiof2_ss1),
4616 SH_PFC_PIN_GROUP(msiof2_ss2),
4617 SH_PFC_PIN_GROUP(msiof2_rx),
4618 SH_PFC_PIN_GROUP(msiof2_tx),
4619 SH_PFC_PIN_GROUP(msiof2_clk_b),
4620 SH_PFC_PIN_GROUP(msiof2_sync_b),
4621 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4622 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4623 SH_PFC_PIN_GROUP(msiof2_rx_b),
4624 SH_PFC_PIN_GROUP(msiof2_tx_b),
4625 SH_PFC_PIN_GROUP(msiof2_clk_c),
4626 SH_PFC_PIN_GROUP(msiof2_sync_c),
4627 SH_PFC_PIN_GROUP(msiof2_rx_c),
4628 SH_PFC_PIN_GROUP(msiof2_tx_c),
4629 SH_PFC_PIN_GROUP(msiof2_clk_d),
4630 SH_PFC_PIN_GROUP(msiof2_sync_d),
4631 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4632 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4633 SH_PFC_PIN_GROUP(msiof2_rx_d),
4634 SH_PFC_PIN_GROUP(msiof2_tx_d),
4635 SH_PFC_PIN_GROUP(msiof2_clk_e),
4636 SH_PFC_PIN_GROUP(msiof2_sync_e),
4637 SH_PFC_PIN_GROUP(msiof2_rx_e),
4638 SH_PFC_PIN_GROUP(msiof2_tx_e),
4639 SH_PFC_PIN_GROUP(pwm0),
4640 SH_PFC_PIN_GROUP(pwm0_b),
4641 SH_PFC_PIN_GROUP(pwm1),
4642 SH_PFC_PIN_GROUP(pwm1_b),
4643 SH_PFC_PIN_GROUP(pwm2),
4644 SH_PFC_PIN_GROUP(pwm2_b),
4645 SH_PFC_PIN_GROUP(pwm3),
4646 SH_PFC_PIN_GROUP(pwm4),
4647 SH_PFC_PIN_GROUP(pwm4_b),
4648 SH_PFC_PIN_GROUP(pwm5),
4649 SH_PFC_PIN_GROUP(pwm5_b),
4650 SH_PFC_PIN_GROUP(pwm6),
4651 SH_PFC_PIN_GROUP(qspi_ctrl),
4652 SH_PFC_PIN_GROUP(qspi_data2),
4653 SH_PFC_PIN_GROUP(qspi_data4),
4654 SH_PFC_PIN_GROUP(qspi_ctrl_b),
4655 SH_PFC_PIN_GROUP(qspi_data2_b),
4656 SH_PFC_PIN_GROUP(qspi_data4_b),
4657 SH_PFC_PIN_GROUP(scif0_data),
4658 SH_PFC_PIN_GROUP(scif0_data_b),
4659 SH_PFC_PIN_GROUP(scif0_data_c),
4660 SH_PFC_PIN_GROUP(scif0_data_d),
4661 SH_PFC_PIN_GROUP(scif0_data_e),
4662 SH_PFC_PIN_GROUP(scif1_data),
4663 SH_PFC_PIN_GROUP(scif1_data_b),
4664 SH_PFC_PIN_GROUP(scif1_clk_b),
4665 SH_PFC_PIN_GROUP(scif1_data_c),
4666 SH_PFC_PIN_GROUP(scif1_data_d),
4667 SH_PFC_PIN_GROUP(scif2_data),
4668 SH_PFC_PIN_GROUP(scif2_data_b),
4669 SH_PFC_PIN_GROUP(scif2_clk_b),
4670 SH_PFC_PIN_GROUP(scif2_data_c),
4671 SH_PFC_PIN_GROUP(scif2_data_e),
4672 SH_PFC_PIN_GROUP(scif3_data),
4673 SH_PFC_PIN_GROUP(scif3_clk),
4674 SH_PFC_PIN_GROUP(scif3_data_b),
4675 SH_PFC_PIN_GROUP(scif3_clk_b),
4676 SH_PFC_PIN_GROUP(scif3_data_c),
4677 SH_PFC_PIN_GROUP(scif3_data_d),
4678 SH_PFC_PIN_GROUP(scif4_data),
4679 SH_PFC_PIN_GROUP(scif4_data_b),
4680 SH_PFC_PIN_GROUP(scif4_data_c),
4681 SH_PFC_PIN_GROUP(scif5_data),
4682 SH_PFC_PIN_GROUP(scif5_data_b),
4683 SH_PFC_PIN_GROUP(scifa0_data),
4684 SH_PFC_PIN_GROUP(scifa0_data_b),
4685 SH_PFC_PIN_GROUP(scifa1_data),
4686 SH_PFC_PIN_GROUP(scifa1_clk),
4687 SH_PFC_PIN_GROUP(scifa1_data_b),
4688 SH_PFC_PIN_GROUP(scifa1_clk_b),
4689 SH_PFC_PIN_GROUP(scifa1_data_c),
4690 SH_PFC_PIN_GROUP(scifa2_data),
4691 SH_PFC_PIN_GROUP(scifa2_clk),
4692 SH_PFC_PIN_GROUP(scifa2_data_b),
4693 SH_PFC_PIN_GROUP(scifa3_data),
4694 SH_PFC_PIN_GROUP(scifa3_clk),
4695 SH_PFC_PIN_GROUP(scifa3_data_b),
4696 SH_PFC_PIN_GROUP(scifa3_clk_b),
4697 SH_PFC_PIN_GROUP(scifa3_data_c),
4698 SH_PFC_PIN_GROUP(scifa3_clk_c),
4699 SH_PFC_PIN_GROUP(scifa4_data),
4700 SH_PFC_PIN_GROUP(scifa4_data_b),
4701 SH_PFC_PIN_GROUP(scifa4_data_c),
4702 SH_PFC_PIN_GROUP(scifa5_data),
4703 SH_PFC_PIN_GROUP(scifa5_data_b),
4704 SH_PFC_PIN_GROUP(scifa5_data_c),
4705 SH_PFC_PIN_GROUP(scifb0_data),
4706 SH_PFC_PIN_GROUP(scifb0_clk),
4707 SH_PFC_PIN_GROUP(scifb0_ctrl),
4708 SH_PFC_PIN_GROUP(scifb0_data_b),
4709 SH_PFC_PIN_GROUP(scifb0_clk_b),
4710 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4711 SH_PFC_PIN_GROUP(scifb0_data_c),
4712 SH_PFC_PIN_GROUP(scifb0_clk_c),
4713 SH_PFC_PIN_GROUP(scifb0_data_d),
4714 SH_PFC_PIN_GROUP(scifb0_clk_d),
4715 SH_PFC_PIN_GROUP(scifb1_data),
4716 SH_PFC_PIN_GROUP(scifb1_clk),
4717 SH_PFC_PIN_GROUP(scifb1_ctrl),
4718 SH_PFC_PIN_GROUP(scifb1_data_b),
4719 SH_PFC_PIN_GROUP(scifb1_clk_b),
4720 SH_PFC_PIN_GROUP(scifb1_data_c),
4721 SH_PFC_PIN_GROUP(scifb1_clk_c),
4722 SH_PFC_PIN_GROUP(scifb1_data_d),
4723 SH_PFC_PIN_GROUP(scifb2_data),
4724 SH_PFC_PIN_GROUP(scifb2_clk),
4725 SH_PFC_PIN_GROUP(scifb2_ctrl),
4726 SH_PFC_PIN_GROUP(scifb2_data_b),
4727 SH_PFC_PIN_GROUP(scifb2_clk_b),
4728 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4729 SH_PFC_PIN_GROUP(scifb2_data_c),
4730 SH_PFC_PIN_GROUP(scifb2_clk_c),
4731 SH_PFC_PIN_GROUP(scifb2_data_d),
4732 SH_PFC_PIN_GROUP(scif_clk),
4733 SH_PFC_PIN_GROUP(scif_clk_b),
4734 SH_PFC_PIN_GROUP(sdhi0_data1),
4735 SH_PFC_PIN_GROUP(sdhi0_data4),
4736 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4737 SH_PFC_PIN_GROUP(sdhi0_cd),
4738 SH_PFC_PIN_GROUP(sdhi0_wp),
4739 SH_PFC_PIN_GROUP(sdhi1_data1),
4740 SH_PFC_PIN_GROUP(sdhi1_data4),
4741 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4742 SH_PFC_PIN_GROUP(sdhi1_cd),
4743 SH_PFC_PIN_GROUP(sdhi1_wp),
4744 SH_PFC_PIN_GROUP(sdhi2_data1),
4745 SH_PFC_PIN_GROUP(sdhi2_data4),
4746 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4747 SH_PFC_PIN_GROUP(sdhi2_cd),
4748 SH_PFC_PIN_GROUP(sdhi2_wp),
4749 SH_PFC_PIN_GROUP(ssi0_data),
4750 SH_PFC_PIN_GROUP(ssi0_data_b),
4751 SH_PFC_PIN_GROUP(ssi0129_ctrl),
4752 SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
4753 SH_PFC_PIN_GROUP(ssi1_data),
4754 SH_PFC_PIN_GROUP(ssi1_data_b),
4755 SH_PFC_PIN_GROUP(ssi1_ctrl),
4756 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4757 SH_PFC_PIN_GROUP(ssi2_data),
4758 SH_PFC_PIN_GROUP(ssi2_ctrl),
4759 SH_PFC_PIN_GROUP(ssi3_data),
4760 SH_PFC_PIN_GROUP(ssi34_ctrl),
4761 SH_PFC_PIN_GROUP(ssi4_data),
4762 SH_PFC_PIN_GROUP(ssi4_ctrl),
4763 SH_PFC_PIN_GROUP(ssi5_data),
4764 SH_PFC_PIN_GROUP(ssi5_ctrl),
4765 SH_PFC_PIN_GROUP(ssi6_data),
4766 SH_PFC_PIN_GROUP(ssi6_ctrl),
4767 SH_PFC_PIN_GROUP(ssi7_data),
4768 SH_PFC_PIN_GROUP(ssi7_data_b),
4769 SH_PFC_PIN_GROUP(ssi78_ctrl),
4770 SH_PFC_PIN_GROUP(ssi78_ctrl_b),
4771 SH_PFC_PIN_GROUP(ssi8_data),
4772 SH_PFC_PIN_GROUP(ssi8_data_b),
4773 SH_PFC_PIN_GROUP(ssi9_data),
4774 SH_PFC_PIN_GROUP(ssi9_data_b),
4775 SH_PFC_PIN_GROUP(ssi9_ctrl),
4776 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4777 SH_PFC_PIN_GROUP(tpu_to0),
4778 SH_PFC_PIN_GROUP(tpu_to1),
4779 SH_PFC_PIN_GROUP(tpu_to2),
4780 SH_PFC_PIN_GROUP(tpu_to3),
4781 SH_PFC_PIN_GROUP(usb0),
4782 SH_PFC_PIN_GROUP(usb1),
4783 VIN_DATA_PIN_GROUP(vin0_data, 24),
4784 VIN_DATA_PIN_GROUP(vin0_data, 20),
4785 SH_PFC_PIN_GROUP(vin0_data18),
4786 VIN_DATA_PIN_GROUP(vin0_data, 16),
4787 VIN_DATA_PIN_GROUP(vin0_data, 12),
4788 VIN_DATA_PIN_GROUP(vin0_data, 10),
4789 VIN_DATA_PIN_GROUP(vin0_data, 8),
4790 SH_PFC_PIN_GROUP(vin0_sync),
4791 SH_PFC_PIN_GROUP(vin0_field),
4792 SH_PFC_PIN_GROUP(vin0_clkenb),
4793 SH_PFC_PIN_GROUP(vin0_clk),
4794 SH_PFC_PIN_GROUP(vin1_data8),
4795 SH_PFC_PIN_GROUP(vin1_sync),
4796 SH_PFC_PIN_GROUP(vin1_field),
4797 SH_PFC_PIN_GROUP(vin1_clkenb),
4798 SH_PFC_PIN_GROUP(vin1_clk),
4799 VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
4800 VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
4801 SH_PFC_PIN_GROUP(vin1_data18_b),
4802 VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
4803 VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
4804 VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
4805 VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
4806 SH_PFC_PIN_GROUP(vin1_sync_b),
4807 SH_PFC_PIN_GROUP(vin1_field_b),
4808 SH_PFC_PIN_GROUP(vin1_clkenb_b),
4809 SH_PFC_PIN_GROUP(vin1_clk_b),
4810 SH_PFC_PIN_GROUP(vin2_data8),
4811 SH_PFC_PIN_GROUP(vin2_sync),
4812 SH_PFC_PIN_GROUP(vin2_field),
4813 SH_PFC_PIN_GROUP(vin2_clkenb),
4814 SH_PFC_PIN_GROUP(vin2_clk),
4815 },
4816 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4817 .automotive = {
4818 SH_PFC_PIN_GROUP(adi_common),
4819 SH_PFC_PIN_GROUP(adi_chsel0),
4820 SH_PFC_PIN_GROUP(adi_chsel1),
4821 SH_PFC_PIN_GROUP(adi_chsel2),
4822 SH_PFC_PIN_GROUP(adi_common_b),
4823 SH_PFC_PIN_GROUP(adi_chsel0_b),
4824 SH_PFC_PIN_GROUP(adi_chsel1_b),
4825 SH_PFC_PIN_GROUP(adi_chsel2_b),
4826 SH_PFC_PIN_GROUP(mlb_3pin),
4827 }
4828 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
4829 };
4830
4831 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
4832 static const char * const adi_groups[] = {
4833 "adi_common",
4834 "adi_chsel0",
4835 "adi_chsel1",
4836 "adi_chsel2",
4837 "adi_common_b",
4838 "adi_chsel0_b",
4839 "adi_chsel1_b",
4840 "adi_chsel2_b",
4841 };
4842 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
4843
4844 static const char * const audio_clk_groups[] = {
4845 "audio_clk_a",
4846 "audio_clk_b",
4847 "audio_clk_b_b",
4848 "audio_clk_c",
4849 "audio_clkout",
4850 };
4851
4852 static const char * const avb_groups[] = {
4853 "avb_link",
4854 "avb_magic",
4855 "avb_phy_int",
4856 "avb_mdio",
4857 "avb_mii",
4858 "avb_gmii",
4859 };
4860
4861 static const char * const can0_groups[] = {
4862 "can0_data",
4863 "can0_data_b",
4864 "can0_data_c",
4865 "can0_data_d",
4866 "can0_data_e",
4867 "can0_data_f",
4868 /*
4869 * Retained for backwards compatibility, use can_clk_groups in new
4870 * designs.
4871 */
4872 "can_clk",
4873 "can_clk_b",
4874 "can_clk_c",
4875 "can_clk_d",
4876 };
4877
4878 static const char * const can1_groups[] = {
4879 "can1_data",
4880 "can1_data_b",
4881 "can1_data_c",
4882 "can1_data_d",
4883 /*
4884 * Retained for backwards compatibility, use can_clk_groups in new
4885 * designs.
4886 */
4887 "can_clk",
4888 "can_clk_b",
4889 "can_clk_c",
4890 "can_clk_d",
4891 };
4892
4893 /*
4894 * can_clk_groups allows for independent configuration, use can_clk function
4895 * in new designs.
4896 */
4897 static const char * const can_clk_groups[] = {
4898 "can_clk",
4899 "can_clk_b",
4900 "can_clk_c",
4901 "can_clk_d",
4902 };
4903
4904 static const char * const du_groups[] = {
4905 "du_rgb666",
4906 "du_rgb888",
4907 "du_clk_out_0",
4908 "du_clk_out_1",
4909 "du_sync",
4910 "du_oddf",
4911 "du_cde",
4912 "du_disp",
4913 };
4914
4915 static const char * const du0_groups[] = {
4916 "du0_clk_in",
4917 };
4918
4919 static const char * const du1_groups[] = {
4920 "du1_clk_in",
4921 "du1_clk_in_b",
4922 "du1_clk_in_c",
4923 };
4924
4925 static const char * const eth_groups[] = {
4926 "eth_link",
4927 "eth_magic",
4928 "eth_mdio",
4929 "eth_rmii",
4930 };
4931
4932 static const char * const hscif0_groups[] = {
4933 "hscif0_data",
4934 "hscif0_clk",
4935 "hscif0_ctrl",
4936 "hscif0_data_b",
4937 "hscif0_ctrl_b",
4938 "hscif0_data_c",
4939 "hscif0_clk_c",
4940 };
4941
4942 static const char * const hscif1_groups[] = {
4943 "hscif1_data",
4944 "hscif1_clk",
4945 "hscif1_ctrl",
4946 "hscif1_data_b",
4947 "hscif1_data_c",
4948 "hscif1_clk_c",
4949 "hscif1_ctrl_c",
4950 "hscif1_data_d",
4951 "hscif1_data_e",
4952 "hscif1_clk_e",
4953 "hscif1_ctrl_e",
4954 };
4955
4956 static const char * const hscif2_groups[] = {
4957 "hscif2_data",
4958 "hscif2_clk",
4959 "hscif2_ctrl",
4960 "hscif2_data_b",
4961 "hscif2_ctrl_b",
4962 "hscif2_data_c",
4963 "hscif2_clk_c",
4964 "hscif2_data_d",
4965 };
4966
4967 static const char * const i2c0_groups[] = {
4968 "i2c0",
4969 "i2c0_b",
4970 "i2c0_c",
4971 };
4972
4973 static const char * const i2c1_groups[] = {
4974 "i2c1",
4975 "i2c1_b",
4976 "i2c1_c",
4977 "i2c1_d",
4978 "i2c1_e",
4979 };
4980
4981 static const char * const i2c2_groups[] = {
4982 "i2c2",
4983 "i2c2_b",
4984 "i2c2_c",
4985 "i2c2_d",
4986 };
4987
4988 static const char * const i2c3_groups[] = {
4989 "i2c3",
4990 "i2c3_b",
4991 "i2c3_c",
4992 "i2c3_d",
4993 };
4994
4995 static const char * const i2c4_groups[] = {
4996 "i2c4",
4997 "i2c4_b",
4998 "i2c4_c",
4999 };
5000
5001 static const char * const i2c7_groups[] = {
5002 "i2c7",
5003 "i2c7_b",
5004 "i2c7_c",
5005 };
5006
5007 static const char * const i2c8_groups[] = {
5008 "i2c8",
5009 "i2c8_b",
5010 "i2c8_c",
5011 };
5012
5013 static const char * const intc_groups[] = {
5014 "intc_irq0",
5015 "intc_irq1",
5016 "intc_irq2",
5017 "intc_irq3",
5018 };
5019
5020 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
5021 static const char * const mlb_groups[] = {
5022 "mlb_3pin",
5023 };
5024 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
5025
5026 static const char * const mmc_groups[] = {
5027 "mmc_data1",
5028 "mmc_data4",
5029 "mmc_data8",
5030 "mmc_data8_b",
5031 "mmc_ctrl",
5032 };
5033
5034 static const char * const msiof0_groups[] = {
5035 "msiof0_clk",
5036 "msiof0_sync",
5037 "msiof0_ss1",
5038 "msiof0_ss2",
5039 "msiof0_rx",
5040 "msiof0_tx",
5041 "msiof0_clk_b",
5042 "msiof0_sync_b",
5043 "msiof0_ss1_b",
5044 "msiof0_ss2_b",
5045 "msiof0_rx_b",
5046 "msiof0_tx_b",
5047 "msiof0_clk_c",
5048 "msiof0_sync_c",
5049 "msiof0_ss1_c",
5050 "msiof0_ss2_c",
5051 "msiof0_rx_c",
5052 "msiof0_tx_c",
5053 };
5054
5055 static const char * const msiof1_groups[] = {
5056 "msiof1_clk",
5057 "msiof1_sync",
5058 "msiof1_ss1",
5059 "msiof1_ss2",
5060 "msiof1_rx",
5061 "msiof1_tx",
5062 "msiof1_clk_b",
5063 "msiof1_sync_b",
5064 "msiof1_ss1_b",
5065 "msiof1_ss2_b",
5066 "msiof1_rx_b",
5067 "msiof1_tx_b",
5068 "msiof1_clk_c",
5069 "msiof1_sync_c",
5070 "msiof1_rx_c",
5071 "msiof1_tx_c",
5072 "msiof1_clk_d",
5073 "msiof1_sync_d",
5074 "msiof1_ss1_d",
5075 "msiof1_rx_d",
5076 "msiof1_tx_d",
5077 "msiof1_clk_e",
5078 "msiof1_sync_e",
5079 "msiof1_rx_e",
5080 "msiof1_tx_e",
5081 };
5082
5083 static const char * const msiof2_groups[] = {
5084 "msiof2_clk",
5085 "msiof2_sync",
5086 "msiof2_ss1",
5087 "msiof2_ss2",
5088 "msiof2_rx",
5089 "msiof2_tx",
5090 "msiof2_clk_b",
5091 "msiof2_sync_b",
5092 "msiof2_ss1_b",
5093 "msiof2_ss2_b",
5094 "msiof2_rx_b",
5095 "msiof2_tx_b",
5096 "msiof2_clk_c",
5097 "msiof2_sync_c",
5098 "msiof2_rx_c",
5099 "msiof2_tx_c",
5100 "msiof2_clk_d",
5101 "msiof2_sync_d",
5102 "msiof2_ss1_d",
5103 "msiof2_ss2_d",
5104 "msiof2_rx_d",
5105 "msiof2_tx_d",
5106 "msiof2_clk_e",
5107 "msiof2_sync_e",
5108 "msiof2_rx_e",
5109 "msiof2_tx_e",
5110 };
5111
5112 static const char * const pwm0_groups[] = {
5113 "pwm0",
5114 "pwm0_b",
5115 };
5116
5117 static const char * const pwm1_groups[] = {
5118 "pwm1",
5119 "pwm1_b",
5120 };
5121
5122 static const char * const pwm2_groups[] = {
5123 "pwm2",
5124 "pwm2_b",
5125 };
5126
5127 static const char * const pwm3_groups[] = {
5128 "pwm3",
5129 };
5130
5131 static const char * const pwm4_groups[] = {
5132 "pwm4",
5133 "pwm4_b",
5134 };
5135
5136 static const char * const pwm5_groups[] = {
5137 "pwm5",
5138 "pwm5_b",
5139 };
5140
5141 static const char * const pwm6_groups[] = {
5142 "pwm6",
5143 };
5144
5145 static const char * const qspi_groups[] = {
5146 "qspi_ctrl",
5147 "qspi_data2",
5148 "qspi_data4",
5149 "qspi_ctrl_b",
5150 "qspi_data2_b",
5151 "qspi_data4_b",
5152 };
5153
5154 static const char * const scif0_groups[] = {
5155 "scif0_data",
5156 "scif0_data_b",
5157 "scif0_data_c",
5158 "scif0_data_d",
5159 "scif0_data_e",
5160 };
5161
5162 static const char * const scif1_groups[] = {
5163 "scif1_data",
5164 "scif1_data_b",
5165 "scif1_clk_b",
5166 "scif1_data_c",
5167 "scif1_data_d",
5168 };
5169
5170 static const char * const scif2_groups[] = {
5171 "scif2_data",
5172 "scif2_data_b",
5173 "scif2_clk_b",
5174 "scif2_data_c",
5175 "scif2_data_e",
5176 };
5177 static const char * const scif3_groups[] = {
5178 "scif3_data",
5179 "scif3_clk",
5180 "scif3_data_b",
5181 "scif3_clk_b",
5182 "scif3_data_c",
5183 "scif3_data_d",
5184 };
5185 static const char * const scif4_groups[] = {
5186 "scif4_data",
5187 "scif4_data_b",
5188 "scif4_data_c",
5189 };
5190 static const char * const scif5_groups[] = {
5191 "scif5_data",
5192 "scif5_data_b",
5193 };
5194 static const char * const scifa0_groups[] = {
5195 "scifa0_data",
5196 "scifa0_data_b",
5197 };
5198 static const char * const scifa1_groups[] = {
5199 "scifa1_data",
5200 "scifa1_clk",
5201 "scifa1_data_b",
5202 "scifa1_clk_b",
5203 "scifa1_data_c",
5204 };
5205 static const char * const scifa2_groups[] = {
5206 "scifa2_data",
5207 "scifa2_clk",
5208 "scifa2_data_b",
5209 };
5210 static const char * const scifa3_groups[] = {
5211 "scifa3_data",
5212 "scifa3_clk",
5213 "scifa3_data_b",
5214 "scifa3_clk_b",
5215 "scifa3_data_c",
5216 "scifa3_clk_c",
5217 };
5218 static const char * const scifa4_groups[] = {
5219 "scifa4_data",
5220 "scifa4_data_b",
5221 "scifa4_data_c",
5222 };
5223 static const char * const scifa5_groups[] = {
5224 "scifa5_data",
5225 "scifa5_data_b",
5226 "scifa5_data_c",
5227 };
5228 static const char * const scifb0_groups[] = {
5229 "scifb0_data",
5230 "scifb0_clk",
5231 "scifb0_ctrl",
5232 "scifb0_data_b",
5233 "scifb0_clk_b",
5234 "scifb0_ctrl_b",
5235 "scifb0_data_c",
5236 "scifb0_clk_c",
5237 "scifb0_data_d",
5238 "scifb0_clk_d",
5239 };
5240 static const char * const scifb1_groups[] = {
5241 "scifb1_data",
5242 "scifb1_clk",
5243 "scifb1_ctrl",
5244 "scifb1_data_b",
5245 "scifb1_clk_b",
5246 "scifb1_data_c",
5247 "scifb1_clk_c",
5248 "scifb1_data_d",
5249 };
5250 static const char * const scifb2_groups[] = {
5251 "scifb2_data",
5252 "scifb2_clk",
5253 "scifb2_ctrl",
5254 "scifb2_data_b",
5255 "scifb2_clk_b",
5256 "scifb2_ctrl_b",
5257 "scifb2_data_c",
5258 "scifb2_clk_c",
5259 "scifb2_data_d",
5260 };
5261
5262 static const char * const scif_clk_groups[] = {
5263 "scif_clk",
5264 "scif_clk_b",
5265 };
5266
5267 static const char * const sdhi0_groups[] = {
5268 "sdhi0_data1",
5269 "sdhi0_data4",
5270 "sdhi0_ctrl",
5271 "sdhi0_cd",
5272 "sdhi0_wp",
5273 };
5274
5275 static const char * const sdhi1_groups[] = {
5276 "sdhi1_data1",
5277 "sdhi1_data4",
5278 "sdhi1_ctrl",
5279 "sdhi1_cd",
5280 "sdhi1_wp",
5281 };
5282
5283 static const char * const sdhi2_groups[] = {
5284 "sdhi2_data1",
5285 "sdhi2_data4",
5286 "sdhi2_ctrl",
5287 "sdhi2_cd",
5288 "sdhi2_wp",
5289 };
5290
5291 static const char * const ssi_groups[] = {
5292 "ssi0_data",
5293 "ssi0_data_b",
5294 "ssi0129_ctrl",
5295 "ssi0129_ctrl_b",
5296 "ssi1_data",
5297 "ssi1_data_b",
5298 "ssi1_ctrl",
5299 "ssi1_ctrl_b",
5300 "ssi2_data",
5301 "ssi2_ctrl",
5302 "ssi3_data",
5303 "ssi34_ctrl",
5304 "ssi4_data",
5305 "ssi4_ctrl",
5306 "ssi5_data",
5307 "ssi5_ctrl",
5308 "ssi6_data",
5309 "ssi6_ctrl",
5310 "ssi7_data",
5311 "ssi7_data_b",
5312 "ssi78_ctrl",
5313 "ssi78_ctrl_b",
5314 "ssi8_data",
5315 "ssi8_data_b",
5316 "ssi9_data",
5317 "ssi9_data_b",
5318 "ssi9_ctrl",
5319 "ssi9_ctrl_b",
5320 };
5321
5322 static const char * const tpu_groups[] = {
5323 "tpu_to0",
5324 "tpu_to1",
5325 "tpu_to2",
5326 "tpu_to3",
5327 };
5328
5329 static const char * const usb0_groups[] = {
5330 "usb0",
5331 };
5332 static const char * const usb1_groups[] = {
5333 "usb1",
5334 };
5335
5336 static const char * const vin0_groups[] = {
5337 "vin0_data24",
5338 "vin0_data20",
5339 "vin0_data18",
5340 "vin0_data16",
5341 "vin0_data12",
5342 "vin0_data10",
5343 "vin0_data8",
5344 "vin0_sync",
5345 "vin0_field",
5346 "vin0_clkenb",
5347 "vin0_clk",
5348 };
5349
5350 static const char * const vin1_groups[] = {
5351 "vin1_data8",
5352 "vin1_sync",
5353 "vin1_field",
5354 "vin1_clkenb",
5355 "vin1_clk",
5356 "vin1_data24_b",
5357 "vin1_data20_b",
5358 "vin1_data18_b",
5359 "vin1_data16_b",
5360 "vin1_data12_b",
5361 "vin1_data10_b",
5362 "vin1_data8_b",
5363 "vin1_sync_b",
5364 "vin1_field_b",
5365 "vin1_clkenb_b",
5366 "vin1_clk_b",
5367 };
5368
5369 static const char * const vin2_groups[] = {
5370 "vin2_data8",
5371 "vin2_sync",
5372 "vin2_field",
5373 "vin2_clkenb",
5374 "vin2_clk",
5375 };
5376
5377 static const struct {
5378 struct sh_pfc_function common[58];
5379 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
5380 struct sh_pfc_function automotive[2];
5381 #endif
5382 } pinmux_functions = {
5383 .common = {
5384 SH_PFC_FUNCTION(audio_clk),
5385 SH_PFC_FUNCTION(avb),
5386 SH_PFC_FUNCTION(can0),
5387 SH_PFC_FUNCTION(can1),
5388 SH_PFC_FUNCTION(can_clk),
5389 SH_PFC_FUNCTION(du),
5390 SH_PFC_FUNCTION(du0),
5391 SH_PFC_FUNCTION(du1),
5392 SH_PFC_FUNCTION(eth),
5393 SH_PFC_FUNCTION(hscif0),
5394 SH_PFC_FUNCTION(hscif1),
5395 SH_PFC_FUNCTION(hscif2),
5396 SH_PFC_FUNCTION(i2c0),
5397 SH_PFC_FUNCTION(i2c1),
5398 SH_PFC_FUNCTION(i2c2),
5399 SH_PFC_FUNCTION(i2c3),
5400 SH_PFC_FUNCTION(i2c4),
5401 SH_PFC_FUNCTION(i2c7),
5402 SH_PFC_FUNCTION(i2c8),
5403 SH_PFC_FUNCTION(intc),
5404 SH_PFC_FUNCTION(mmc),
5405 SH_PFC_FUNCTION(msiof0),
5406 SH_PFC_FUNCTION(msiof1),
5407 SH_PFC_FUNCTION(msiof2),
5408 SH_PFC_FUNCTION(pwm0),
5409 SH_PFC_FUNCTION(pwm1),
5410 SH_PFC_FUNCTION(pwm2),
5411 SH_PFC_FUNCTION(pwm3),
5412 SH_PFC_FUNCTION(pwm4),
5413 SH_PFC_FUNCTION(pwm5),
5414 SH_PFC_FUNCTION(pwm6),
5415 SH_PFC_FUNCTION(qspi),
5416 SH_PFC_FUNCTION(scif0),
5417 SH_PFC_FUNCTION(scif1),
5418 SH_PFC_FUNCTION(scif2),
5419 SH_PFC_FUNCTION(scif3),
5420 SH_PFC_FUNCTION(scif4),
5421 SH_PFC_FUNCTION(scif5),
5422 SH_PFC_FUNCTION(scifa0),
5423 SH_PFC_FUNCTION(scifa1),
5424 SH_PFC_FUNCTION(scifa2),
5425 SH_PFC_FUNCTION(scifa3),
5426 SH_PFC_FUNCTION(scifa4),
5427 SH_PFC_FUNCTION(scifa5),
5428 SH_PFC_FUNCTION(scifb0),
5429 SH_PFC_FUNCTION(scifb1),
5430 SH_PFC_FUNCTION(scifb2),
5431 SH_PFC_FUNCTION(scif_clk),
5432 SH_PFC_FUNCTION(sdhi0),
5433 SH_PFC_FUNCTION(sdhi1),
5434 SH_PFC_FUNCTION(sdhi2),
5435 SH_PFC_FUNCTION(ssi),
5436 SH_PFC_FUNCTION(tpu),
5437 SH_PFC_FUNCTION(usb0),
5438 SH_PFC_FUNCTION(usb1),
5439 SH_PFC_FUNCTION(vin0),
5440 SH_PFC_FUNCTION(vin1),
5441 SH_PFC_FUNCTION(vin2),
5442 },
5443 #if defined(CONFIG_PINCTRL_PFC_R8A7791) || defined(CONFIG_PINCTRL_PFC_R8A7793)
5444 .automotive = {
5445 SH_PFC_FUNCTION(adi),
5446 SH_PFC_FUNCTION(mlb),
5447 }
5448 #endif /* CONFIG_PINCTRL_PFC_R8A7791 || CONFIG_PINCTRL_PFC_R8A7793 */
5449 };
5450
5451 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5452 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
5453 GP_0_31_FN, FN_IP1_22_20,
5454 GP_0_30_FN, FN_IP1_19_17,
5455 GP_0_29_FN, FN_IP1_16_14,
5456 GP_0_28_FN, FN_IP1_13_11,
5457 GP_0_27_FN, FN_IP1_10_8,
5458 GP_0_26_FN, FN_IP1_7_6,
5459 GP_0_25_FN, FN_IP1_5_4,
5460 GP_0_24_FN, FN_IP1_3_2,
5461 GP_0_23_FN, FN_IP1_1_0,
5462 GP_0_22_FN, FN_IP0_30_29,
5463 GP_0_21_FN, FN_IP0_28_27,
5464 GP_0_20_FN, FN_IP0_26_25,
5465 GP_0_19_FN, FN_IP0_24_23,
5466 GP_0_18_FN, FN_IP0_22_21,
5467 GP_0_17_FN, FN_IP0_20_19,
5468 GP_0_16_FN, FN_IP0_18_16,
5469 GP_0_15_FN, FN_IP0_15,
5470 GP_0_14_FN, FN_IP0_14,
5471 GP_0_13_FN, FN_IP0_13,
5472 GP_0_12_FN, FN_IP0_12,
5473 GP_0_11_FN, FN_IP0_11,
5474 GP_0_10_FN, FN_IP0_10,
5475 GP_0_9_FN, FN_IP0_9,
5476 GP_0_8_FN, FN_IP0_8,
5477 GP_0_7_FN, FN_IP0_7,
5478 GP_0_6_FN, FN_IP0_6,
5479 GP_0_5_FN, FN_IP0_5,
5480 GP_0_4_FN, FN_IP0_4,
5481 GP_0_3_FN, FN_IP0_3,
5482 GP_0_2_FN, FN_IP0_2,
5483 GP_0_1_FN, FN_IP0_1,
5484 GP_0_0_FN, FN_IP0_0, ))
5485 },
5486 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
5487 0, 0,
5488 0, 0,
5489 0, 0,
5490 0, 0,
5491 0, 0,
5492 0, 0,
5493 GP_1_25_FN, FN_IP3_21_20,
5494 GP_1_24_FN, FN_IP3_19_18,
5495 GP_1_23_FN, FN_IP3_17_16,
5496 GP_1_22_FN, FN_IP3_15_14,
5497 GP_1_21_FN, FN_IP3_13_12,
5498 GP_1_20_FN, FN_IP3_11_9,
5499 GP_1_19_FN, FN_RD_N,
5500 GP_1_18_FN, FN_IP3_8_6,
5501 GP_1_17_FN, FN_IP3_5_3,
5502 GP_1_16_FN, FN_IP3_2_0,
5503 GP_1_15_FN, FN_IP2_29_27,
5504 GP_1_14_FN, FN_IP2_26_25,
5505 GP_1_13_FN, FN_IP2_24_23,
5506 GP_1_12_FN, FN_EX_CS0_N,
5507 GP_1_11_FN, FN_IP2_22_21,
5508 GP_1_10_FN, FN_IP2_20_19,
5509 GP_1_9_FN, FN_IP2_18_16,
5510 GP_1_8_FN, FN_IP2_15_13,
5511 GP_1_7_FN, FN_IP2_12_10,
5512 GP_1_6_FN, FN_IP2_9_7,
5513 GP_1_5_FN, FN_IP2_6_5,
5514 GP_1_4_FN, FN_IP2_4_3,
5515 GP_1_3_FN, FN_IP2_2_0,
5516 GP_1_2_FN, FN_IP1_31_29,
5517 GP_1_1_FN, FN_IP1_28_26,
5518 GP_1_0_FN, FN_IP1_25_23, ))
5519 },
5520 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
5521 GP_2_31_FN, FN_IP6_7_6,
5522 GP_2_30_FN, FN_IP6_5_3,
5523 GP_2_29_FN, FN_IP6_2_0,
5524 GP_2_28_FN, FN_AUDIO_CLKA,
5525 GP_2_27_FN, FN_IP5_31_29,
5526 GP_2_26_FN, FN_IP5_28_26,
5527 GP_2_25_FN, FN_IP5_25_24,
5528 GP_2_24_FN, FN_IP5_23_22,
5529 GP_2_23_FN, FN_IP5_21_20,
5530 GP_2_22_FN, FN_IP5_19_17,
5531 GP_2_21_FN, FN_IP5_16_15,
5532 GP_2_20_FN, FN_IP5_14_12,
5533 GP_2_19_FN, FN_IP5_11_9,
5534 GP_2_18_FN, FN_IP5_8_6,
5535 GP_2_17_FN, FN_IP5_5_3,
5536 GP_2_16_FN, FN_IP5_2_0,
5537 GP_2_15_FN, FN_IP4_30_28,
5538 GP_2_14_FN, FN_IP4_27_26,
5539 GP_2_13_FN, FN_IP4_25_24,
5540 GP_2_12_FN, FN_IP4_23_22,
5541 GP_2_11_FN, FN_IP4_21,
5542 GP_2_10_FN, FN_IP4_20,
5543 GP_2_9_FN, FN_IP4_19,
5544 GP_2_8_FN, FN_IP4_18_16,
5545 GP_2_7_FN, FN_IP4_15_13,
5546 GP_2_6_FN, FN_IP4_12_10,
5547 GP_2_5_FN, FN_IP4_9_8,
5548 GP_2_4_FN, FN_IP4_7_5,
5549 GP_2_3_FN, FN_IP4_4_2,
5550 GP_2_2_FN, FN_IP4_1_0,
5551 GP_2_1_FN, FN_IP3_30_28,
5552 GP_2_0_FN, FN_IP3_27_25 ))
5553 },
5554 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
5555 GP_3_31_FN, FN_IP9_18_17,
5556 GP_3_30_FN, FN_IP9_16,
5557 GP_3_29_FN, FN_IP9_15_13,
5558 GP_3_28_FN, FN_IP9_12,
5559 GP_3_27_FN, FN_IP9_11,
5560 GP_3_26_FN, FN_IP9_10_8,
5561 GP_3_25_FN, FN_IP9_7,
5562 GP_3_24_FN, FN_IP9_6,
5563 GP_3_23_FN, FN_IP9_5_3,
5564 GP_3_22_FN, FN_IP9_2_0,
5565 GP_3_21_FN, FN_IP8_30_28,
5566 GP_3_20_FN, FN_IP8_27_26,
5567 GP_3_19_FN, FN_IP8_25_24,
5568 GP_3_18_FN, FN_IP8_23_21,
5569 GP_3_17_FN, FN_IP8_20_18,
5570 GP_3_16_FN, FN_IP8_17_15,
5571 GP_3_15_FN, FN_IP8_14_12,
5572 GP_3_14_FN, FN_IP8_11_9,
5573 GP_3_13_FN, FN_IP8_8_6,
5574 GP_3_12_FN, FN_IP8_5_3,
5575 GP_3_11_FN, FN_IP8_2_0,
5576 GP_3_10_FN, FN_IP7_29_27,
5577 GP_3_9_FN, FN_IP7_26_24,
5578 GP_3_8_FN, FN_IP7_23_21,
5579 GP_3_7_FN, FN_IP7_20_19,
5580 GP_3_6_FN, FN_IP7_18_17,
5581 GP_3_5_FN, FN_IP7_16_15,
5582 GP_3_4_FN, FN_IP7_14_13,
5583 GP_3_3_FN, FN_IP7_12_11,
5584 GP_3_2_FN, FN_IP7_10_9,
5585 GP_3_1_FN, FN_IP7_8_6,
5586 GP_3_0_FN, FN_IP7_5_3 ))
5587 },
5588 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
5589 GP_4_31_FN, FN_IP15_5_4,
5590 GP_4_30_FN, FN_IP15_3_2,
5591 GP_4_29_FN, FN_IP15_1_0,
5592 GP_4_28_FN, FN_IP11_8_6,
5593 GP_4_27_FN, FN_IP11_5_3,
5594 GP_4_26_FN, FN_IP11_2_0,
5595 GP_4_25_FN, FN_IP10_31_29,
5596 GP_4_24_FN, FN_IP10_28_27,
5597 GP_4_23_FN, FN_IP10_26_25,
5598 GP_4_22_FN, FN_IP10_24_22,
5599 GP_4_21_FN, FN_IP10_21_19,
5600 GP_4_20_FN, FN_IP10_18_17,
5601 GP_4_19_FN, FN_IP10_16_15,
5602 GP_4_18_FN, FN_IP10_14_12,
5603 GP_4_17_FN, FN_IP10_11_9,
5604 GP_4_16_FN, FN_IP10_8_6,
5605 GP_4_15_FN, FN_IP10_5_3,
5606 GP_4_14_FN, FN_IP10_2_0,
5607 GP_4_13_FN, FN_IP9_31_29,
5608 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
5609 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
5610 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
5611 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
5612 GP_4_8_FN, FN_IP9_28_27,
5613 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
5614 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
5615 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
5616 GP_4_4_FN, FN_IP9_26_25,
5617 GP_4_3_FN, FN_IP9_24_23,
5618 GP_4_2_FN, FN_IP9_22_21,
5619 GP_4_1_FN, FN_IP9_20_19,
5620 GP_4_0_FN, FN_VI0_CLK ))
5621 },
5622 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
5623 GP_5_31_FN, FN_IP3_24_22,
5624 GP_5_30_FN, FN_IP13_9_7,
5625 GP_5_29_FN, FN_IP13_6_5,
5626 GP_5_28_FN, FN_IP13_4_3,
5627 GP_5_27_FN, FN_IP13_2_0,
5628 GP_5_26_FN, FN_IP12_29_27,
5629 GP_5_25_FN, FN_IP12_26_24,
5630 GP_5_24_FN, FN_IP12_23_22,
5631 GP_5_23_FN, FN_IP12_21_20,
5632 GP_5_22_FN, FN_IP12_19_18,
5633 GP_5_21_FN, FN_IP12_17_16,
5634 GP_5_20_FN, FN_IP12_15_13,
5635 GP_5_19_FN, FN_IP12_12_10,
5636 GP_5_18_FN, FN_IP12_9_7,
5637 GP_5_17_FN, FN_IP12_6_4,
5638 GP_5_16_FN, FN_IP12_3_2,
5639 GP_5_15_FN, FN_IP12_1_0,
5640 GP_5_14_FN, FN_IP11_31_30,
5641 GP_5_13_FN, FN_IP11_29_28,
5642 GP_5_12_FN, FN_IP11_27,
5643 GP_5_11_FN, FN_IP11_26,
5644 GP_5_10_FN, FN_IP11_25,
5645 GP_5_9_FN, FN_IP11_24,
5646 GP_5_8_FN, FN_IP11_23,
5647 GP_5_7_FN, FN_IP11_22,
5648 GP_5_6_FN, FN_IP11_21,
5649 GP_5_5_FN, FN_IP11_20,
5650 GP_5_4_FN, FN_IP11_19,
5651 GP_5_3_FN, FN_IP11_18_17,
5652 GP_5_2_FN, FN_IP11_16_15,
5653 GP_5_1_FN, FN_IP11_14_12,
5654 GP_5_0_FN, FN_IP11_11_9 ))
5655 },
5656 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
5657 GP_6_31_FN, FN_DU0_DOTCLKIN,
5658 GP_6_30_FN, FN_USB1_OVC,
5659 GP_6_29_FN, FN_IP14_31_29,
5660 GP_6_28_FN, FN_IP14_28_26,
5661 GP_6_27_FN, FN_IP14_25_23,
5662 GP_6_26_FN, FN_IP14_22_20,
5663 GP_6_25_FN, FN_IP14_19_17,
5664 GP_6_24_FN, FN_IP14_16_14,
5665 GP_6_23_FN, FN_IP14_13_11,
5666 GP_6_22_FN, FN_IP14_10_8,
5667 GP_6_21_FN, FN_IP14_7,
5668 GP_6_20_FN, FN_IP14_6,
5669 GP_6_19_FN, FN_IP14_5,
5670 GP_6_18_FN, FN_IP14_4,
5671 GP_6_17_FN, FN_IP14_3,
5672 GP_6_16_FN, FN_IP14_2,
5673 GP_6_15_FN, FN_IP14_1_0,
5674 GP_6_14_FN, FN_IP13_30_28,
5675 GP_6_13_FN, FN_IP13_27,
5676 GP_6_12_FN, FN_IP13_26,
5677 GP_6_11_FN, FN_IP13_25,
5678 GP_6_10_FN, FN_IP13_24_23,
5679 GP_6_9_FN, FN_IP13_22,
5680 GP_6_8_FN, FN_SD1_CLK,
5681 GP_6_7_FN, FN_IP13_21_19,
5682 GP_6_6_FN, FN_IP13_18_16,
5683 GP_6_5_FN, FN_IP13_15,
5684 GP_6_4_FN, FN_IP13_14,
5685 GP_6_3_FN, FN_IP13_13,
5686 GP_6_2_FN, FN_IP13_12,
5687 GP_6_1_FN, FN_IP13_11,
5688 GP_6_0_FN, FN_IP13_10 ))
5689 },
5690 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
5691 0, 0,
5692 0, 0,
5693 0, 0,
5694 0, 0,
5695 0, 0,
5696 0, 0,
5697 GP_7_25_FN, FN_USB1_PWEN,
5698 GP_7_24_FN, FN_USB0_OVC,
5699 GP_7_23_FN, FN_USB0_PWEN,
5700 GP_7_22_FN, FN_IP15_14_12,
5701 GP_7_21_FN, FN_IP15_11_9,
5702 GP_7_20_FN, FN_IP15_8_6,
5703 GP_7_19_FN, FN_IP7_2_0,
5704 GP_7_18_FN, FN_IP6_29_27,
5705 GP_7_17_FN, FN_IP6_26_24,
5706 GP_7_16_FN, FN_IP6_23_21,
5707 GP_7_15_FN, FN_IP6_20_19,
5708 GP_7_14_FN, FN_IP6_18_16,
5709 GP_7_13_FN, FN_IP6_15_14,
5710 GP_7_12_FN, FN_IP6_13_12,
5711 GP_7_11_FN, FN_IP6_11_10,
5712 GP_7_10_FN, FN_IP6_9_8,
5713 GP_7_9_FN, FN_IP16_11_10,
5714 GP_7_8_FN, FN_IP16_9_8,
5715 GP_7_7_FN, FN_IP16_7_6,
5716 GP_7_6_FN, FN_IP16_5_3,
5717 GP_7_5_FN, FN_IP16_2_0,
5718 GP_7_4_FN, FN_IP15_29_27,
5719 GP_7_3_FN, FN_IP15_26_24,
5720 GP_7_2_FN, FN_IP15_23_21,
5721 GP_7_1_FN, FN_IP15_20_18,
5722 GP_7_0_FN, FN_IP15_17_15 ))
5723 },
5724 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
5725 GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
5726 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
5727 GROUP(
5728 /* IP0_31 [1] */
5729 0, 0,
5730 /* IP0_30_29 [2] */
5731 FN_A6, FN_MSIOF1_SCK,
5732 0, 0,
5733 /* IP0_28_27 [2] */
5734 FN_A5, FN_MSIOF0_RXD_B,
5735 0, 0,
5736 /* IP0_26_25 [2] */
5737 FN_A4, FN_MSIOF0_TXD_B,
5738 0, 0,
5739 /* IP0_24_23 [2] */
5740 FN_A3, FN_MSIOF0_SS2_B,
5741 0, 0,
5742 /* IP0_22_21 [2] */
5743 FN_A2, FN_MSIOF0_SS1_B,
5744 0, 0,
5745 /* IP0_20_19 [2] */
5746 FN_A1, FN_MSIOF0_SYNC_B,
5747 0, 0,
5748 /* IP0_18_16 [3] */
5749 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
5750 0, 0, 0,
5751 /* IP0_15 [1] */
5752 FN_D15, 0,
5753 /* IP0_14 [1] */
5754 FN_D14, 0,
5755 /* IP0_13 [1] */
5756 FN_D13, 0,
5757 /* IP0_12 [1] */
5758 FN_D12, 0,
5759 /* IP0_11 [1] */
5760 FN_D11, 0,
5761 /* IP0_10 [1] */
5762 FN_D10, 0,
5763 /* IP0_9 [1] */
5764 FN_D9, 0,
5765 /* IP0_8 [1] */
5766 FN_D8, 0,
5767 /* IP0_7 [1] */
5768 FN_D7, 0,
5769 /* IP0_6 [1] */
5770 FN_D6, 0,
5771 /* IP0_5 [1] */
5772 FN_D5, 0,
5773 /* IP0_4 [1] */
5774 FN_D4, 0,
5775 /* IP0_3 [1] */
5776 FN_D3, 0,
5777 /* IP0_2 [1] */
5778 FN_D2, 0,
5779 /* IP0_1 [1] */
5780 FN_D1, 0,
5781 /* IP0_0 [1] */
5782 FN_D0, 0, ))
5783 },
5784 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
5785 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
5786 GROUP(
5787 /* IP1_31_29 [3] */
5788 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
5789 0, 0, 0,
5790 /* IP1_28_26 [3] */
5791 FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
5792 0, 0, 0, 0,
5793 /* IP1_25_23 [3] */
5794 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
5795 0, 0, 0,
5796 /* IP1_22_20 [3] */
5797 FN_A15, FN_BPFCLK_C,
5798 0, 0, 0, 0, 0, 0,
5799 /* IP1_19_17 [3] */
5800 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
5801 0, 0, 0,
5802 /* IP1_16_14 [3] */
5803 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
5804 0, 0, 0, 0,
5805 /* IP1_13_11 [3] */
5806 FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
5807 0, 0, 0, 0,
5808 /* IP1_10_8 [3] */
5809 FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
5810 0, 0, 0, 0,
5811 /* IP1_7_6 [2] */
5812 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
5813 /* IP1_5_4 [2] */
5814 FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
5815 /* IP1_3_2 [2] */
5816 FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
5817 /* IP1_1_0 [2] */
5818 FN_A7, FN_MSIOF1_SYNC,
5819 0, 0, ))
5820 },
5821 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5822 GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
5823 GROUP(
5824 /* IP2_31_30 [2] */
5825 0, 0, 0, 0,
5826 /* IP2_29_27 [3] */
5827 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
5828 FN_ATAG0_N, 0, FN_EX_WAIT1,
5829 0, 0,
5830 /* IP2_26_25 [2] */
5831 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
5832 /* IP2_24_23 [2] */
5833 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
5834 /* IP2_22_21 [2] */
5835 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
5836 /* IP2_20_19 [2] */
5837 FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
5838 /* IP2_18_16 [3] */
5839 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
5840 0, 0,
5841 /* IP2_15_13 [3] */
5842 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
5843 0, 0, 0,
5844 /* IP2_12_10 [3] */
5845 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
5846 0, 0, 0,
5847 /* IP2_9_7 [3] */
5848 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
5849 0, 0, 0,
5850 /* IP2_6_5 [2] */
5851 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
5852 /* IP2_4_3 [2] */
5853 FN_A20, FN_SPCLK, 0, 0,
5854 /* IP2_2_0 [3] */
5855 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
5856 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
5857 },
5858 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5859 GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
5860 GROUP(
5861 /* IP3_31 [1] */
5862 0, 0,
5863 /* IP3_30_28 [3] */
5864 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
5865 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
5866 0, 0, 0,
5867 /* IP3_27_25 [3] */
5868 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
5869 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
5870 0, 0, 0,
5871 /* IP3_24_22 [3] */
5872 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
5873 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
5874 /* IP3_21_20 [2] */
5875 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
5876 /* IP3_19_18 [2] */
5877 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
5878 /* IP3_17_16 [2] */
5879 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
5880 /* IP3_15_14 [2] */
5881 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
5882 /* IP3_13_12 [2] */
5883 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
5884 /* IP3_11_9 [3] */
5885 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
5886 0, 0, 0,
5887 /* IP3_8_6 [3] */
5888 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
5889 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
5890 /* IP3_5_3 [3] */
5891 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
5892 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
5893 /* IP3_2_0 [3] */
5894 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
5895 0, 0, 0, ))
5896 },
5897 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5898 GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
5899 3, 3, 2),
5900 GROUP(
5901 /* IP4_31 [1] */
5902 0, 0,
5903 /* IP4_30_28 [3] */
5904 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
5905 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
5906 0, 0,
5907 /* IP4_27_26 [2] */
5908 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
5909 /* IP4_25_24 [2] */
5910 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
5911 /* IP4_23_22 [2] */
5912 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
5913 /* IP4_21 [1] */
5914 FN_SSI_SDATA3, 0,
5915 /* IP4_20 [1] */
5916 FN_SSI_WS34, 0,
5917 /* IP4_19 [1] */
5918 FN_SSI_SCK34, 0,
5919 /* IP4_18_16 [3] */
5920 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
5921 0, 0, 0, 0,
5922 /* IP4_15_13 [3] */
5923 FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
5924 FN_GLO_Q1_D, FN_HCTS1_N_E,
5925 0, 0,
5926 /* IP4_12_10 [3] */
5927 FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
5928 0, 0, 0,
5929 /* IP4_9_8 [2] */
5930 FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
5931 /* IP4_7_5 [3] */
5932 FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
5933 FN_GLO_I1_D, 0, 0, 0,
5934 /* IP4_4_2 [3] */
5935 FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
5936 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
5937 0, 0, 0,
5938 /* IP4_1_0 [2] */
5939 FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
5940 ))
5941 },
5942 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5943 GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
5944 GROUP(
5945 /* IP5_31_29 [3] */
5946 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
5947 0, 0, 0, 0, 0,
5948 /* IP5_28_26 [3] */
5949 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
5950 0, 0, 0, 0,
5951 /* IP5_25_24 [2] */
5952 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
5953 /* IP5_23_22 [2] */
5954 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
5955 /* IP5_21_20 [2] */
5956 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
5957 /* IP5_19_17 [3] */
5958 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
5959 0, 0, 0, 0,
5960 /* IP5_16_15 [2] */
5961 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
5962 /* IP5_14_12 [3] */
5963 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
5964 0, 0, 0, 0,
5965 /* IP5_11_9 [3] */
5966 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
5967 0, 0, 0, 0,
5968 /* IP5_8_6 [3] */
5969 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
5970 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
5971 0, 0,
5972 /* IP5_5_3 [3] */
5973 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
5974 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
5975 0, 0,
5976 /* IP5_2_0 [3] */
5977 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
5978 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
5979 0, 0, ))
5980 },
5981 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5982 GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
5983 GROUP(
5984 /* IP6_31_30 [2] */
5985 0, 0, 0, 0,
5986 /* IP6_29_27 [3] */
5987 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
5988 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
5989 0, 0, 0,
5990 /* IP6_26_24 [3] */
5991 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
5992 FN_GPS_CLK_C, FN_GPS_CLK_D,
5993 0, 0, 0,
5994 /* IP6_23_21 [3] */
5995 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
5996 FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
5997 0, 0, 0,
5998 /* IP6_20_19 [2] */
5999 FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
6000 /* IP6_18_16 [3] */
6001 FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
6002 FN_INTC_IRQ4_N, 0, 0, 0,
6003 /* IP6_15_14 [2] */
6004 FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
6005 /* IP6_13_12 [2] */
6006 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
6007 /* IP6_11_10 [2] */
6008 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
6009 /* IP6_9_8 [2] */
6010 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
6011 /* IP6_7_6 [2] */
6012 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
6013 /* IP6_5_3 [3] */
6014 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
6015 FN_SCIFA2_RXD, FN_FMIN_E,
6016 0, 0,
6017 /* IP6_2_0 [3] */
6018 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
6019 FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
6020 0, 0, ))
6021 },
6022 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
6023 GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
6024 GROUP(
6025 /* IP7_31_30 [2] */
6026 0, 0, 0, 0,
6027 /* IP7_29_27 [3] */
6028 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
6029 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
6030 0, 0,
6031 /* IP7_26_24 [3] */
6032 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
6033 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
6034 0, 0,
6035 /* IP7_23_21 [3] */
6036 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
6037 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
6038 0, 0,
6039 /* IP7_20_19 [2] */
6040 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
6041 /* IP7_18_17 [2] */
6042 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
6043 /* IP7_16_15 [2] */
6044 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
6045 /* IP7_14_13 [2] */
6046 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
6047 /* IP7_12_11 [2] */
6048 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
6049 /* IP7_10_9 [2] */
6050 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
6051 /* IP7_8_6 [3] */
6052 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
6053 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
6054 0, 0,
6055 /* IP7_5_3 [3] */
6056 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
6057 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
6058 0, 0,
6059 /* IP7_2_0 [3] */
6060 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
6061 FN_SCIF_CLK_B, FN_GPS_MAG_D,
6062 0, 0, ))
6063 },
6064 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
6065 GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
6066 GROUP(
6067 /* IP8_31 [1] */
6068 0, 0,
6069 /* IP8_30_28 [3] */
6070 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
6071 0, 0, 0,
6072 /* IP8_27_26 [2] */
6073 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
6074 /* IP8_25_24 [2] */
6075 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
6076 /* IP8_23_21 [3] */
6077 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
6078 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
6079 0, 0,
6080 /* IP8_20_18 [3] */
6081 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
6082 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
6083 0, 0,
6084 /* IP8_17_15 [3] */
6085 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
6086 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
6087 0, 0,
6088 /* IP8_14_12 [3] */
6089 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
6090 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
6091 0, 0, 0,
6092 /* IP8_11_9 [3] */
6093 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
6094 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
6095 0, 0, 0,
6096 /* IP8_8_6 [3] */
6097 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
6098 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
6099 0, 0,
6100 /* IP8_5_3 [3] */
6101 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
6102 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
6103 0, 0,
6104 /* IP8_2_0 [3] */
6105 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
6106 0, 0, 0, ))
6107 },
6108 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
6109 GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
6110 1, 1, 3, 3),
6111 GROUP(
6112 /* IP9_31_29 [3] */
6113 FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
6114 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
6115 /* IP9_28_27 [2] */
6116 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
6117 /* IP9_26_25 [2] */
6118 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
6119 /* IP9_24_23 [2] */
6120 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
6121 /* IP9_22_21 [2] */
6122 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
6123 /* IP9_20_19 [2] */
6124 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
6125 /* IP9_18_17 [2] */
6126 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
6127 /* IP9_16 [1] */
6128 FN_DU1_DISP, FN_QPOLA,
6129 /* IP9_15_13 [3] */
6130 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
6131 FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
6132 0, 0, 0,
6133 /* IP9_12 [1] */
6134 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
6135 /* IP9_11 [1] */
6136 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
6137 /* IP9_10_8 [3] */
6138 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
6139 FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
6140 0, 0,
6141 /* IP9_7 [1] */
6142 FN_DU1_DOTCLKOUT0, FN_QCLK,
6143 /* IP9_6 [1] */
6144 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
6145 /* IP9_5_3 [3] */
6146 FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
6147 FN_SCIF3_SCK, FN_SCIFA3_SCK,
6148 0, 0, 0,
6149 /* IP9_2_0 [3] */
6150 FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
6151 0, 0, 0, ))
6152 },
6153 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
6154 GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
6155 GROUP(
6156 /* IP10_31_29 [3] */
6157 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
6158 0, 0, 0,
6159 /* IP10_28_27 [2] */
6160 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
6161 /* IP10_26_25 [2] */
6162 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
6163 /* IP10_24_22 [3] */
6164 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
6165 0, 0, 0,
6166 /* IP10_21_19 [3] */
6167 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
6168 FN_TS_SDATA0_C, FN_ATACS11_N,
6169 0, 0, 0,
6170 /* IP10_18_17 [2] */
6171 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
6172 /* IP10_16_15 [2] */
6173 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
6174 /* IP10_14_12 [3] */
6175 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
6176 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
6177 /* IP10_11_9 [3] */
6178 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
6179 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
6180 0, 0,
6181 /* IP10_8_6 [3] */
6182 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
6183 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
6184 /* IP10_5_3 [3] */
6185 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
6186 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
6187 /* IP10_2_0 [3] */
6188 FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
6189 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
6190 },
6191 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
6192 GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
6193 2, 3, 3, 3, 3, 3),
6194 GROUP(
6195 /* IP11_31_30 [2] */
6196 FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
6197 /* IP11_29_28 [2] */
6198 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
6199 /* IP11_27 [1] */
6200 FN_VI1_DATA7, FN_AVB_MDC,
6201 /* IP11_26 [1] */
6202 FN_VI1_DATA6, FN_AVB_MAGIC,
6203 /* IP11_25 [1] */
6204 FN_VI1_DATA5, FN_AVB_RX_DV,
6205 /* IP11_24 [1] */
6206 FN_VI1_DATA4, FN_AVB_MDIO,
6207 /* IP11_23 [1] */
6208 FN_VI1_DATA3, FN_AVB_RX_ER,
6209 /* IP11_22 [1] */
6210 FN_VI1_DATA2, FN_AVB_RXD7,
6211 /* IP11_21 [1] */
6212 FN_VI1_DATA1, FN_AVB_RXD6,
6213 /* IP11_20 [1] */
6214 FN_VI1_DATA0, FN_AVB_RXD5,
6215 /* IP11_19 [1] */
6216 FN_VI1_CLK, FN_AVB_RXD4,
6217 /* IP11_18_17 [2] */
6218 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
6219 /* IP11_16_15 [2] */
6220 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
6221 /* IP11_14_12 [3] */
6222 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
6223 FN_RX4_B, FN_SCIFA4_RXD_B,
6224 0, 0, 0,
6225 /* IP11_11_9 [3] */
6226 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
6227 FN_TX4_B, FN_SCIFA4_TXD_B,
6228 0, 0, 0,
6229 /* IP11_8_6 [3] */
6230 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
6231 FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
6232 /* IP11_5_3 [3] */
6233 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
6234 0, 0, 0,
6235 /* IP11_2_0 [3] */
6236 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
6237 FN_I2C1_SDA_D, 0, 0, 0, ))
6238 },
6239 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
6240 GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
6241 GROUP(
6242 /* IP12_31_30 [2] */
6243 0, 0, 0, 0,
6244 /* IP12_29_27 [3] */
6245 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
6246 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
6247 0, 0, 0,
6248 /* IP12_26_24 [3] */
6249 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
6250 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
6251 0, 0, 0,
6252 /* IP12_23_22 [2] */
6253 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
6254 /* IP12_21_20 [2] */
6255 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
6256 /* IP12_19_18 [2] */
6257 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
6258 /* IP12_17_16 [2] */
6259 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
6260 /* IP12_15_13 [3] */
6261 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
6262 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
6263 0, 0, 0,
6264 /* IP12_12_10 [3] */
6265 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
6266 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
6267 0, 0, 0,
6268 /* IP12_9_7 [3] */
6269 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
6270 FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
6271 0, 0, 0,
6272 /* IP12_6_4 [3] */
6273 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
6274 FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
6275 0, 0, 0,
6276 /* IP12_3_2 [2] */
6277 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
6278 /* IP12_1_0 [2] */
6279 FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
6280 },
6281 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
6282 GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
6283 1, 1, 1, 3, 2, 2, 3),
6284 GROUP(
6285 /* IP13_31 [1] */
6286 0, 0,
6287 /* IP13_30_28 [3] */
6288 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
6289 0, 0, 0, 0,
6290 /* IP13_27 [1] */
6291 FN_SD1_DATA3, FN_IERX_B,
6292 /* IP13_26 [1] */
6293 FN_SD1_DATA2, FN_IECLK_B,
6294 /* IP13_25 [1] */
6295 FN_SD1_DATA1, FN_IETX_B,
6296 /* IP13_24_23 [2] */
6297 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
6298 /* IP13_22 [1] */
6299 FN_SD1_CMD, FN_REMOCON_B,
6300 /* IP13_21_19 [3] */
6301 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
6302 FN_SCIFA5_RXD_B, FN_RX3_C,
6303 0, 0,
6304 /* IP13_18_16 [3] */
6305 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
6306 FN_SCIFA5_TXD_B, FN_TX3_C,
6307 0, 0,
6308 /* IP13_15 [1] */
6309 FN_SD0_DATA3, FN_SSL_B,
6310 /* IP13_14 [1] */
6311 FN_SD0_DATA2, FN_IO3_B,
6312 /* IP13_13 [1] */
6313 FN_SD0_DATA1, FN_IO2_B,
6314 /* IP13_12 [1] */
6315 FN_SD0_DATA0, FN_MISO_IO1_B,
6316 /* IP13_11 [1] */
6317 FN_SD0_CMD, FN_MOSI_IO0_B,
6318 /* IP13_10 [1] */
6319 FN_SD0_CLK, FN_SPCLK_B,
6320 /* IP13_9_7 [3] */
6321 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
6322 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
6323 0, 0, 0,
6324 /* IP13_6_5 [2] */
6325 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
6326 /* IP13_4_3 [2] */
6327 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
6328 /* IP13_2_0 [3] */
6329 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
6330 FN_ADICLK_B, FN_MSIOF0_SS1_C,
6331 0, 0, 0, ))
6332 },
6333 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
6334 GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
6335 1, 1, 2),
6336 GROUP(
6337 /* IP14_31_29 [3] */
6338 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
6339 FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
6340 /* IP14_28_26 [3] */
6341 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
6342 FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
6343 /* IP14_25_23 [3] */
6344 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
6345 0, 0, 0,
6346 /* IP14_22_20 [3] */
6347 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
6348 0, 0, 0,
6349 /* IP14_19_17 [3] */
6350 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
6351 FN_VI1_CLKENB_C, FN_VI1_G1_B,
6352 0, 0,
6353 /* IP14_16_14 [3] */
6354 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
6355 FN_VI1_CLK_C, FN_VI1_G0_B,
6356 0, 0,
6357 /* IP14_13_11 [3] */
6358 FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
6359 0, 0, 0,
6360 /* IP14_10_8 [3] */
6361 FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
6362 0, 0, 0,
6363 /* IP14_7 [1] */
6364 FN_SD2_DATA3, FN_MMC_D3,
6365 /* IP14_6 [1] */
6366 FN_SD2_DATA2, FN_MMC_D2,
6367 /* IP14_5 [1] */
6368 FN_SD2_DATA1, FN_MMC_D1,
6369 /* IP14_4 [1] */
6370 FN_SD2_DATA0, FN_MMC_D0,
6371 /* IP14_3 [1] */
6372 FN_SD2_CMD, FN_MMC_CMD,
6373 /* IP14_2 [1] */
6374 FN_SD2_CLK, FN_MMC_CLK,
6375 /* IP14_1_0 [2] */
6376 FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
6377 },
6378 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
6379 GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
6380 GROUP(
6381 /* IP15_31_30 [2] */
6382 0, 0, 0, 0,
6383 /* IP15_29_27 [3] */
6384 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
6385 FN_CAN0_TX_B, FN_VI1_DATA5_C,
6386 0, 0,
6387 /* IP15_26_24 [3] */
6388 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
6389 FN_CAN0_RX_B, FN_VI1_DATA4_C,
6390 0, 0,
6391 /* IP15_23_21 [3] */
6392 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
6393 FN_TCLK2, FN_VI1_DATA3_C, 0,
6394 /* IP15_20_18 [3] */
6395 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
6396 0, 0, 0,
6397 /* IP15_17_15 [3] */
6398 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
6399 FN_TCLK1, FN_VI1_DATA1_C,
6400 0, 0,
6401 /* IP15_14_12 [3] */
6402 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
6403 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
6404 0, 0,
6405 /* IP15_11_9 [3] */
6406 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
6407 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
6408 0, 0,
6409 /* IP15_8_6 [3] */
6410 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
6411 FN_PWM5_B, FN_SCIFA3_TXD_C,
6412 0, 0, 0,
6413 /* IP15_5_4 [2] */
6414 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
6415 /* IP15_3_2 [2] */
6416 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
6417 /* IP15_1_0 [2] */
6418 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
6419 },
6420 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
6421 GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
6422 GROUP(
6423 /* IP16_31_28 [4] */
6424 0, 0, 0, 0, 0, 0, 0, 0,
6425 0, 0, 0, 0, 0, 0, 0, 0,
6426 /* IP16_27_24 [4] */
6427 0, 0, 0, 0, 0, 0, 0, 0,
6428 0, 0, 0, 0, 0, 0, 0, 0,
6429 /* IP16_23_20 [4] */
6430 0, 0, 0, 0, 0, 0, 0, 0,
6431 0, 0, 0, 0, 0, 0, 0, 0,
6432 /* IP16_19_16 [4] */
6433 0, 0, 0, 0, 0, 0, 0, 0,
6434 0, 0, 0, 0, 0, 0, 0, 0,
6435 /* IP16_15_12 [4] */
6436 0, 0, 0, 0, 0, 0, 0, 0,
6437 0, 0, 0, 0, 0, 0, 0, 0,
6438 /* IP16_11_10 [2] */
6439 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
6440 /* IP16_9_8 [2] */
6441 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
6442 /* IP16_7_6 [2] */
6443 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
6444 /* IP16_5_3 [3] */
6445 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
6446 FN_GLO_SS_C, FN_VI1_DATA7_C,
6447 0, 0, 0,
6448 /* IP16_2_0 [3] */
6449 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
6450 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
6451 0, 0, 0, ))
6452 },
6453 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
6454 GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
6455 2, 2, 1, 2, 2, 2),
6456 GROUP(
6457 /* RESERVED [1] */
6458 0, 0,
6459 /* SEL_SCIF1 [2] */
6460 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
6461 /* SEL_SCIFB [2] */
6462 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
6463 /* SEL_SCIFB2 [2] */
6464 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
6465 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
6466 /* SEL_SCIFB1 [3] */
6467 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
6468 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
6469 0, 0, 0, 0,
6470 /* SEL_SCIFA1 [2] */
6471 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
6472 /* SEL_SSI9 [1] */
6473 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
6474 /* SEL_SCFA [1] */
6475 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
6476 /* SEL_QSP [1] */
6477 FN_SEL_QSP_0, FN_SEL_QSP_1,
6478 /* SEL_SSI7 [1] */
6479 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
6480 /* SEL_HSCIF1 [3] */
6481 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
6482 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
6483 0, 0, 0,
6484 /* RESERVED [2] */
6485 0, 0, 0, 0,
6486 /* SEL_VI1 [2] */
6487 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
6488 /* RESERVED [2] */
6489 0, 0, 0, 0,
6490 /* SEL_TMU [1] */
6491 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
6492 /* SEL_LBS [2] */
6493 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
6494 /* SEL_TSIF0 [2] */
6495 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
6496 /* SEL_SOF0 [2] */
6497 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
6498 },
6499 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
6500 GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
6501 1, 2, 2, 2, 1, 1, 1),
6502 GROUP(
6503 /* SEL_SCIF0 [3] */
6504 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
6505 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
6506 0, 0, 0,
6507 /* RESERVED [1] */
6508 0, 0,
6509 /* SEL_SCIF [1] */
6510 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
6511 /* SEL_CAN0 [3] */
6512 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
6513 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
6514 0, 0,
6515 /* SEL_CAN1 [2] */
6516 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
6517 /* RESERVED [1] */
6518 0, 0,
6519 /* SEL_SCIFA2 [1] */
6520 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
6521 /* SEL_SCIF4 [2] */
6522 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
6523 /* RESERVED [2] */
6524 0, 0, 0, 0,
6525 /* SEL_ADG [1] */
6526 FN_SEL_ADG_0, FN_SEL_ADG_1,
6527 /* SEL_FM [3] */
6528 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
6529 FN_SEL_FM_3, FN_SEL_FM_4,
6530 0, 0, 0,
6531 /* SEL_SCIFA5 [2] */
6532 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
6533 /* RESERVED [1] */
6534 0, 0,
6535 /* SEL_GPS [2] */
6536 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
6537 /* SEL_SCIFA4 [2] */
6538 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
6539 /* SEL_SCIFA3 [2] */
6540 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
6541 /* SEL_SIM [1] */
6542 FN_SEL_SIM_0, FN_SEL_SIM_1,
6543 /* RESERVED [1] */
6544 0, 0,
6545 /* SEL_SSI8 [1] */
6546 FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
6547 },
6548 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
6549 GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
6550 3, 2, 2, 2, 1),
6551 GROUP(
6552 /* SEL_HSCIF2 [2] */
6553 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
6554 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
6555 /* SEL_CANCLK [2] */
6556 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
6557 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
6558 /* SEL_IIC1 [2] */
6559 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
6560 /* SEL_IIC0 [2] */
6561 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
6562 /* SEL_I2C4 [2] */
6563 FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
6564 /* SEL_I2C3 [2] */
6565 FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
6566 /* SEL_SCIF3 [2] */
6567 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
6568 /* SEL_IEB [2] */
6569 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
6570 /* SEL_MMC [1] */
6571 FN_SEL_MMC_0, FN_SEL_MMC_1,
6572 /* SEL_SCIF5 [1] */
6573 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
6574 /* RESERVED [2] */
6575 0, 0, 0, 0,
6576 /* SEL_I2C2 [2] */
6577 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
6578 /* SEL_I2C1 [3] */
6579 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
6580 FN_SEL_I2C1_4,
6581 0, 0, 0,
6582 /* SEL_I2C0 [2] */
6583 FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
6584 /* RESERVED [2] */
6585 0, 0, 0, 0,
6586 /* RESERVED [2] */
6587 0, 0, 0, 0,
6588 /* RESERVED [1] */
6589 0, 0, ))
6590 },
6591 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
6592 GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
6593 1, 1, 2, 2, 2, 2),
6594 GROUP(
6595 /* SEL_SOF1 [3] */
6596 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
6597 FN_SEL_SOF1_4,
6598 0, 0, 0,
6599 /* SEL_HSCIF0 [2] */
6600 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
6601 /* SEL_DIS [2] */
6602 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
6603 /* RESERVED [1] */
6604 0, 0,
6605 /* SEL_RAD [1] */
6606 FN_SEL_RAD_0, FN_SEL_RAD_1,
6607 /* SEL_RCN [1] */
6608 FN_SEL_RCN_0, FN_SEL_RCN_1,
6609 /* SEL_RSP [1] */
6610 FN_SEL_RSP_0, FN_SEL_RSP_1,
6611 /* SEL_SCIF2 [3] */
6612 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
6613 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
6614 0, 0, 0,
6615 /* RESERVED [2] */
6616 0, 0, 0, 0,
6617 /* RESERVED [2] */
6618 0, 0, 0, 0,
6619 /* SEL_SOF2 [3] */
6620 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
6621 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
6622 0, 0, 0,
6623 /* RESERVED [1] */
6624 0, 0,
6625 /* SEL_SSI1 [1] */
6626 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
6627 /* SEL_SSI0 [1] */
6628 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
6629 /* SEL_SSP [2] */
6630 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
6631 /* RESERVED [2] */
6632 0, 0, 0, 0,
6633 /* RESERVED [2] */
6634 0, 0, 0, 0,
6635 /* RESERVED [2] */
6636 0, 0, 0, 0, ))
6637 },
6638 { },
6639 };
6640
r8a7791_pin_to_pocctrl(struct sh_pfc * pfc,unsigned int pin,u32 * pocctrl)6641 static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
6642 {
6643 if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
6644 return -EINVAL;
6645
6646 *pocctrl = 0xe606008c;
6647
6648 return 31 - (pin & 0x1f);
6649 }
6650
6651 static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
6652 .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
6653 };
6654
6655 #ifdef CONFIG_PINCTRL_PFC_R8A7743
6656 const struct sh_pfc_soc_info r8a7743_pinmux_info = {
6657 .name = "r8a77430_pfc",
6658 .ops = &r8a7791_pinmux_ops,
6659 .unlock_reg = 0xe6060000, /* PMMR */
6660
6661 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6662
6663 .pins = pinmux_pins,
6664 .nr_pins = ARRAY_SIZE(pinmux_pins),
6665 .groups = pinmux_groups.common,
6666 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6667 .functions = pinmux_functions.common,
6668 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6669
6670 .cfg_regs = pinmux_config_regs,
6671
6672 .pinmux_data = pinmux_data,
6673 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6674 };
6675 #endif
6676
6677 #ifdef CONFIG_PINCTRL_PFC_R8A7744
6678 const struct sh_pfc_soc_info r8a7744_pinmux_info = {
6679 .name = "r8a77440_pfc",
6680 .ops = &r8a7791_pinmux_ops,
6681 .unlock_reg = 0xe6060000, /* PMMR */
6682
6683 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6684
6685 .pins = pinmux_pins,
6686 .nr_pins = ARRAY_SIZE(pinmux_pins),
6687 .groups = pinmux_groups.common,
6688 .nr_groups = ARRAY_SIZE(pinmux_groups.common),
6689 .functions = pinmux_functions.common,
6690 .nr_functions = ARRAY_SIZE(pinmux_functions.common),
6691
6692 .cfg_regs = pinmux_config_regs,
6693
6694 .pinmux_data = pinmux_data,
6695 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6696 };
6697 #endif
6698
6699 #ifdef CONFIG_PINCTRL_PFC_R8A7791
6700 const struct sh_pfc_soc_info r8a7791_pinmux_info = {
6701 .name = "r8a77910_pfc",
6702 .ops = &r8a7791_pinmux_ops,
6703 .unlock_reg = 0xe6060000, /* PMMR */
6704
6705 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6706
6707 .pins = pinmux_pins,
6708 .nr_pins = ARRAY_SIZE(pinmux_pins),
6709 .groups = pinmux_groups.common,
6710 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6711 ARRAY_SIZE(pinmux_groups.automotive),
6712 .functions = pinmux_functions.common,
6713 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6714 ARRAY_SIZE(pinmux_functions.automotive),
6715
6716 .cfg_regs = pinmux_config_regs,
6717
6718 .pinmux_data = pinmux_data,
6719 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6720 };
6721 #endif
6722
6723 #ifdef CONFIG_PINCTRL_PFC_R8A7793
6724 const struct sh_pfc_soc_info r8a7793_pinmux_info = {
6725 .name = "r8a77930_pfc",
6726 .ops = &r8a7791_pinmux_ops,
6727 .unlock_reg = 0xe6060000, /* PMMR */
6728
6729 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6730
6731 .pins = pinmux_pins,
6732 .nr_pins = ARRAY_SIZE(pinmux_pins),
6733 .groups = pinmux_groups.common,
6734 .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
6735 ARRAY_SIZE(pinmux_groups.automotive),
6736 .functions = pinmux_functions.common,
6737 .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
6738 ARRAY_SIZE(pinmux_functions.automotive),
6739
6740 .cfg_regs = pinmux_config_regs,
6741
6742 .pinmux_data = pinmux_data,
6743 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6744 };
6745 #endif
6746