1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * SuperH Pin Function Controller Support 4 * 5 * Copyright (c) 2008 Magnus Damm 6 */ 7 8 #ifndef __SH_PFC_H 9 #define __SH_PFC_H 10 11 #include <linux/stringify.h> 12 13 enum { 14 PINMUX_TYPE_NONE, 15 PINMUX_TYPE_FUNCTION, 16 PINMUX_TYPE_GPIO, 17 PINMUX_TYPE_OUTPUT, 18 PINMUX_TYPE_INPUT, 19 }; 20 21 #define SH_PFC_PIN_NONE U16_MAX 22 23 #define SH_PFC_PIN_CFG_INPUT (1 << 0) 24 #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) 25 #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) 26 #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) 27 #define SH_PFC_PIN_CFG_PULL_UP_DOWN (SH_PFC_PIN_CFG_PULL_UP | \ 28 SH_PFC_PIN_CFG_PULL_DOWN) 29 #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) 30 #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) 31 32 #define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6) 33 #define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6) 34 35 #define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ 36 SH_PFC_PIN_VOLTAGE_18_33) 37 #define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33 (SH_PFC_PIN_CFG_IO_VOLTAGE | \ 38 SH_PFC_PIN_VOLTAGE_25_33) 39 40 #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) 41 42 struct sh_pfc_pin { 43 const char *name; 44 unsigned int configs; 45 u16 pin; 46 u16 enum_id; 47 }; 48 49 #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ 50 { \ 51 .name = #alias, \ 52 .pins = n##_pins, \ 53 .mux = n##_mux, \ 54 .nr_pins = ARRAY_SIZE(n##_pins) + \ 55 BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ 56 } 57 #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) 58 59 struct sh_pfc_pin_group { 60 const char *name; 61 const unsigned int *pins; 62 const unsigned int *mux; 63 unsigned int nr_pins; 64 }; 65 66 /* 67 * Using union vin_data{,12,16} saves memory occupied by the VIN data pins. 68 * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups 69 * in this case. It accepts an optional 'version' argument used when the 70 * same group can appear on a different set of pins. 71 */ 72 #define VIN_DATA_PIN_GROUP(n, s, ...) \ 73 { \ 74 .name = #n#s#__VA_ARGS__, \ 75 .pins = n##__VA_ARGS__##_pins.data##s, \ 76 .mux = n##__VA_ARGS__##_mux.data##s, \ 77 .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \ 78 } 79 80 union vin_data12 { 81 unsigned int data12[12]; 82 unsigned int data10[10]; 83 unsigned int data8[8]; 84 }; 85 86 union vin_data16 { 87 unsigned int data16[16]; 88 unsigned int data12[12]; 89 unsigned int data10[10]; 90 unsigned int data8[8]; 91 }; 92 93 union vin_data { 94 unsigned int data24[24]; 95 unsigned int data20[20]; 96 unsigned int data16[16]; 97 unsigned int data12[12]; 98 unsigned int data10[10]; 99 unsigned int data8[8]; 100 unsigned int data4[4]; 101 }; 102 103 #define SH_PFC_FUNCTION(n) \ 104 { \ 105 .name = #n, \ 106 .groups = n##_groups, \ 107 .nr_groups = ARRAY_SIZE(n##_groups), \ 108 } 109 110 struct sh_pfc_function { 111 const char *name; 112 const char * const *groups; 113 unsigned int nr_groups; 114 }; 115 116 struct pinmux_func { 117 u16 enum_id; 118 const char *name; 119 }; 120 121 struct pinmux_cfg_reg { 122 u32 reg; 123 u8 reg_width, field_width; 124 #ifdef DEBUG 125 u16 nr_enum_ids; /* for variable width regs only */ 126 #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, 127 #else 128 #define SET_NR_ENUM_IDS(n) 129 #endif 130 const u16 *enum_ids; 131 const u8 *var_field_width; 132 }; 133 134 #define GROUP(...) __VA_ARGS__ 135 136 /* 137 * Describe a config register consisting of several fields of the same width 138 * - name: Register name (unused, for documentation purposes only) 139 * - r: Physical register address 140 * - r_width: Width of the register (in bits) 141 * - f_width: Width of the fixed-width register fields (in bits) 142 * - ids: For each register field (from left to right, i.e. MSB to LSB), 143 * 2^f_width enum IDs must be specified, one for each possible 144 * combination of the register field bit values, all wrapped using 145 * the GROUP() macro. 146 */ 147 #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ 148 .reg = r, .reg_width = r_width, \ 149 .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ 150 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ 151 (r_width / f_width) * (1 << f_width)), \ 152 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ 153 { ids } 154 155 /* 156 * Describe a config register consisting of several fields of different widths 157 * - name: Register name (unused, for documentation purposes only) 158 * - r: Physical register address 159 * - r_width: Width of the register (in bits) 160 * - f_widths: List of widths of the register fields (in bits), from left 161 * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. 162 * - ids: For each register field (from left to right, i.e. MSB to LSB), 163 * 2^f_widths[i] enum IDs must be specified, one for each possible 164 * combination of the register field bit values, all wrapped using 165 * the GROUP() macro. 166 */ 167 #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ 168 .reg = r, .reg_width = r_width, \ 169 .var_field_width = (const u8 []) { f_widths, 0 }, \ 170 SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ 171 .enum_ids = (const u16 []) { ids } 172 173 struct pinmux_drive_reg_field { 174 u16 pin; 175 u8 offset; 176 u8 size; 177 }; 178 179 struct pinmux_drive_reg { 180 u32 reg; 181 const struct pinmux_drive_reg_field fields[8]; 182 }; 183 184 #define PINMUX_DRIVE_REG(name, r) \ 185 .reg = r, \ 186 .fields = 187 188 struct pinmux_bias_reg { 189 u32 puen; /* Pull-enable or pull-up control register */ 190 u32 pud; /* Pull-up/down control register (optional) */ 191 const u16 pins[32]; 192 }; 193 194 #define PINMUX_BIAS_REG(name1, r1, name2, r2) \ 195 .puen = r1, \ 196 .pud = r2, \ 197 .pins = 198 199 struct pinmux_ioctrl_reg { 200 u32 reg; 201 }; 202 203 struct pinmux_data_reg { 204 u32 reg; 205 u8 reg_width; 206 const u16 *enum_ids; 207 }; 208 209 /* 210 * Describe a data register 211 * - name: Register name (unused, for documentation purposes only) 212 * - r: Physical register address 213 * - r_width: Width of the register (in bits) 214 * - ids: For each register bit (from left to right, i.e. MSB to LSB), one 215 * enum ID must be specified, all wrapped using the GROUP() macro. 216 */ 217 #define PINMUX_DATA_REG(name, r, r_width, ids) \ 218 .reg = r, .reg_width = r_width + \ 219 BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ 220 r_width), \ 221 .enum_ids = (const u16 [r_width]) { ids } 222 223 struct pinmux_irq { 224 const short *gpios; 225 }; 226 227 /* 228 * Describe the mapping from GPIOs to a single IRQ 229 * - ids...: List of GPIOs that are mapped to the same IRQ 230 */ 231 #define PINMUX_IRQ(ids...) \ 232 { .gpios = (const short []) { ids, -1 } } 233 234 struct pinmux_range { 235 u16 begin; 236 u16 end; 237 u16 force; 238 }; 239 240 struct sh_pfc_window { 241 phys_addr_t phys; 242 void __iomem *virt; 243 unsigned long size; 244 }; 245 246 struct sh_pfc_pin_range; 247 248 struct sh_pfc { 249 struct device *dev; 250 const struct sh_pfc_soc_info *info; 251 252 void *regs; 253 254 struct sh_pfc_pin_range *ranges; 255 unsigned int nr_ranges; 256 257 unsigned int nr_gpio_pins; 258 259 struct sh_pfc_chip *gpio; 260 }; 261 262 struct sh_pfc_soc_operations { 263 int (*init)(struct sh_pfc *pfc); 264 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); 265 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, 266 unsigned int bias); 267 int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); 268 }; 269 270 struct sh_pfc_soc_info { 271 const char *name; 272 const struct sh_pfc_soc_operations *ops; 273 274 struct pinmux_range input; 275 struct pinmux_range output; 276 struct pinmux_range function; 277 278 const struct sh_pfc_pin *pins; 279 unsigned int nr_pins; 280 const struct sh_pfc_pin_group *groups; 281 unsigned int nr_groups; 282 const struct sh_pfc_function *functions; 283 unsigned int nr_functions; 284 285 const struct pinmux_cfg_reg *cfg_regs; 286 const struct pinmux_drive_reg *drive_regs; 287 const struct pinmux_bias_reg *bias_regs; 288 const struct pinmux_ioctrl_reg *ioctrl_regs; 289 const struct pinmux_data_reg *data_regs; 290 291 const u16 *pinmux_data; 292 unsigned int pinmux_data_size; 293 294 const struct pinmux_irq *gpio_irq; 295 unsigned int gpio_irq_size; 296 297 u32 unlock_reg; /* can be literal address or mask */ 298 }; 299 300 u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg); 301 void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data); 302 const struct pinmux_bias_reg * 303 sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, 304 unsigned int *bit); 305 306 extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; 307 extern const struct sh_pfc_soc_info r8a774b1_pinmux_info; 308 extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; 309 extern const struct sh_pfc_soc_info r8a774e1_pinmux_info; 310 extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 311 extern const struct sh_pfc_soc_info r8a7791_pinmux_info; 312 extern const struct sh_pfc_soc_info r8a7792_pinmux_info; 313 extern const struct sh_pfc_soc_info r8a7793_pinmux_info; 314 extern const struct sh_pfc_soc_info r8a7794_pinmux_info; 315 extern const struct sh_pfc_soc_info r8a7795_pinmux_info; 316 extern const struct sh_pfc_soc_info r8a7796_pinmux_info; 317 extern const struct sh_pfc_soc_info r8a77965_pinmux_info; 318 extern const struct sh_pfc_soc_info r8a77970_pinmux_info; 319 extern const struct sh_pfc_soc_info r8a77980_pinmux_info; 320 extern const struct sh_pfc_soc_info r8a77990_pinmux_info; 321 extern const struct sh_pfc_soc_info r8a77995_pinmux_info; 322 323 /* ----------------------------------------------------------------------------- 324 * Helper macros to create pin and port lists 325 */ 326 327 /* 328 * sh_pfc_soc_info pinmux_data array macros 329 */ 330 331 /* 332 * Describe generic pinmux data 333 * - data_or_mark: *_DATA or *_MARK enum ID 334 * - ids...: List of enum IDs to associate with data_or_mark 335 */ 336 #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 337 338 /* 339 * Describe a pinmux configuration without GPIO function that needs 340 * configuration in a Peripheral Function Select Register (IPSR) 341 * - ipsr: IPSR field (unused, for documentation purposes only) 342 * - fn: Function name, referring to a field in the IPSR 343 */ 344 #define PINMUX_IPSR_NOGP(ipsr, fn) \ 345 PINMUX_DATA(fn##_MARK, FN_##fn) 346 347 /* 348 * Describe a pinmux configuration with GPIO function that needs configuration 349 * in both a Peripheral Function Select Register (IPSR) and in a 350 * GPIO/Peripheral Function Select Register (GPSR) 351 * - ipsr: IPSR field 352 * - fn: Function name, also referring to the IPSR field 353 */ 354 #define PINMUX_IPSR_GPSR(ipsr, fn) \ 355 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) 356 357 /* 358 * Describe a pinmux configuration without GPIO function that needs 359 * configuration in a Peripheral Function Select Register (IPSR), and where the 360 * pinmux function has a representation in a Module Select Register (MOD_SEL). 361 * - ipsr: IPSR field (unused, for documentation purposes only) 362 * - fn: Function name, also referring to the IPSR field 363 * - msel: Module selector 364 */ 365 #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \ 366 PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel) 367 368 /* 369 * Describe a pinmux configuration with GPIO function where the pinmux function 370 * has no representation in a Peripheral Function Select Register (IPSR), but 371 * instead solely depends on a group selection. 372 * - gpsr: GPSR field 373 * - fn: Function name, also referring to the GPSR field 374 * - gsel: Group selector 375 */ 376 #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \ 377 PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel) 378 379 /* 380 * Describe a pinmux configuration with GPIO function that needs configuration 381 * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral 382 * Function Select Register (GPSR), and where the pinmux function has a 383 * representation in a Module Select Register (MOD_SEL). 384 * - ipsr: IPSR field 385 * - fn: Function name, also referring to the IPSR field 386 * - msel: Module selector 387 */ 388 #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ 389 PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) 390 391 /* 392 * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with 393 * an additional select register that controls physical multiplexing 394 * with another pin. 395 * - ipsr: IPSR field 396 * - fn: Function name, also referring to the IPSR field 397 * - psel: Physical multiplexing selector 398 * - msel: Module selector 399 */ 400 #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \ 401 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr) 402 403 /* 404 * Describe a pinmux configuration in which a pin is physically multiplexed 405 * with other pins. 406 * - ipsr: IPSR field 407 * - fn: Function name 408 * - psel: Physical multiplexing selector 409 */ 410 #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ 411 PINMUX_DATA(fn##_MARK, FN_##psel, FN_##ipsr) 412 413 /* 414 * Describe a pinmux configuration for a single-function pin with GPIO 415 * capability. 416 * - fn: Function name 417 */ 418 #define PINMUX_SINGLE(fn) \ 419 PINMUX_DATA(fn##_MARK, FN_##fn) 420 421 /* 422 * GP port style (32 ports banks) 423 */ 424 425 #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ 426 fn(bank, pin, GP_##bank##_##pin, sfx, cfg) 427 #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) 428 429 #define PORT_GP_CFG_2(bank, fn, sfx, cfg) \ 430 PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ 431 PORT_GP_CFG_1(bank, 1, fn, sfx, cfg) 432 #define PORT_GP_2(bank, fn, sfx) PORT_GP_CFG_2(bank, fn, sfx, 0) 433 434 #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ 435 PORT_GP_CFG_2(bank, fn, sfx, cfg), \ 436 PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ 437 PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) 438 #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) 439 440 #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ 441 PORT_GP_CFG_4(bank, fn, sfx, cfg), \ 442 PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ 443 PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) 444 #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) 445 446 #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ 447 PORT_GP_CFG_6(bank, fn, sfx, cfg), \ 448 PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ 449 PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) 450 #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) 451 452 #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ 453 PORT_GP_CFG_8(bank, fn, sfx, cfg), \ 454 PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) 455 #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) 456 457 #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \ 458 PORT_GP_CFG_9(bank, fn, sfx, cfg), \ 459 PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) 460 #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) 461 462 #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ 463 PORT_GP_CFG_10(bank, fn, sfx, cfg), \ 464 PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) 465 #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) 466 467 #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ 468 PORT_GP_CFG_11(bank, fn, sfx, cfg), \ 469 PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) 470 #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) 471 472 #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ 473 PORT_GP_CFG_12(bank, fn, sfx, cfg), \ 474 PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ 475 PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) 476 #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) 477 478 #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ 479 PORT_GP_CFG_14(bank, fn, sfx, cfg), \ 480 PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) 481 #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) 482 483 #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ 484 PORT_GP_CFG_15(bank, fn, sfx, cfg), \ 485 PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) 486 #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) 487 488 #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ 489 PORT_GP_CFG_16(bank, fn, sfx, cfg), \ 490 PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) 491 #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) 492 493 #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ 494 PORT_GP_CFG_17(bank, fn, sfx, cfg), \ 495 PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) 496 #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) 497 498 #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ 499 PORT_GP_CFG_18(bank, fn, sfx, cfg), \ 500 PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ 501 PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) 502 #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) 503 504 #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \ 505 PORT_GP_CFG_20(bank, fn, sfx, cfg), \ 506 PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) 507 #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) 508 509 #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \ 510 PORT_GP_CFG_21(bank, fn, sfx, cfg), \ 511 PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) 512 #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0) 513 514 #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ 515 PORT_GP_CFG_22(bank, fn, sfx, cfg), \ 516 PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) 517 #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) 518 519 #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ 520 PORT_GP_CFG_23(bank, fn, sfx, cfg), \ 521 PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) 522 #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) 523 524 #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \ 525 PORT_GP_CFG_24(bank, fn, sfx, cfg), \ 526 PORT_GP_CFG_1(bank, 24, fn, sfx, cfg) 527 #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0) 528 529 #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ 530 PORT_GP_CFG_25(bank, fn, sfx, cfg), \ 531 PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) 532 #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) 533 534 #define PORT_GP_CFG_27(bank, fn, sfx, cfg) \ 535 PORT_GP_CFG_26(bank, fn, sfx, cfg), \ 536 PORT_GP_CFG_1(bank, 26, fn, sfx, cfg) 537 #define PORT_GP_27(bank, fn, sfx) PORT_GP_CFG_27(bank, fn, sfx, 0) 538 539 #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ 540 PORT_GP_CFG_27(bank, fn, sfx, cfg), \ 541 PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) 542 #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) 543 544 #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ 545 PORT_GP_CFG_28(bank, fn, sfx, cfg), \ 546 PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) 547 #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) 548 549 #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ 550 PORT_GP_CFG_29(bank, fn, sfx, cfg), \ 551 PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) 552 #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) 553 554 #define PORT_GP_CFG_31(bank, fn, sfx, cfg) \ 555 PORT_GP_CFG_30(bank, fn, sfx, cfg), \ 556 PORT_GP_CFG_1(bank, 30, fn, sfx, cfg) 557 #define PORT_GP_31(bank, fn, sfx) PORT_GP_CFG_31(bank, fn, sfx, 0) 558 559 #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ 560 PORT_GP_CFG_31(bank, fn, sfx, cfg), \ 561 PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) 562 #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) 563 564 #define PORT_GP_32_REV(bank, fn, sfx) \ 565 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ 566 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ 567 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ 568 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ 569 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ 570 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ 571 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ 572 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ 573 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ 574 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ 575 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ 576 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ 577 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ 578 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ 579 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ 580 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) 581 582 /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ 583 #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx 584 #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str) 585 586 /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ 587 #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ 588 { \ 589 .pin = (bank * 32) + _pin, \ 590 .name = __stringify(_name), \ 591 .enum_id = _name##_DATA, \ 592 .configs = cfg, \ 593 } 594 #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused) 595 596 /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ 597 #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) 598 #define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused) 599 600 /* 601 * GP_ASSIGN_LAST() - Expand to an enum definition for the last GP pin 602 * 603 * The largest GP pin index is obtained by taking the size of a union, 604 * containing one array per GP pin, sized by the corresponding pin index. 605 * As the fields in the CPU_ALL_GP() macro definition are separated by commas, 606 * while the members of a union must be terminated by semicolons, the commas 607 * are absorbed by wrapping them inside dummy attributes. 608 */ 609 #define _GP_ENTRY(bank, pin, name, sfx, cfg) \ 610 deprecated)); char name[(bank * 32) + pin] __attribute__((deprecated 611 #define GP_ASSIGN_LAST() \ 612 GP_LAST = sizeof(union { \ 613 char dummy[0] __attribute__((deprecated, \ 614 CPU_ALL_GP(_GP_ENTRY, unused), \ 615 deprecated)); \ 616 }) 617 618 /* 619 * PORT style (linear pin space) 620 */ 621 622 #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) 623 624 #define PORT_10(pn, fn, pfx, sfx) \ 625 PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ 626 PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ 627 PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ 628 PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ 629 PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) 630 631 #define PORT_90(pn, fn, pfx, sfx) \ 632 PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ 633 PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ 634 PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ 635 PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ 636 PORT_10(pn+90, fn, pfx##9, sfx) 637 638 /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ 639 #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx 640 #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 641 642 /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ 643 #define PINMUX_GPIO(_pin) \ 644 [GPIO_##_pin] = { \ 645 .pin = (u16)-1, \ 646 .name = __stringify(GPIO_##_pin), \ 647 .enum_id = _pin##_DATA, \ 648 } 649 650 /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ 651 #define SH_PFC_PIN_CFG(_pin, cfgs) \ 652 { \ 653 .pin = _pin, \ 654 .name = __stringify(PORT##_pin), \ 655 .enum_id = PORT##_pin##_DATA, \ 656 .configs = cfgs, \ 657 } 658 659 /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, 660 * PORT_name_OUT, PORT_name_IN marks 661 */ 662 #define _PORT_DATA(pn, pfx, sfx) \ 663 PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ 664 PORT##pfx##_OUT, PORT##pfx##_IN) 665 #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) 666 667 /* 668 * PORT_ASSIGN_LAST() - Expand to an enum definition for the last PORT pin 669 * 670 * The largest PORT pin index is obtained by taking the size of a union, 671 * containing one array per PORT pin, sized by the corresponding pin index. 672 * As the fields in the CPU_ALL_PORT() macro definition are separated by 673 * commas, while the members of a union must be terminated by semicolons, the 674 * commas are absorbed by wrapping them inside dummy attributes. 675 */ 676 #define _PORT_ENTRY(pn, pfx, sfx) \ 677 deprecated)); char pfx[pn] __attribute__((deprecated 678 #define PORT_ASSIGN_LAST() \ 679 PORT_LAST = sizeof(union { \ 680 char dummy[0] __attribute__((deprecated, \ 681 CPU_ALL_PORT(_PORT_ENTRY, PORT, unused), \ 682 deprecated)); \ 683 }) 684 685 /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ 686 #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ 687 [gpio - (base)] = { \ 688 .name = __stringify(gpio), \ 689 .enum_id = data_or_mark, \ 690 } 691 #define GPIO_FN(str) \ 692 PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) 693 694 /* 695 * Pins not associated with a GPIO port 696 */ 697 698 #define PIN_NOGP_CFG(pin, name, fn, cfg) fn(pin, name, cfg) 699 #define PIN_NOGP(pin, name, fn) fn(pin, name, 0) 700 701 /* NOGP_ALL - Expand to a list of PIN_id */ 702 #define _NOGP_ALL(pin, name, cfg) PIN_##pin 703 #define NOGP_ALL() CPU_ALL_NOGP(_NOGP_ALL) 704 705 /* PINMUX_NOGP_ALL - Expand to a list of sh_pfc_pin entries */ 706 #define _NOGP_PINMUX(_pin, _name, cfg) \ 707 { \ 708 .pin = PIN_##_pin, \ 709 .name = "PIN_" _name, \ 710 .configs = SH_PFC_PIN_CFG_NO_GPIO | cfg, \ 711 } 712 #define PINMUX_NOGP_ALL() CPU_ALL_NOGP(_NOGP_PINMUX) 713 714 /* 715 * PORTnCR helper macro for SH-Mobile/R-Mobile 716 */ 717 #define PORTCR(nr, reg) \ 718 { \ 719 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ 720 GROUP(2, 2, 1, 3), \ 721 GROUP( \ 722 /* PULMD[1:0], handled by .set_bias() */ \ 723 0, 0, 0, 0, \ 724 /* IE and OE */ \ 725 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ 726 /* SEC, not supported */ \ 727 0, 0, \ 728 /* PTMD[2:0] */ \ 729 PORT##nr##_FN0, PORT##nr##_FN1, \ 730 PORT##nr##_FN2, PORT##nr##_FN3, \ 731 PORT##nr##_FN4, PORT##nr##_FN5, \ 732 PORT##nr##_FN6, PORT##nr##_FN7 \ 733 )) \ 734 } 735 736 /* 737 * GPIO number helper macro for R-Car 738 */ 739 #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) 740 741 #include <linux/bug.h> 742 #endif /* __SH_PFC_H */ 743