1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc.
4 *
5 * Dave Liu <daveliu@freescale.com>
6 * based on source code of Shlomi Gridish
7 */
8
9 #include <common.h>
10 #include <linux/errno.h>
11 #include <asm/io.h>
12 #include <asm/immap_83xx.h>
13
14 #define NUM_OF_PINS 32
15
16 /** qe_cfg_iopin configure one io pin setting
17 *
18 * @par_io: pointer to parallel I/O base
19 * @port: io pin port
20 * @pin: io pin number which get configured
21 * @dir: direction of io pin 2 bits valid
22 * 00 = pin disabled
23 * 01 = output
24 * 10 = input
25 * 11 = pin is I/O
26 * @open_drain: is pin open drain
27 * @assign: pin assignment registers select the function of the pin
28 */
qe_cfg_iopin(qepio83xx_t * par_io,u8 port,u8 pin,int dir,int open_drain,int assign)29 static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
30 int open_drain, int assign)
31 {
32 u32 dbit_mask;
33 u32 dbit_dir;
34 u32 dbit_asgn;
35 u32 bit_mask;
36 u32 tmp_val;
37 int offset;
38
39 offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
40
41 /* Calculate pin location and 2bit mask and dir */
42 dbit_mask = (u32)(0x3 << offset);
43 dbit_dir = (u32)(dir << offset);
44
45 /* Setup the direction */
46 tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
47 in_be32(&par_io->ioport[port].dir2) :
48 in_be32(&par_io->ioport[port].dir1);
49
50 if (pin > (NUM_OF_PINS / 2) - 1) {
51 out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
52 out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
53 } else {
54 out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
55 out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
56 }
57
58 /* Calculate pin location for 1bit mask */
59 bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
60
61 /* Setup the open drain */
62 tmp_val = in_be32(&par_io->ioport[port].podr);
63 if (open_drain)
64 out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
65 else
66 out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
67
68 /* Setup the assignment */
69 tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
70 in_be32(&par_io->ioport[port].ppar2) :
71 in_be32(&par_io->ioport[port].ppar1);
72 dbit_asgn = (u32)(assign << offset);
73
74 /* Clear and set 2 bits mask */
75 if (pin > (NUM_OF_PINS / 2) - 1) {
76 out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
77 out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
78 } else {
79 out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
80 out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
81 }
82 }
83
84 #if !defined(CONFIG_PINCTRL)
85 /** qe_config_iopin configure one io pin setting
86 *
87 * @port: io pin port
88 * @pin: io pin number which get configured
89 * @dir: direction of io pin 2 bits valid
90 * 00 = pin disabled
91 * 01 = output
92 * 10 = input
93 * 11 = pin is I/O
94 * @open_drain: is pin open drain
95 * @assign: pin assignment registers select the function of the pin
96 */
qe_config_iopin(u8 port,u8 pin,int dir,int open_drain,int assign)97 void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
98 {
99 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
100 qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
101
102 qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
103 }
104 #endif
105