1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2016 Google, Inc 4 */ 5 6 #ifndef __ASM_ARCH_PCH_H 7 #define __ASM_ARCH_PCH_H 8 9 #define PMBASE 0x40 10 #define ACPI_CNTL 0x44 11 #define ACPI_EN (1 << 7) 12 13 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ 14 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ 15 #define GPIO_EN (1 << 4) 16 17 #define PCIEXBAR 0x60 18 19 #define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0) 20 21 /* RCB registers */ 22 #define OIC 0x31fe /* 16bit */ 23 #define HPTC 0x3404 /* 32bit */ 24 #define FD 0x3418 /* 32bit */ 25 26 /* Function Disable 1 RCBA 0x3418 */ 27 #define PCH_DISABLE_ALWAYS (1 << 0) 28 29 /* PM registers */ 30 #define TCO1_CNT 0x60 31 #define TCO_TMR_HLT (1 << 11) 32 33 34 /* Device 0:0.0 PCI configuration space */ 35 36 #define EPBAR 0x40 37 #define MCHBAR 0x48 38 #define PCIEXBAR 0x60 39 #define DMIBAR 0x68 40 #define GGC 0x50 /* GMCH Graphics Control */ 41 #define DEVEN 0x54 /* Device Enable */ 42 #define DEVEN_D7EN (1 << 14) 43 #define DEVEN_D4EN (1 << 7) 44 #define DEVEN_D3EN (1 << 5) 45 #define DEVEN_D2EN (1 << 4) 46 #define DEVEN_D1F0EN (1 << 3) 47 #define DEVEN_D1F1EN (1 << 2) 48 #define DEVEN_D1F2EN (1 << 1) 49 #define DEVEN_D0EN (1 << 0) 50 #define DPR 0x5c 51 #define DPR_EPM (1 << 2) 52 #define DPR_PRS (1 << 1) 53 #define DPR_SIZE_MASK 0xff0 54 55 #define MCHBAR_PEI_VERSION 0x5034 56 #define BIOS_RESET_CPL 0x5da8 57 #define EDRAMBAR 0x5408 58 #define MCH_PAIR 0x5418 59 #define GDXCBAR 0x5420 60 61 #define PAM0 0x80 62 #define PAM1 0x81 63 #define PAM2 0x82 64 #define PAM3 0x83 65 #define PAM4 0x84 66 #define PAM5 0x85 67 #define PAM6 0x86 68 69 /* PCODE MMIO communications live in the MCHBAR. */ 70 #define BIOS_MAILBOX_INTERFACE 0x5da4 71 #define MAILBOX_RUN_BUSY (1 << 31) 72 #define MAILBOX_BIOS_CMD_READ_PCS 1 73 #define MAILBOX_BIOS_CMD_WRITE_PCS 2 74 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 75 #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 76 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa 77 #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb 78 #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26 79 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27 80 /* Errors are returned back in bits 7:0. */ 81 #define MAILBOX_BIOS_ERROR_NONE 0 82 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 83 #define MAILBOX_BIOS_ERROR_TIMEOUT 2 84 #define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 85 #define MAILBOX_BIOS_ERROR_RESERVED 4 86 #define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 87 #define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 88 #define MAILBOX_BIOS_ERROR_VR_ERROR 7 89 /* Data is passed through bits 31:0 of the data register. */ 90 #define BIOS_MAILBOX_DATA 0x5da0 91 92 /* SATA IOBP Registers */ 93 #define SATA_IOBP_SP0_SECRT88 0xea002688 94 #define SATA_IOBP_SP1_SECRT88 0xea002488 95 96 #define SATA_SECRT88_VADJ_MASK 0xff 97 #define SATA_SECRT88_VADJ_SHIFT 16 98 99 #define SATA_IOBP_SP0DTLE_DATA 0xea002550 100 #define SATA_IOBP_SP0DTLE_EDGE 0xea002554 101 #define SATA_IOBP_SP1DTLE_DATA 0xea002750 102 #define SATA_IOBP_SP1DTLE_EDGE 0xea002754 103 104 #define SATA_DTLE_MASK 0xF 105 #define SATA_DTLE_DATA_SHIFT 24 106 #define SATA_DTLE_EDGE_SHIFT 16 107 108 /* Power Management */ 109 #define PCH_PCS 0x84 110 #define PCH_PCS_PS_D3HOT 3 111 112 #define GEN_PMCON_1 0xa0 113 #define SMI_LOCK (1 << 4) 114 #define GEN_PMCON_2 0xa2 115 #define SYSTEM_RESET_STS (1 << 4) 116 #define THERMTRIP_STS (1 << 3) 117 #define SYSPWR_FLR (1 << 1) 118 #define PWROK_FLR (1 << 0) 119 #define GEN_PMCON_3 0xa4 120 #define SUS_PWR_FLR (1 << 14) 121 #define GEN_RST_STS (1 << 9) 122 #define RTC_BATTERY_DEAD (1 << 2) 123 #define PWR_FLR (1 << 1) 124 #define SLEEP_AFTER_POWER_FAIL (1 << 0) 125 #define GEN_PMCON_LOCK 0xa6 126 #define SLP_STR_POL_LOCK (1 << 2) 127 #define ACPI_BASE_LOCK (1 << 1) 128 #define PMIR 0xac 129 #define PMIR_CF9LOCK (1 << 31) 130 #define PMIR_CF9GR (1 << 20) 131 132 /* Broadwell PCH (Wildcat Point) */ 133 #define PCH_WPT_HSW_U_SAMPLE 0x9cc1 134 #define PCH_WPT_BDW_U_SAMPLE 0x9cc2 135 #define PCH_WPT_BDW_U_PREMIUM 0x9cc3 136 #define PCH_WPT_BDW_U_BASE 0x9cc5 137 #define PCH_WPT_BDW_Y_SAMPLE 0x9cc6 138 #define PCH_WPT_BDW_Y_PREMIUM 0x9cc7 139 #define PCH_WPT_BDW_Y_BASE 0x9cc9 140 #define PCH_WPT_BDW_H 0x9ccb 141 142 #define SA_IGD_OPROM_VENDEV 0x80860406 143 144 /* Dynamically determine if the part is ULT */ 145 bool cpu_is_ult(void); 146 147 u32 pch_iobp_read(u32 address); 148 int pch_iobp_write(u32 address, u32 data); 149 int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); 150 int pch_iobp_exec(u32 addr, u16 op_dcode, u8 route_id, u32 *data, u8 *resp); 151 152 #endif 153