1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2007-2008
4 * Stelian Pop <stelian@popies.net>
5 * Lead Tech Design <www.leadtechdesign.com>
6 */
7
8 #include <common.h>
9 #include <debug_uart.h>
10 #include <init.h>
11 #include <vsprintf.h>
12 #include <asm/global_data.h>
13 #include <asm/io.h>
14 #include <asm/arch/at91sam9261.h>
15 #include <asm/arch/at91sam9261_matrix.h>
16 #include <asm/arch/at91sam9_smc.h>
17 #include <asm/arch/at91_common.h>
18 #include <asm/arch/at91_rstc.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/gpio.h>
21 #include <lcd.h>
22 #include <atmel_lcdc.h>
23 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
24 #include <net.h>
25 #include <netdev.h>
26 #endif
27 #include <asm/mach-types.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 /* ------------------------------------------------------------------------- */
32 /*
33 * Miscelaneous platform dependent initialisations
34 */
35
36 #ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init(void)37 static void at91sam9261ek_nand_hw_init(void)
38 {
39 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
40 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
41 unsigned long csa;
42
43 /* Enable CS3 */
44 csa = readl(&matrix->ebicsa);
45 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
46
47 writel(csa, &matrix->ebicsa);
48
49 /* Configure SMC CS3 for NAND/SmartMedia */
50 #ifdef CONFIG_AT91SAM9G10EK
51 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
52 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
53 &smc->cs[3].setup);
54 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(7) |
55 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(7),
56 &smc->cs[3].pulse);
57 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
58 &smc->cs[3].cycle);
59 #else
60 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
61 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
62 &smc->cs[3].setup);
63 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
64 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
65 &smc->cs[3].pulse);
66 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
67 &smc->cs[3].cycle);
68 #endif
69 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
70 AT91_SMC_MODE_EXNW_DISABLE |
71 #ifdef CONFIG_SYS_NAND_DBW_16
72 AT91_SMC_MODE_DBW_16 |
73 #else /* CONFIG_SYS_NAND_DBW_8 */
74 AT91_SMC_MODE_DBW_8 |
75 #endif
76 AT91_SMC_MODE_TDF_CYCLE(2),
77 &smc->cs[3].mode);
78
79 at91_periph_clk_enable(ATMEL_ID_PIOC);
80
81 /* Configure RDY/BSY */
82 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
83
84 /* Enable NandFlash */
85 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
86
87 at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */
88 at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */
89 }
90 #endif
91
92 #ifdef CONFIG_DRIVER_DM9000
at91sam9261ek_dm9000_hw_init(void)93 static void at91sam9261ek_dm9000_hw_init(void)
94 {
95 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
96
97 /* Configure SMC CS2 for DM9000 */
98 #ifdef CONFIG_AT91SAM9G10EK
99 writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
100 AT91_SMC_SETUP_NRD(3) | AT91_SMC_SETUP_NCS_RD(0),
101 &smc->cs[2].setup);
102 writel(AT91_SMC_PULSE_NWE(6) | AT91_SMC_PULSE_NCS_WR(8) |
103 AT91_SMC_PULSE_NRD(6) | AT91_SMC_PULSE_NCS_RD(8),
104 &smc->cs[2].pulse);
105 writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
106 &smc->cs[2].cycle);
107 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
108 AT91_SMC_MODE_EXNW_DISABLE |
109 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
110 AT91_SMC_MODE_TDF_CYCLE(1),
111 &smc->cs[2].mode);
112 #else
113 writel(AT91_SMC_SETUP_NWE(3) | AT91_SMC_SETUP_NCS_WR(0) |
114 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
115 &smc->cs[2].setup);
116 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(8) |
117 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(8),
118 &smc->cs[2].pulse);
119 writel(AT91_SMC_CYCLE_NWE(16) | AT91_SMC_CYCLE_NRD(16),
120 &smc->cs[2].cycle);
121 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
122 AT91_SMC_MODE_EXNW_DISABLE |
123 AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
124 AT91_SMC_MODE_TDF_CYCLE(1),
125 &smc->cs[2].mode);
126 #endif
127
128 /* Configure Reset signal as output */
129 at91_set_gpio_output(AT91_PIN_PC10, 0);
130
131 /* Configure Interrupt pin as input, no pull-up */
132 at91_set_gpio_input(AT91_PIN_PC11, 0);
133 }
134 #endif
135
136 #ifdef CONFIG_LCD
137 vidinfo_t panel_info = {
138 .vl_col = 240,
139 .vl_row = 320,
140 .vl_clk = 4965000,
141 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
142 ATMEL_LCDC_INVFRAME_INVERTED,
143 .vl_bpix = 3,
144 .vl_tft = 1,
145 .vl_hsync_len = 5,
146 .vl_left_margin = 1,
147 .vl_right_margin = 33,
148 .vl_vsync_len = 1,
149 .vl_upper_margin = 1,
150 .vl_lower_margin = 0,
151 .mmio = ATMEL_BASE_LCDC,
152 };
153
lcd_enable(void)154 void lcd_enable(void)
155 {
156 at91_set_gpio_value(AT91_PIN_PA12, 0); /* power up */
157 }
158
lcd_disable(void)159 void lcd_disable(void)
160 {
161 at91_set_gpio_value(AT91_PIN_PA12, 1); /* power down */
162 }
163
at91sam9261ek_lcd_hw_init(void)164 static void at91sam9261ek_lcd_hw_init(void)
165 {
166 at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
167 at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */
168 at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */
169 at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */
170 at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */
171 at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */
172 at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */
173 at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */
174 at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */
175 at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */
176 at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */
177 at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */
178 at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */
179 at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */
180 at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */
181 at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */
182 at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */
183 at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */
184 at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */
185 at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */
186 at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */
187 at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */
188
189 at91_system_clk_enable(AT91_PMC_HCK1);
190
191 /* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
192 #ifdef CONFIG_AT91SAM9261EK
193 gd->fb_base = ATMEL_BASE_SRAM;
194 #endif
195 }
196
197 #ifdef CONFIG_LCD_INFO
198 #include <nand.h>
199 #include <version.h>
200
lcd_show_board_info(void)201 void lcd_show_board_info(void)
202 {
203 ulong dram_size, nand_size;
204 int i;
205 char temp[32];
206
207 lcd_printf ("%s\n", U_BOOT_VERSION);
208 lcd_printf ("(C) 2008 ATMEL Corp\n");
209 lcd_printf ("at91support@atmel.com\n");
210 lcd_printf ("%s CPU at %s MHz\n",
211 ATMEL_CPU_NAME,
212 strmhz(temp, get_cpu_clk_rate()));
213
214 dram_size = 0;
215 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
216 dram_size += gd->bd->bi_dram[i].size;
217 nand_size = 0;
218 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
219 nand_size += get_nand_dev_by_index(i)->size;
220 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
221 dram_size >> 20,
222 nand_size >> 20 );
223 }
224 #endif /* CONFIG_LCD_INFO */
225 #endif
226
227 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
board_debug_uart_init(void)228 void board_debug_uart_init(void)
229 {
230 at91_seriald_hw_init();
231 }
232 #endif
233
234 #ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f(void)235 int board_early_init_f(void)
236 {
237 #ifdef CONFIG_DEBUG_UART
238 debug_uart_init();
239 #endif
240 return 0;
241 }
242 #endif
243
board_init(void)244 int board_init(void)
245 {
246 #ifdef CONFIG_AT91SAM9G10EK
247 /* arch number of AT91SAM9G10EK-Board */
248 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G10EK;
249 #else
250 /* arch number of AT91SAM9261EK-Board */
251 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
252 #endif
253 /* adress of boot parameters */
254 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
255
256 #ifdef CONFIG_CMD_NAND
257 at91sam9261ek_nand_hw_init();
258 #endif
259 #ifdef CONFIG_DRIVER_DM9000
260 at91sam9261ek_dm9000_hw_init();
261 #endif
262 #ifdef CONFIG_LCD
263 at91sam9261ek_lcd_hw_init();
264 #endif
265 return 0;
266 }
267
268 #ifdef CONFIG_DRIVER_DM9000
board_eth_init(struct bd_info * bis)269 int board_eth_init(struct bd_info *bis)
270 {
271 return dm9000_initialize(bis);
272 }
273 #endif
274
dram_init(void)275 int dram_init(void)
276 {
277 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
278 CONFIG_SYS_SDRAM_SIZE);
279
280 return 0;
281 }
282
283 #ifdef CONFIG_RESET_PHY_R
reset_phy(void)284 void reset_phy(void)
285 {
286 #ifdef CONFIG_DRIVER_DM9000
287 /*
288 * Initialize ethernet HW addr prior to starting Linux,
289 * needed for nfsroot
290 */
291 eth_init();
292 #endif
293 }
294 #endif
295