1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <errno.h>
8 #include <asm/io.h>
9 #include <asm/arch/freeze_controller.h>
10 #include <asm/arch/scan_manager.h>
11 #include <asm/arch/system_manager.h>
12 #include <linux/delay.h>
13
14 /*
15 * Maximum polling loop to wait for IO scan chain engine becomes idle
16 * to prevent infinite loop. It is important that this is NOT changed
17 * to delay using timer functions, since at the time this function is
18 * called, timer might not yet be inited.
19 */
20 #define SCANMGR_MAX_DELAY 100
21
22 /*
23 * Maximum length of TDI_TDO packet payload is 128 bits,
24 * represented by (length - 1) in TDI_TDO header.
25 */
26 #define TDI_TDO_MAX_PAYLOAD 127
27
28 #define SCANMGR_STAT_ACTIVE (1 << 31)
29 #define SCANMGR_STAT_WFIFOCNT_MASK 0x70000000
30
31 static const struct socfpga_scan_manager *scan_manager_base =
32 (void *)(SOCFPGA_SCANMGR_ADDRESS);
33 static const struct socfpga_freeze_controller *freeze_controller_base =
34 (void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
35
36 /**
37 * scan_chain_engine_is_idle() - Check if the JTAG scan chain is idle
38 * @max_iter: Maximum number of iterations to wait for idle
39 *
40 * Function to check IO scan chain engine status and wait if the engine is
41 * is active. Poll the IO scan chain engine till maximum iteration reached.
42 */
scan_chain_engine_is_idle(u32 max_iter)43 static u32 scan_chain_engine_is_idle(u32 max_iter)
44 {
45 const u32 mask = SCANMGR_STAT_ACTIVE | SCANMGR_STAT_WFIFOCNT_MASK;
46 u32 status;
47
48 /* Poll the engine until the scan engine is inactive. */
49 do {
50 status = readl(&scan_manager_base->stat);
51 if (!(status & mask))
52 return 0;
53 } while (max_iter--);
54
55 return -ETIMEDOUT;
56 }
57
58 #define JTAG_BP_INSN (1 << 0)
59 #define JTAG_BP_TMS (1 << 1)
60 #define JTAG_BP_PAYLOAD (1 << 2)
61 #define JTAG_BP_2BYTE (1 << 3)
62 #define JTAG_BP_4BYTE (1 << 4)
63
64 /**
65 * scan_mgr_jtag_io() - Access the JTAG chain
66 * @flags: Control flags, used to configure the action on the JTAG
67 * @iarg: Instruction argument
68 * @parg: Payload argument or data
69 *
70 * Perform I/O on the JTAG chain
71 */
scan_mgr_jtag_io(const u32 flags,const u8 iarg,const u32 parg)72 static void scan_mgr_jtag_io(const u32 flags, const u8 iarg, const u32 parg)
73 {
74 u32 data = parg;
75
76 if (flags & JTAG_BP_INSN) { /* JTAG instruction */
77 /*
78 * The SCC JTAG register is LSB first, so make
79 * space for the instruction at the LSB.
80 */
81 data <<= 8;
82 if (flags & JTAG_BP_TMS) {
83 data |= (0 << 7); /* TMS instruction. */
84 data |= iarg & 0x3f; /* TMS arg is 6 bits. */
85 if (flags & JTAG_BP_PAYLOAD)
86 data |= (1 << 6);
87 } else {
88 data |= (1 << 7); /* TDI/TDO instruction. */
89 data |= iarg & 0xf; /* TDI/TDO arg is 4 bits. */
90 if (flags & JTAG_BP_PAYLOAD)
91 data |= (1 << 4);
92 }
93 }
94
95 if (flags & JTAG_BP_4BYTE)
96 writel(data, &scan_manager_base->fifo_quad_byte);
97 else if (flags & JTAG_BP_2BYTE)
98 writel(data & 0xffff, &scan_manager_base->fifo_double_byte);
99 else
100 writel(data & 0xff, &scan_manager_base->fifo_single_byte);
101 }
102
103 /**
104 * scan_mgr_jtag_insn_data() - Send JTAG instruction and data
105 * @iarg: Instruction argument
106 * @data: Associated data
107 * @dlen: Length of data in bits
108 *
109 * This function is used when programming the IO chains to submit the
110 * instruction followed by variable length payload.
111 */
112 static int
scan_mgr_jtag_insn_data(const u8 iarg,const unsigned long * data,const unsigned int dlen)113 scan_mgr_jtag_insn_data(const u8 iarg, const unsigned long *data,
114 const unsigned int dlen)
115 {
116 int i, j;
117
118 scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_2BYTE, iarg, dlen - 1);
119
120 /* 32 bits or more remain */
121 for (i = 0; i < dlen / 32; i++)
122 scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
123
124 if ((dlen % 32) > 24) { /* 31...24 bits remain */
125 scan_mgr_jtag_io(JTAG_BP_4BYTE, 0x0, data[i]);
126 } else if (dlen % 32) { /* 24...1 bit remain */
127 for (j = 0; j < dlen % 32; j += 8)
128 scan_mgr_jtag_io(0, 0x0, data[i] >> j);
129 }
130
131 return scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
132 }
133
134 /**
135 * scan_mgr_io_scan_chain_prg() - Program HPS IO Scan Chain
136 * @io_scan_chain_id: IO scan chain ID
137 */
scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)138 static int scan_mgr_io_scan_chain_prg(const unsigned int io_scan_chain_id)
139 {
140 u32 io_scan_chain_len_in_bits;
141 const unsigned long *iocsr_scan_chain;
142 unsigned int rem, idx = 0;
143 int ret;
144
145 ret = iocsr_get_config_table(io_scan_chain_id, &iocsr_scan_chain,
146 &io_scan_chain_len_in_bits);
147 if (ret)
148 return 1;
149
150 /*
151 * De-assert reinit if the IO scan chain is intended for HIO. In
152 * this, its the chain 3.
153 */
154 if (io_scan_chain_id == 3)
155 clrbits_le32(&freeze_controller_base->hioctrl,
156 SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
157
158 /*
159 * Check if the scan chain engine is inactive and the
160 * WFIFO is empty before enabling the IO scan chain
161 */
162 ret = scan_chain_engine_is_idle(SCANMGR_MAX_DELAY);
163 if (ret)
164 return ret;
165
166 /*
167 * Enable IO Scan chain based on scan chain id
168 * Note: only one chain can be enabled at a time
169 */
170 setbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
171
172 /* Program IO scan chain. */
173 while (io_scan_chain_len_in_bits) {
174 if (io_scan_chain_len_in_bits > 128)
175 rem = 128;
176 else
177 rem = io_scan_chain_len_in_bits;
178
179 ret = scan_mgr_jtag_insn_data(0x0, &iocsr_scan_chain[idx], rem);
180 if (ret)
181 goto error;
182 io_scan_chain_len_in_bits -= rem;
183 idx += 4;
184 }
185
186 /* Disable IO Scan chain when configuration done*/
187 clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
188 return 0;
189
190 error:
191 /* Disable IO Scan chain when error detected */
192 clrbits_le32(&scan_manager_base->en, 1 << io_scan_chain_id);
193 return ret;
194 }
195
scan_mgr_configure_iocsr(void)196 int scan_mgr_configure_iocsr(void)
197 {
198 int status = 0;
199
200 /* configure the IOCSR through scan chain */
201 status |= scan_mgr_io_scan_chain_prg(0);
202 status |= scan_mgr_io_scan_chain_prg(1);
203 status |= scan_mgr_io_scan_chain_prg(2);
204 status |= scan_mgr_io_scan_chain_prg(3);
205 return status;
206 }
207
208 /**
209 * scan_mgr_get_fpga_id() - Obtain FPGA JTAG ID
210 *
211 * This function obtains JTAG ID from the FPGA TAP controller.
212 */
scan_mgr_get_fpga_id(void)213 u32 scan_mgr_get_fpga_id(void)
214 {
215 const unsigned long data = 0;
216 u32 id = 0xffffffff;
217 int ret;
218
219 /* Enable HPS to talk to JTAG in the FPGA through the System Manager */
220 writel(0x1, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL);
221
222 /* Enable port 7 */
223 writel(0x80, &scan_manager_base->en);
224 /* write to CSW to make s2f_ntrst reset */
225 writel(0x02, &scan_manager_base->stat);
226
227 /* Add a pause */
228 mdelay(1);
229
230 /* write 0x00 to CSW to clear the s2f_ntrst */
231 writel(0, &scan_manager_base->stat);
232
233 /*
234 * Go to Test-Logic-Reset state.
235 * This sets TAP controller into IDCODE mode.
236 */
237 scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x1f | (1 << 5), 0x0);
238
239 /* Go to Run-Test/Idle -> DR-Scan -> Capture-DR -> Shift-DR state. */
240 scan_mgr_jtag_io(JTAG_BP_INSN | JTAG_BP_TMS, 0x02 | (1 << 4), 0x0);
241
242 /*
243 * Push 4 bytes of data through TDI->DR->TDO.
244 *
245 * Length of TDI data is 32bits (length - 1) and they are only
246 * zeroes as we care only for TDO data.
247 */
248 ret = scan_mgr_jtag_insn_data(0x4, &data, 32);
249 /* Read 32 bit from captured JTAG data. */
250 if (!ret)
251 id = readl(&scan_manager_base->fifo_quad_byte);
252
253 /* Disable all port */
254 writel(0, &scan_manager_base->en);
255 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_SCANMGRGRP_CTRL);
256
257 return id;
258 }
259