1menu "mpc85xx CPU" 2 depends on MPC85xx 3 4config SYS_CPU 5 default "mpc85xx" 6 7config CMD_ERRATA 8 bool "Enable the 'errata' command" 9 depends on MPC85xx 10 default y 11 help 12 This enables the 'errata' command which displays a list of errata 13 work-arounds which are enabled for the current board. 14 15choice 16 prompt "Target select" 17 optional 18 19config TARGET_SBC8548 20 bool "Support sbc8548" 21 select ARCH_MPC8548 22 23config TARGET_SOCRATES 24 bool "Support socrates" 25 select ARCH_MPC8544 26 27config TARGET_P3041DS 28 bool "Support P3041DS" 29 select PHYS_64BIT 30 select ARCH_P3041 31 select BOARD_LATE_INIT if CHAIN_OF_TRUST 32 imply CMD_SATA 33 imply PANIC_HANG 34 35config TARGET_P4080DS 36 bool "Support P4080DS" 37 select PHYS_64BIT 38 select ARCH_P4080 39 select BOARD_LATE_INIT if CHAIN_OF_TRUST 40 imply CMD_SATA 41 imply PANIC_HANG 42 43config TARGET_P5040DS 44 bool "Support P5040DS" 45 select PHYS_64BIT 46 select ARCH_P5040 47 select BOARD_LATE_INIT if CHAIN_OF_TRUST 48 imply CMD_SATA 49 imply PANIC_HANG 50 51config TARGET_MPC8541CDS 52 bool "Support MPC8541CDS" 53 select ARCH_MPC8541 54 select FSL_VIA 55 56config TARGET_MPC8548CDS 57 bool "Support MPC8548CDS" 58 select ARCH_MPC8548 59 select FSL_VIA 60 61config TARGET_MPC8555CDS 62 bool "Support MPC8555CDS" 63 select ARCH_MPC8555 64 select FSL_VIA 65 66config TARGET_MPC8568MDS 67 bool "Support MPC8568MDS" 68 select ARCH_MPC8568 69 70config TARGET_P1010RDB_PA 71 bool "Support P1010RDB_PA" 72 select ARCH_P1010 73 select BOARD_LATE_INIT if CHAIN_OF_TRUST 74 select SUPPORT_SPL 75 select SUPPORT_TPL 76 imply CMD_EEPROM 77 imply CMD_SATA 78 imply PANIC_HANG 79 80config TARGET_P1010RDB_PB 81 bool "Support P1010RDB_PB" 82 select ARCH_P1010 83 select BOARD_LATE_INIT if CHAIN_OF_TRUST 84 select SUPPORT_SPL 85 select SUPPORT_TPL 86 imply CMD_EEPROM 87 imply CMD_SATA 88 imply PANIC_HANG 89 90config TARGET_P1020RDB_PC 91 bool "Support P1020RDB-PC" 92 select SUPPORT_SPL 93 select SUPPORT_TPL 94 select ARCH_P1020 95 imply CMD_EEPROM 96 imply CMD_SATA 97 imply PANIC_HANG 98 99config TARGET_P1020RDB_PD 100 bool "Support P1020RDB-PD" 101 select SUPPORT_SPL 102 select SUPPORT_TPL 103 select ARCH_P1020 104 imply CMD_EEPROM 105 imply CMD_SATA 106 imply PANIC_HANG 107 108config TARGET_P2020RDB 109 bool "Support P2020RDB-PC" 110 select SUPPORT_SPL 111 select SUPPORT_TPL 112 select ARCH_P2020 113 imply CMD_EEPROM 114 imply CMD_SATA 115 imply SATA_SIL 116 117config TARGET_P2041RDB 118 bool "Support P2041RDB" 119 select ARCH_P2041 120 select BOARD_LATE_INIT if CHAIN_OF_TRUST 121 select PHYS_64BIT 122 imply CMD_SATA 123 imply FSL_SATA 124 125config TARGET_QEMU_PPCE500 126 bool "Support qemu-ppce500" 127 select ARCH_QEMU_E500 128 select PHYS_64BIT 129 130config TARGET_T1023RDB 131 bool "Support T1023RDB" 132 select ARCH_T1023 133 select BOARD_LATE_INIT if CHAIN_OF_TRUST 134 select SUPPORT_SPL 135 select PHYS_64BIT 136 select FSL_DDR_INTERACTIVE 137 imply CMD_EEPROM 138 imply PANIC_HANG 139 140config TARGET_T1024RDB 141 bool "Support T1024RDB" 142 select ARCH_T1024 143 select BOARD_LATE_INIT if CHAIN_OF_TRUST 144 select SUPPORT_SPL 145 select PHYS_64BIT 146 select FSL_DDR_INTERACTIVE 147 imply CMD_EEPROM 148 imply PANIC_HANG 149 150config TARGET_T1040RDB 151 bool "Support T1040RDB" 152 select ARCH_T1040 153 select BOARD_LATE_INIT if CHAIN_OF_TRUST 154 select SUPPORT_SPL 155 select PHYS_64BIT 156 imply PANIC_HANG 157 158config TARGET_T1040D4RDB 159 bool "Support T1040D4RDB" 160 select ARCH_T1040 161 select BOARD_LATE_INIT if CHAIN_OF_TRUST 162 select SUPPORT_SPL 163 select PHYS_64BIT 164 imply PANIC_HANG 165 166config TARGET_T1042RDB 167 bool "Support T1042RDB" 168 select ARCH_T1042 169 select BOARD_LATE_INIT if CHAIN_OF_TRUST 170 select SUPPORT_SPL 171 select PHYS_64BIT 172 173config TARGET_T1042D4RDB 174 bool "Support T1042D4RDB" 175 select ARCH_T1042 176 select BOARD_LATE_INIT if CHAIN_OF_TRUST 177 select SUPPORT_SPL 178 select PHYS_64BIT 179 imply PANIC_HANG 180 181config TARGET_T1042RDB_PI 182 bool "Support T1042RDB_PI" 183 select ARCH_T1042 184 select BOARD_LATE_INIT if CHAIN_OF_TRUST 185 select SUPPORT_SPL 186 select PHYS_64BIT 187 imply PANIC_HANG 188 189config TARGET_T2080QDS 190 bool "Support T2080QDS" 191 select ARCH_T2080 192 select BOARD_LATE_INIT if CHAIN_OF_TRUST 193 select SUPPORT_SPL 194 select PHYS_64BIT 195 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 196 select FSL_DDR_INTERACTIVE 197 imply CMD_SATA 198 199config TARGET_T2080RDB 200 bool "Support T2080RDB" 201 select ARCH_T2080 202 select BOARD_LATE_INIT if CHAIN_OF_TRUST 203 select SUPPORT_SPL 204 select PHYS_64BIT 205 imply CMD_SATA 206 imply PANIC_HANG 207 208config TARGET_T4160RDB 209 bool "Support T4160RDB" 210 select ARCH_T4160 211 select SUPPORT_SPL 212 select PHYS_64BIT 213 imply PANIC_HANG 214 215config TARGET_T4240RDB 216 bool "Support T4240RDB" 217 select ARCH_T4240 218 select SUPPORT_SPL 219 select PHYS_64BIT 220 select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE 221 imply CMD_SATA 222 imply PANIC_HANG 223 224config TARGET_KMP204X 225 bool "Support kmp204x" 226 select VENDOR_KM 227 228config TARGET_KMCENT2 229 bool "Support kmcent2" 230 select VENDOR_KM 231 232config TARGET_XPEDITE520X 233 bool "Support xpedite520x" 234 select ARCH_MPC8548 235 236config TARGET_XPEDITE537X 237 bool "Support xpedite537x" 238 select ARCH_MPC8572 239# Use DDR3 controller with DDR2 DIMMs on this board 240 select SYS_FSL_DDRC_GEN3 241 242config TARGET_XPEDITE550X 243 bool "Support xpedite550x" 244 select ARCH_P2020 245 246config TARGET_UCP1020 247 bool "Support uCP1020" 248 select ARCH_P1020 249 imply CMD_SATA 250 imply PANIC_HANG 251 252endchoice 253 254config ARCH_B4420 255 bool 256 select E500MC 257 select E6500 258 select FSL_LAW 259 select SYS_FSL_DDR_VER_47 260 select SYS_FSL_ERRATUM_A004477 261 select SYS_FSL_ERRATUM_A005871 262 select SYS_FSL_ERRATUM_A006379 263 select SYS_FSL_ERRATUM_A006384 264 select SYS_FSL_ERRATUM_A006475 265 select SYS_FSL_ERRATUM_A006593 266 select SYS_FSL_ERRATUM_A007075 267 select SYS_FSL_ERRATUM_A007186 268 select SYS_FSL_ERRATUM_A007212 269 select SYS_FSL_ERRATUM_A009942 270 select SYS_FSL_HAS_DDR3 271 select SYS_FSL_HAS_SEC 272 select SYS_FSL_QORIQ_CHASSIS2 273 select SYS_FSL_SEC_BE 274 select SYS_FSL_SEC_COMPAT_4 275 select SYS_PPC64 276 select FSL_IFC 277 imply CMD_EEPROM 278 imply CMD_NAND 279 imply CMD_REGINFO 280 281config ARCH_B4860 282 bool 283 select E500MC 284 select E6500 285 select FSL_LAW 286 select SYS_FSL_DDR_VER_47 287 select SYS_FSL_ERRATUM_A004477 288 select SYS_FSL_ERRATUM_A005871 289 select SYS_FSL_ERRATUM_A006379 290 select SYS_FSL_ERRATUM_A006384 291 select SYS_FSL_ERRATUM_A006475 292 select SYS_FSL_ERRATUM_A006593 293 select SYS_FSL_ERRATUM_A007075 294 select SYS_FSL_ERRATUM_A007186 295 select SYS_FSL_ERRATUM_A007212 296 select SYS_FSL_ERRATUM_A007907 297 select SYS_FSL_ERRATUM_A009942 298 select SYS_FSL_HAS_DDR3 299 select SYS_FSL_HAS_SEC 300 select SYS_FSL_QORIQ_CHASSIS2 301 select SYS_FSL_SEC_BE 302 select SYS_FSL_SEC_COMPAT_4 303 select SYS_PPC64 304 select FSL_IFC 305 imply CMD_EEPROM 306 imply CMD_NAND 307 imply CMD_REGINFO 308 309config ARCH_BSC9131 310 bool 311 select FSL_LAW 312 select SYS_FSL_DDR_VER_44 313 select SYS_FSL_ERRATUM_A004477 314 select SYS_FSL_ERRATUM_A005125 315 select SYS_FSL_ERRATUM_ESDHC111 316 select SYS_FSL_HAS_DDR3 317 select SYS_FSL_HAS_SEC 318 select SYS_FSL_SEC_BE 319 select SYS_FSL_SEC_COMPAT_4 320 select FSL_IFC 321 imply CMD_EEPROM 322 imply CMD_NAND 323 imply CMD_REGINFO 324 325config ARCH_BSC9132 326 bool 327 select FSL_LAW 328 select SYS_FSL_DDR_VER_46 329 select SYS_FSL_ERRATUM_A004477 330 select SYS_FSL_ERRATUM_A005125 331 select SYS_FSL_ERRATUM_A005434 332 select SYS_FSL_ERRATUM_ESDHC111 333 select SYS_FSL_ERRATUM_I2C_A004447 334 select SYS_FSL_ERRATUM_IFC_A002769 335 select FSL_PCIE_RESET 336 select SYS_FSL_HAS_DDR3 337 select SYS_FSL_HAS_SEC 338 select SYS_FSL_SEC_BE 339 select SYS_FSL_SEC_COMPAT_4 340 select SYS_PPC_E500_USE_DEBUG_TLB 341 select FSL_IFC 342 imply CMD_EEPROM 343 imply CMD_MTDPARTS 344 imply CMD_NAND 345 imply CMD_PCI 346 imply CMD_REGINFO 347 348config ARCH_C29X 349 bool 350 select FSL_LAW 351 select SYS_FSL_DDR_VER_46 352 select SYS_FSL_ERRATUM_A005125 353 select SYS_FSL_ERRATUM_ESDHC111 354 select FSL_PCIE_RESET 355 select SYS_FSL_HAS_DDR3 356 select SYS_FSL_HAS_SEC 357 select SYS_FSL_SEC_BE 358 select SYS_FSL_SEC_COMPAT_6 359 select SYS_PPC_E500_USE_DEBUG_TLB 360 select FSL_IFC 361 imply CMD_NAND 362 imply CMD_PCI 363 imply CMD_REGINFO 364 365config ARCH_MPC8536 366 bool 367 select FSL_LAW 368 select SYS_FSL_ERRATUM_A004508 369 select SYS_FSL_ERRATUM_A005125 370 select FSL_PCIE_RESET 371 select SYS_FSL_HAS_DDR2 372 select SYS_FSL_HAS_DDR3 373 select SYS_FSL_HAS_SEC 374 select SYS_FSL_SEC_BE 375 select SYS_FSL_SEC_COMPAT_2 376 select SYS_PPC_E500_USE_DEBUG_TLB 377 select FSL_ELBC 378 imply CMD_NAND 379 imply CMD_SATA 380 imply CMD_REGINFO 381 382config ARCH_MPC8540 383 bool 384 select FSL_LAW 385 select SYS_FSL_HAS_DDR1 386 387config ARCH_MPC8541 388 bool 389 select FSL_LAW 390 select SYS_FSL_HAS_DDR1 391 select SYS_FSL_HAS_SEC 392 select SYS_FSL_SEC_BE 393 select SYS_FSL_SEC_COMPAT_2 394 395config ARCH_MPC8544 396 bool 397 select FSL_LAW 398 select SYS_FSL_ERRATUM_A005125 399 select FSL_PCIE_RESET 400 select SYS_FSL_HAS_DDR2 401 select SYS_FSL_HAS_SEC 402 select SYS_FSL_SEC_BE 403 select SYS_FSL_SEC_COMPAT_2 404 select SYS_PPC_E500_USE_DEBUG_TLB 405 select FSL_ELBC 406 407config ARCH_MPC8548 408 bool 409 select FSL_LAW 410 select SYS_FSL_ERRATUM_A005125 411 select SYS_FSL_ERRATUM_NMG_DDR120 412 select SYS_FSL_ERRATUM_NMG_LBC103 413 select SYS_FSL_ERRATUM_NMG_ETSEC129 414 select SYS_FSL_ERRATUM_I2C_A004447 415 select FSL_PCIE_RESET 416 select SYS_FSL_HAS_DDR2 417 select SYS_FSL_HAS_DDR1 418 select SYS_FSL_HAS_SEC 419 select SYS_FSL_SEC_BE 420 select SYS_FSL_SEC_COMPAT_2 421 select SYS_PPC_E500_USE_DEBUG_TLB 422 imply CMD_REGINFO 423 424config ARCH_MPC8555 425 bool 426 select FSL_LAW 427 select SYS_FSL_HAS_DDR1 428 select SYS_FSL_HAS_SEC 429 select SYS_FSL_SEC_BE 430 select SYS_FSL_SEC_COMPAT_2 431 432config ARCH_MPC8560 433 bool 434 select FSL_LAW 435 select SYS_FSL_HAS_DDR1 436 437config ARCH_MPC8568 438 bool 439 select FSL_LAW 440 select FSL_PCIE_RESET 441 select SYS_FSL_HAS_DDR2 442 select SYS_FSL_HAS_SEC 443 select SYS_FSL_SEC_BE 444 select SYS_FSL_SEC_COMPAT_2 445 446config ARCH_MPC8572 447 bool 448 select FSL_LAW 449 select SYS_FSL_ERRATUM_A004508 450 select SYS_FSL_ERRATUM_A005125 451 select SYS_FSL_ERRATUM_DDR_115 452 select SYS_FSL_ERRATUM_DDR111_DDR134 453 select FSL_PCIE_RESET 454 select SYS_FSL_HAS_DDR2 455 select SYS_FSL_HAS_DDR3 456 select SYS_FSL_HAS_SEC 457 select SYS_FSL_SEC_BE 458 select SYS_FSL_SEC_COMPAT_2 459 select SYS_PPC_E500_USE_DEBUG_TLB 460 select FSL_ELBC 461 imply CMD_NAND 462 463config ARCH_P1010 464 bool 465 select FSL_LAW 466 select SYS_FSL_ERRATUM_A004477 467 select SYS_FSL_ERRATUM_A004508 468 select SYS_FSL_ERRATUM_A005125 469 select SYS_FSL_ERRATUM_A005275 470 select SYS_FSL_ERRATUM_A006261 471 select SYS_FSL_ERRATUM_A007075 472 select SYS_FSL_ERRATUM_ESDHC111 473 select SYS_FSL_ERRATUM_I2C_A004447 474 select SYS_FSL_ERRATUM_IFC_A002769 475 select SYS_FSL_ERRATUM_P1010_A003549 476 select SYS_FSL_ERRATUM_SEC_A003571 477 select SYS_FSL_ERRATUM_IFC_A003399 478 select FSL_PCIE_RESET 479 select SYS_FSL_HAS_DDR3 480 select SYS_FSL_HAS_SEC 481 select SYS_FSL_SEC_BE 482 select SYS_FSL_SEC_COMPAT_4 483 select SYS_PPC_E500_USE_DEBUG_TLB 484 select FSL_IFC 485 imply CMD_EEPROM 486 imply CMD_MTDPARTS 487 imply CMD_NAND 488 imply CMD_SATA 489 imply CMD_PCI 490 imply CMD_REGINFO 491 imply FSL_SATA 492 493config ARCH_P1011 494 bool 495 select FSL_LAW 496 select SYS_FSL_ERRATUM_A004508 497 select SYS_FSL_ERRATUM_A005125 498 select SYS_FSL_ERRATUM_ELBC_A001 499 select SYS_FSL_ERRATUM_ESDHC111 500 select FSL_PCIE_DISABLE_ASPM 501 select SYS_FSL_HAS_DDR3 502 select SYS_FSL_HAS_SEC 503 select SYS_FSL_SEC_BE 504 select SYS_FSL_SEC_COMPAT_2 505 select SYS_PPC_E500_USE_DEBUG_TLB 506 select FSL_ELBC 507 508config ARCH_P1020 509 bool 510 select FSL_LAW 511 select SYS_FSL_ERRATUM_A004508 512 select SYS_FSL_ERRATUM_A005125 513 select SYS_FSL_ERRATUM_ELBC_A001 514 select SYS_FSL_ERRATUM_ESDHC111 515 select FSL_PCIE_DISABLE_ASPM 516 select FSL_PCIE_RESET 517 select SYS_FSL_HAS_DDR3 518 select SYS_FSL_HAS_SEC 519 select SYS_FSL_SEC_BE 520 select SYS_FSL_SEC_COMPAT_2 521 select SYS_PPC_E500_USE_DEBUG_TLB 522 select FSL_ELBC 523 imply CMD_NAND 524 imply CMD_SATA 525 imply CMD_PCI 526 imply CMD_REGINFO 527 imply SATA_SIL 528 529config ARCH_P1021 530 bool 531 select FSL_LAW 532 select SYS_FSL_ERRATUM_A004508 533 select SYS_FSL_ERRATUM_A005125 534 select SYS_FSL_ERRATUM_ELBC_A001 535 select SYS_FSL_ERRATUM_ESDHC111 536 select FSL_PCIE_DISABLE_ASPM 537 select FSL_PCIE_RESET 538 select SYS_FSL_HAS_DDR3 539 select SYS_FSL_HAS_SEC 540 select SYS_FSL_SEC_BE 541 select SYS_FSL_SEC_COMPAT_2 542 select SYS_PPC_E500_USE_DEBUG_TLB 543 select FSL_ELBC 544 imply CMD_REGINFO 545 imply CMD_NAND 546 imply CMD_SATA 547 imply CMD_REGINFO 548 imply SATA_SIL 549 550config ARCH_P1023 551 bool 552 select FSL_LAW 553 select SYS_FSL_ERRATUM_A004508 554 select SYS_FSL_ERRATUM_A005125 555 select SYS_FSL_ERRATUM_I2C_A004447 556 select FSL_PCIE_RESET 557 select SYS_FSL_HAS_DDR3 558 select SYS_FSL_HAS_SEC 559 select SYS_FSL_SEC_BE 560 select SYS_FSL_SEC_COMPAT_4 561 select FSL_ELBC 562 563config ARCH_P1024 564 bool 565 select FSL_LAW 566 select SYS_FSL_ERRATUM_A004508 567 select SYS_FSL_ERRATUM_A005125 568 select SYS_FSL_ERRATUM_ELBC_A001 569 select SYS_FSL_ERRATUM_ESDHC111 570 select FSL_PCIE_DISABLE_ASPM 571 select FSL_PCIE_RESET 572 select SYS_FSL_HAS_DDR3 573 select SYS_FSL_HAS_SEC 574 select SYS_FSL_SEC_BE 575 select SYS_FSL_SEC_COMPAT_2 576 select SYS_PPC_E500_USE_DEBUG_TLB 577 select FSL_ELBC 578 imply CMD_EEPROM 579 imply CMD_NAND 580 imply CMD_SATA 581 imply CMD_PCI 582 imply CMD_REGINFO 583 imply SATA_SIL 584 585config ARCH_P1025 586 bool 587 select FSL_LAW 588 select SYS_FSL_ERRATUM_A004508 589 select SYS_FSL_ERRATUM_A005125 590 select SYS_FSL_ERRATUM_ELBC_A001 591 select SYS_FSL_ERRATUM_ESDHC111 592 select FSL_PCIE_DISABLE_ASPM 593 select FSL_PCIE_RESET 594 select SYS_FSL_HAS_DDR3 595 select SYS_FSL_HAS_SEC 596 select SYS_FSL_SEC_BE 597 select SYS_FSL_SEC_COMPAT_2 598 select SYS_PPC_E500_USE_DEBUG_TLB 599 select FSL_ELBC 600 imply CMD_SATA 601 imply CMD_REGINFO 602 603config ARCH_P2020 604 bool 605 select FSL_LAW 606 select SYS_FSL_ERRATUM_A004477 607 select SYS_FSL_ERRATUM_A004508 608 select SYS_FSL_ERRATUM_A005125 609 select SYS_FSL_ERRATUM_ESDHC111 610 select SYS_FSL_ERRATUM_ESDHC_A001 611 select FSL_PCIE_RESET 612 select SYS_FSL_HAS_DDR3 613 select SYS_FSL_HAS_SEC 614 select SYS_FSL_SEC_BE 615 select SYS_FSL_SEC_COMPAT_2 616 select SYS_PPC_E500_USE_DEBUG_TLB 617 select FSL_ELBC 618 imply CMD_EEPROM 619 imply CMD_NAND 620 imply CMD_REGINFO 621 622config ARCH_P2041 623 bool 624 select E500MC 625 select FSL_LAW 626 select SYS_FSL_ERRATUM_A004510 627 select SYS_FSL_ERRATUM_A004849 628 select SYS_FSL_ERRATUM_A005275 629 select SYS_FSL_ERRATUM_A006261 630 select SYS_FSL_ERRATUM_CPU_A003999 631 select SYS_FSL_ERRATUM_DDR_A003 632 select SYS_FSL_ERRATUM_DDR_A003474 633 select SYS_FSL_ERRATUM_ESDHC111 634 select SYS_FSL_ERRATUM_I2C_A004447 635 select SYS_FSL_ERRATUM_NMG_CPU_A011 636 select SYS_FSL_ERRATUM_SRIO_A004034 637 select SYS_FSL_ERRATUM_USB14 638 select SYS_FSL_HAS_DDR3 639 select SYS_FSL_HAS_SEC 640 select SYS_FSL_QORIQ_CHASSIS1 641 select SYS_FSL_SEC_BE 642 select SYS_FSL_SEC_COMPAT_4 643 select FSL_ELBC 644 imply CMD_NAND 645 646config ARCH_P3041 647 bool 648 select E500MC 649 select FSL_LAW 650 select SYS_FSL_DDR_VER_44 651 select SYS_FSL_ERRATUM_A004510 652 select SYS_FSL_ERRATUM_A004849 653 select SYS_FSL_ERRATUM_A005275 654 select SYS_FSL_ERRATUM_A005812 655 select SYS_FSL_ERRATUM_A006261 656 select SYS_FSL_ERRATUM_CPU_A003999 657 select SYS_FSL_ERRATUM_DDR_A003 658 select SYS_FSL_ERRATUM_DDR_A003474 659 select SYS_FSL_ERRATUM_ESDHC111 660 select SYS_FSL_ERRATUM_I2C_A004447 661 select SYS_FSL_ERRATUM_NMG_CPU_A011 662 select SYS_FSL_ERRATUM_SRIO_A004034 663 select SYS_FSL_ERRATUM_USB14 664 select SYS_FSL_HAS_DDR3 665 select SYS_FSL_HAS_SEC 666 select SYS_FSL_QORIQ_CHASSIS1 667 select SYS_FSL_SEC_BE 668 select SYS_FSL_SEC_COMPAT_4 669 select FSL_ELBC 670 imply CMD_NAND 671 imply CMD_SATA 672 imply CMD_REGINFO 673 imply FSL_SATA 674 675config ARCH_P4080 676 bool 677 select E500MC 678 select FSL_LAW 679 select SYS_FSL_DDR_VER_44 680 select SYS_FSL_ERRATUM_A004510 681 select SYS_FSL_ERRATUM_A004580 682 select SYS_FSL_ERRATUM_A004849 683 select SYS_FSL_ERRATUM_A005812 684 select SYS_FSL_ERRATUM_A007075 685 select SYS_FSL_ERRATUM_CPC_A002 686 select SYS_FSL_ERRATUM_CPC_A003 687 select SYS_FSL_ERRATUM_CPU_A003999 688 select SYS_FSL_ERRATUM_DDR_A003 689 select SYS_FSL_ERRATUM_DDR_A003474 690 select SYS_FSL_ERRATUM_ELBC_A001 691 select SYS_FSL_ERRATUM_ESDHC111 692 select SYS_FSL_ERRATUM_ESDHC13 693 select SYS_FSL_ERRATUM_ESDHC135 694 select SYS_FSL_ERRATUM_I2C_A004447 695 select SYS_FSL_ERRATUM_NMG_CPU_A011 696 select SYS_FSL_ERRATUM_SRIO_A004034 697 select SYS_P4080_ERRATUM_CPU22 698 select SYS_P4080_ERRATUM_PCIE_A003 699 select SYS_P4080_ERRATUM_SERDES8 700 select SYS_P4080_ERRATUM_SERDES9 701 select SYS_P4080_ERRATUM_SERDES_A001 702 select SYS_P4080_ERRATUM_SERDES_A005 703 select SYS_FSL_HAS_DDR3 704 select SYS_FSL_HAS_SEC 705 select SYS_FSL_QORIQ_CHASSIS1 706 select SYS_FSL_SEC_BE 707 select SYS_FSL_SEC_COMPAT_4 708 select FSL_ELBC 709 imply CMD_SATA 710 imply CMD_REGINFO 711 imply SATA_SIL 712 713config ARCH_P5040 714 bool 715 select E500MC 716 select FSL_LAW 717 select SYS_FSL_DDR_VER_44 718 select SYS_FSL_ERRATUM_A004510 719 select SYS_FSL_ERRATUM_A004699 720 select SYS_FSL_ERRATUM_A005275 721 select SYS_FSL_ERRATUM_A005812 722 select SYS_FSL_ERRATUM_A006261 723 select SYS_FSL_ERRATUM_DDR_A003 724 select SYS_FSL_ERRATUM_DDR_A003474 725 select SYS_FSL_ERRATUM_ESDHC111 726 select SYS_FSL_ERRATUM_USB14 727 select SYS_FSL_HAS_DDR3 728 select SYS_FSL_HAS_SEC 729 select SYS_FSL_QORIQ_CHASSIS1 730 select SYS_FSL_SEC_BE 731 select SYS_FSL_SEC_COMPAT_4 732 select SYS_PPC64 733 select FSL_ELBC 734 imply CMD_SATA 735 imply CMD_REGINFO 736 imply FSL_SATA 737 738config ARCH_QEMU_E500 739 bool 740 741config ARCH_T1023 742 bool 743 select E500MC 744 select FSL_LAW 745 select SYS_FSL_DDR_VER_50 746 select SYS_FSL_ERRATUM_A008378 747 select SYS_FSL_ERRATUM_A008109 748 select SYS_FSL_ERRATUM_A009663 749 select SYS_FSL_ERRATUM_A009942 750 select SYS_FSL_ERRATUM_ESDHC111 751 select SYS_FSL_HAS_DDR3 752 select SYS_FSL_HAS_DDR4 753 select SYS_FSL_HAS_SEC 754 select SYS_FSL_QORIQ_CHASSIS2 755 select SYS_FSL_SEC_BE 756 select SYS_FSL_SEC_COMPAT_5 757 select FSL_IFC 758 imply CMD_EEPROM 759 imply CMD_NAND 760 imply CMD_REGINFO 761 762config ARCH_T1024 763 bool 764 select E500MC 765 select FSL_LAW 766 select SYS_FSL_DDR_VER_50 767 select SYS_FSL_ERRATUM_A008378 768 select SYS_FSL_ERRATUM_A008109 769 select SYS_FSL_ERRATUM_A009663 770 select SYS_FSL_ERRATUM_A009942 771 select SYS_FSL_ERRATUM_ESDHC111 772 select SYS_FSL_HAS_DDR3 773 select SYS_FSL_HAS_DDR4 774 select SYS_FSL_HAS_SEC 775 select SYS_FSL_QORIQ_CHASSIS2 776 select SYS_FSL_SEC_BE 777 select SYS_FSL_SEC_COMPAT_5 778 select FSL_IFC 779 imply CMD_EEPROM 780 imply CMD_NAND 781 imply CMD_MTDPARTS 782 imply CMD_REGINFO 783 784config ARCH_T1040 785 bool 786 select E500MC 787 select FSL_LAW 788 select SYS_FSL_DDR_VER_50 789 select SYS_FSL_ERRATUM_A008044 790 select SYS_FSL_ERRATUM_A008378 791 select SYS_FSL_ERRATUM_A008109 792 select SYS_FSL_ERRATUM_A009663 793 select SYS_FSL_ERRATUM_A009942 794 select SYS_FSL_ERRATUM_ESDHC111 795 select SYS_FSL_HAS_DDR3 796 select SYS_FSL_HAS_DDR4 797 select SYS_FSL_HAS_SEC 798 select SYS_FSL_QORIQ_CHASSIS2 799 select SYS_FSL_SEC_BE 800 select SYS_FSL_SEC_COMPAT_5 801 select FSL_IFC 802 imply CMD_MTDPARTS 803 imply CMD_NAND 804 imply CMD_REGINFO 805 806config ARCH_T1042 807 bool 808 select E500MC 809 select FSL_LAW 810 select SYS_FSL_DDR_VER_50 811 select SYS_FSL_ERRATUM_A008044 812 select SYS_FSL_ERRATUM_A008378 813 select SYS_FSL_ERRATUM_A008109 814 select SYS_FSL_ERRATUM_A009663 815 select SYS_FSL_ERRATUM_A009942 816 select SYS_FSL_ERRATUM_ESDHC111 817 select SYS_FSL_HAS_DDR3 818 select SYS_FSL_HAS_DDR4 819 select SYS_FSL_HAS_SEC 820 select SYS_FSL_QORIQ_CHASSIS2 821 select SYS_FSL_SEC_BE 822 select SYS_FSL_SEC_COMPAT_5 823 select FSL_IFC 824 imply CMD_MTDPARTS 825 imply CMD_NAND 826 imply CMD_REGINFO 827 828config ARCH_T2080 829 bool 830 select E500MC 831 select E6500 832 select FSL_LAW 833 select SYS_FSL_DDR_VER_47 834 select SYS_FSL_ERRATUM_A006379 835 select SYS_FSL_ERRATUM_A006593 836 select SYS_FSL_ERRATUM_A007186 837 select SYS_FSL_ERRATUM_A007212 838 select SYS_FSL_ERRATUM_A007815 839 select SYS_FSL_ERRATUM_A007907 840 select SYS_FSL_ERRATUM_A008109 841 select SYS_FSL_ERRATUM_A009942 842 select SYS_FSL_ERRATUM_ESDHC111 843 select FSL_PCIE_RESET 844 select SYS_FSL_HAS_DDR3 845 select SYS_FSL_HAS_SEC 846 select SYS_FSL_QORIQ_CHASSIS2 847 select SYS_FSL_SEC_BE 848 select SYS_FSL_SEC_COMPAT_4 849 select SYS_PPC64 850 select FSL_IFC 851 imply CMD_SATA 852 imply CMD_NAND 853 imply CMD_REGINFO 854 imply FSL_SATA 855 856config ARCH_T4160 857 bool 858 select E500MC 859 select E6500 860 select FSL_LAW 861 select SYS_FSL_DDR_VER_47 862 select SYS_FSL_ERRATUM_A004468 863 select SYS_FSL_ERRATUM_A005871 864 select SYS_FSL_ERRATUM_A006379 865 select SYS_FSL_ERRATUM_A006593 866 select SYS_FSL_ERRATUM_A007186 867 select SYS_FSL_ERRATUM_A007798 868 select SYS_FSL_ERRATUM_A009942 869 select SYS_FSL_HAS_DDR3 870 select SYS_FSL_HAS_SEC 871 select SYS_FSL_QORIQ_CHASSIS2 872 select SYS_FSL_SEC_BE 873 select SYS_FSL_SEC_COMPAT_4 874 select SYS_PPC64 875 select FSL_IFC 876 imply CMD_NAND 877 imply CMD_REGINFO 878 879config ARCH_T4240 880 bool 881 select E500MC 882 select E6500 883 select FSL_LAW 884 select SYS_FSL_DDR_VER_47 885 select SYS_FSL_ERRATUM_A004468 886 select SYS_FSL_ERRATUM_A005871 887 select SYS_FSL_ERRATUM_A006261 888 select SYS_FSL_ERRATUM_A006379 889 select SYS_FSL_ERRATUM_A006593 890 select SYS_FSL_ERRATUM_A007186 891 select SYS_FSL_ERRATUM_A007798 892 select SYS_FSL_ERRATUM_A007815 893 select SYS_FSL_ERRATUM_A007907 894 select SYS_FSL_ERRATUM_A008109 895 select SYS_FSL_ERRATUM_A009942 896 select SYS_FSL_HAS_DDR3 897 select SYS_FSL_HAS_SEC 898 select SYS_FSL_QORIQ_CHASSIS2 899 select SYS_FSL_SEC_BE 900 select SYS_FSL_SEC_COMPAT_4 901 select SYS_PPC64 902 select FSL_IFC 903 imply CMD_SATA 904 imply CMD_NAND 905 imply CMD_REGINFO 906 imply FSL_SATA 907 908config MPC85XX_HAVE_RESET_VECTOR 909 bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc" 910 depends on MPC85xx 911 912config BOOKE 913 bool 914 default y 915 916config E500 917 bool 918 default y 919 help 920 Enable PowerPC E500 cores, including e500v1, e500v2, e500mc 921 922config E500MC 923 bool 924 imply CMD_PCI 925 help 926 Enble PowerPC E500MC core 927 928config E6500 929 bool 930 help 931 Enable PowerPC E6500 core 932 933config FSL_LAW 934 bool 935 help 936 Use Freescale common code for Local Access Window 937 938config NXP_ESBC 939 bool "NXP_ESBC" 940 help 941 Enable Freescale Secure Boot feature. Normally selected 942 by defconfig. If unsure, do not change. 943 944config MAX_CPUS 945 int "Maximum number of CPUs permitted for MPC85xx" 946 default 12 if ARCH_T4240 947 default 8 if ARCH_P4080 || \ 948 ARCH_T4160 949 default 4 if ARCH_B4860 || \ 950 ARCH_P2041 || \ 951 ARCH_P3041 || \ 952 ARCH_P5040 || \ 953 ARCH_T1040 || \ 954 ARCH_T1042 || \ 955 ARCH_T2080 956 default 2 if ARCH_B4420 || \ 957 ARCH_BSC9132 || \ 958 ARCH_MPC8572 || \ 959 ARCH_P1020 || \ 960 ARCH_P1021 || \ 961 ARCH_P1023 || \ 962 ARCH_P1024 || \ 963 ARCH_P1025 || \ 964 ARCH_P2020 || \ 965 ARCH_T1023 || \ 966 ARCH_T1024 967 default 1 968 help 969 Set this number to the maximum number of possible CPUs in the SoC. 970 SoCs may have multiple clusters with each cluster may have multiple 971 ports. If some ports are reserved but higher ports are used for 972 cores, count the reserved ports. This will allocate enough memory 973 in spin table to properly handle all cores. 974 975config SYS_CCSRBAR_DEFAULT 976 hex "Default CCSRBAR address" 977 default 0xff700000 if ARCH_BSC9131 || \ 978 ARCH_BSC9132 || \ 979 ARCH_C29X || \ 980 ARCH_MPC8536 || \ 981 ARCH_MPC8540 || \ 982 ARCH_MPC8541 || \ 983 ARCH_MPC8544 || \ 984 ARCH_MPC8548 || \ 985 ARCH_MPC8555 || \ 986 ARCH_MPC8560 || \ 987 ARCH_MPC8568 || \ 988 ARCH_MPC8572 || \ 989 ARCH_P1010 || \ 990 ARCH_P1011 || \ 991 ARCH_P1020 || \ 992 ARCH_P1021 || \ 993 ARCH_P1024 || \ 994 ARCH_P1025 || \ 995 ARCH_P2020 996 default 0xff600000 if ARCH_P1023 997 default 0xfe000000 if ARCH_B4420 || \ 998 ARCH_B4860 || \ 999 ARCH_P2041 || \ 1000 ARCH_P3041 || \ 1001 ARCH_P4080 || \ 1002 ARCH_P5040 || \ 1003 ARCH_T1023 || \ 1004 ARCH_T1024 || \ 1005 ARCH_T1040 || \ 1006 ARCH_T1042 || \ 1007 ARCH_T2080 || \ 1008 ARCH_T4160 || \ 1009 ARCH_T4240 1010 default 0xe0000000 if ARCH_QEMU_E500 1011 help 1012 Default value of CCSRBAR comes from power-on-reset. It 1013 is fixed on each SoC. Some SoCs can have different value 1014 if changed by pre-boot regime. The value here must match 1015 the current value in SoC. If not sure, do not change. 1016 1017config SYS_FSL_ERRATUM_A004468 1018 bool 1019 1020config SYS_FSL_ERRATUM_A004477 1021 bool 1022 1023config SYS_FSL_ERRATUM_A004508 1024 bool 1025 1026config SYS_FSL_ERRATUM_A004580 1027 bool 1028 1029config SYS_FSL_ERRATUM_A004699 1030 bool 1031 1032config SYS_FSL_ERRATUM_A004849 1033 bool 1034 1035config SYS_FSL_ERRATUM_A004510 1036 bool 1037 1038config SYS_FSL_ERRATUM_A004510_SVR_REV 1039 hex 1040 depends on SYS_FSL_ERRATUM_A004510 1041 default 0x20 if ARCH_P4080 1042 default 0x10 1043 1044config SYS_FSL_ERRATUM_A004510_SVR_REV2 1045 hex 1046 depends on (SYS_FSL_ERRATUM_A004510 && (ARCH_P2041 || ARCH_P3041)) 1047 default 0x11 1048 1049config SYS_FSL_ERRATUM_A005125 1050 bool 1051 1052config SYS_FSL_ERRATUM_A005434 1053 bool 1054 1055config SYS_FSL_ERRATUM_A005812 1056 bool 1057 1058config SYS_FSL_ERRATUM_A005871 1059 bool 1060 1061config SYS_FSL_ERRATUM_A005275 1062 bool 1063 1064config SYS_FSL_ERRATUM_A006261 1065 bool 1066 1067config SYS_FSL_ERRATUM_A006379 1068 bool 1069 1070config SYS_FSL_ERRATUM_A006384 1071 bool 1072 1073config SYS_FSL_ERRATUM_A006475 1074 bool 1075 1076config SYS_FSL_ERRATUM_A006593 1077 bool 1078 1079config SYS_FSL_ERRATUM_A007075 1080 bool 1081 1082config SYS_FSL_ERRATUM_A007186 1083 bool 1084 1085config SYS_FSL_ERRATUM_A007212 1086 bool 1087 1088config SYS_FSL_ERRATUM_A007815 1089 bool 1090 1091config SYS_FSL_ERRATUM_A007798 1092 bool 1093 1094config SYS_FSL_ERRATUM_A007907 1095 bool 1096 1097config SYS_FSL_ERRATUM_A008044 1098 bool 1099 1100config SYS_FSL_ERRATUM_CPC_A002 1101 bool 1102 1103config SYS_FSL_ERRATUM_CPC_A003 1104 bool 1105 1106config SYS_FSL_ERRATUM_CPU_A003999 1107 bool 1108 1109config SYS_FSL_ERRATUM_ELBC_A001 1110 bool 1111 1112config SYS_FSL_ERRATUM_I2C_A004447 1113 bool 1114 1115config SYS_FSL_A004447_SVR_REV 1116 hex 1117 depends on SYS_FSL_ERRATUM_I2C_A004447 1118 default 0x00 if ARCH_MPC8548 1119 default 0x10 if ARCH_P1010 1120 default 0x11 if ARCH_P1023 || ARCH_P2041 || ARCH_BSC9132 1121 default 0x20 if ARCH_P3041 || ARCH_P4080 1122 1123config SYS_FSL_ERRATUM_IFC_A002769 1124 bool 1125 1126config SYS_FSL_ERRATUM_IFC_A003399 1127 bool 1128 1129config SYS_FSL_ERRATUM_NMG_CPU_A011 1130 bool 1131 1132config SYS_FSL_ERRATUM_NMG_ETSEC129 1133 bool 1134 1135config SYS_FSL_ERRATUM_NMG_LBC103 1136 bool 1137 1138config SYS_FSL_ERRATUM_P1010_A003549 1139 bool 1140 1141config SYS_FSL_ERRATUM_SATA_A001 1142 bool 1143 1144config SYS_FSL_ERRATUM_SEC_A003571 1145 bool 1146 1147config SYS_FSL_ERRATUM_SRIO_A004034 1148 bool 1149 1150config SYS_FSL_ERRATUM_USB14 1151 bool 1152 1153config SYS_P4080_ERRATUM_CPU22 1154 bool 1155 1156config SYS_P4080_ERRATUM_PCIE_A003 1157 bool 1158 1159config SYS_P4080_ERRATUM_SERDES8 1160 bool 1161 1162config SYS_P4080_ERRATUM_SERDES9 1163 bool 1164 1165config SYS_P4080_ERRATUM_SERDES_A001 1166 bool 1167 1168config SYS_P4080_ERRATUM_SERDES_A005 1169 bool 1170 1171config FSL_PCIE_DISABLE_ASPM 1172 bool 1173 1174config FSL_PCIE_RESET 1175 bool 1176 1177config SYS_FSL_QORIQ_CHASSIS1 1178 bool 1179 1180config SYS_FSL_QORIQ_CHASSIS2 1181 bool 1182 1183config SYS_FSL_NUM_LAWS 1184 int "Number of local access windows" 1185 depends on FSL_LAW 1186 default 32 if ARCH_B4420 || \ 1187 ARCH_B4860 || \ 1188 ARCH_P2041 || \ 1189 ARCH_P3041 || \ 1190 ARCH_P4080 || \ 1191 ARCH_P5040 || \ 1192 ARCH_T2080 || \ 1193 ARCH_T4160 || \ 1194 ARCH_T4240 1195 default 16 if ARCH_T1023 || \ 1196 ARCH_T1024 || \ 1197 ARCH_T1040 || \ 1198 ARCH_T1042 1199 default 12 if ARCH_BSC9131 || \ 1200 ARCH_BSC9132 || \ 1201 ARCH_C29X || \ 1202 ARCH_MPC8536 || \ 1203 ARCH_MPC8572 || \ 1204 ARCH_P1010 || \ 1205 ARCH_P1011 || \ 1206 ARCH_P1020 || \ 1207 ARCH_P1021 || \ 1208 ARCH_P1023 || \ 1209 ARCH_P1024 || \ 1210 ARCH_P1025 || \ 1211 ARCH_P2020 1212 default 10 if ARCH_MPC8544 || \ 1213 ARCH_MPC8548 || \ 1214 ARCH_MPC8568 1215 default 8 if ARCH_MPC8540 || \ 1216 ARCH_MPC8541 || \ 1217 ARCH_MPC8555 || \ 1218 ARCH_MPC8560 1219 help 1220 Number of local access windows. This is fixed per SoC. 1221 If not sure, do not change. 1222 1223config SYS_FSL_THREADS_PER_CORE 1224 int 1225 default 2 if E6500 1226 default 1 1227 1228config SYS_NUM_TLBCAMS 1229 int "Number of TLB CAM entries" 1230 default 64 if E500MC 1231 default 16 1232 help 1233 Number of TLB CAM entries for Book-E chips. 64 for E500MC, 1234 16 for other E500 SoCs. 1235 1236config SYS_PPC64 1237 bool 1238 1239config SYS_PPC_E500_USE_DEBUG_TLB 1240 bool 1241 1242config FSL_IFC 1243 bool 1244 1245config FSL_ELBC 1246 bool 1247 1248config SYS_PPC_E500_DEBUG_TLB 1249 int "Temporary TLB entry for external debugger" 1250 depends on SYS_PPC_E500_USE_DEBUG_TLB 1251 default 0 if ARCH_MPC8544 || ARCH_MPC8548 1252 default 1 if ARCH_MPC8536 1253 default 2 if ARCH_MPC8572 || \ 1254 ARCH_P1011 || \ 1255 ARCH_P1020 || \ 1256 ARCH_P1021 || \ 1257 ARCH_P1024 || \ 1258 ARCH_P1025 || \ 1259 ARCH_P2020 1260 default 3 if ARCH_P1010 || \ 1261 ARCH_BSC9132 || \ 1262 ARCH_C29X 1263 help 1264 Select a temporary TLB entry to be used during boot to work 1265 around limitations in e500v1 and e500v2 external debugger 1266 support. This reduces the portions of the boot code where 1267 breakpoints and single stepping do not work. The value of this 1268 symbol should be set to the TLB1 entry to be used for this 1269 purpose. If unsure, do not change. 1270 1271config SYS_FSL_IFC_CLK_DIV 1272 int "Divider of platform clock" 1273 depends on FSL_IFC 1274 default 2 if ARCH_B4420 || \ 1275 ARCH_B4860 || \ 1276 ARCH_T1024 || \ 1277 ARCH_T1023 || \ 1278 ARCH_T1040 || \ 1279 ARCH_T1042 || \ 1280 ARCH_T4160 || \ 1281 ARCH_T4240 1282 default 1 1283 help 1284 Defines divider of platform clock(clock input to 1285 IFC controller). 1286 1287config SYS_FSL_LBC_CLK_DIV 1288 int "Divider of platform clock" 1289 depends on FSL_ELBC || ARCH_MPC8540 || \ 1290 ARCH_MPC8548 || ARCH_MPC8541 || \ 1291 ARCH_MPC8555 || ARCH_MPC8560 || \ 1292 ARCH_MPC8568 1293 1294 default 2 if ARCH_P2041 || \ 1295 ARCH_P3041 || \ 1296 ARCH_P4080 || \ 1297 ARCH_P5040 1298 default 1 1299 1300 help 1301 Defines divider of platform clock(clock input to 1302 eLBC controller). 1303 1304config FSL_VIA 1305 bool 1306 1307source "board/emulation/qemu-ppce500/Kconfig" 1308source "board/freescale/corenet_ds/Kconfig" 1309source "board/freescale/mpc8541cds/Kconfig" 1310source "board/freescale/mpc8548cds/Kconfig" 1311source "board/freescale/mpc8555cds/Kconfig" 1312source "board/freescale/mpc8568mds/Kconfig" 1313source "board/freescale/p1010rdb/Kconfig" 1314source "board/freescale/p1_p2_rdb_pc/Kconfig" 1315source "board/freescale/p2041rdb/Kconfig" 1316source "board/freescale/t102xrdb/Kconfig" 1317source "board/freescale/t104xrdb/Kconfig" 1318source "board/freescale/t208xqds/Kconfig" 1319source "board/freescale/t208xrdb/Kconfig" 1320source "board/freescale/t4rdb/Kconfig" 1321source "board/keymile/Kconfig" 1322source "board/sbc8548/Kconfig" 1323source "board/socrates/Kconfig" 1324source "board/xes/xpedite520x/Kconfig" 1325source "board/xes/xpedite537x/Kconfig" 1326source "board/xes/xpedite550x/Kconfig" 1327source "board/Arcturus/ucp1020/Kconfig" 1328 1329endmenu 1330