1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Configuation settings for the Freescale MCF5329 FireEngine board. 4 * 5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 /* 10 * board/config.h - configuration options, board specific 11 */ 12 13 #ifndef _M5329EVB_H 14 #define _M5329EVB_H 15 16 /* 17 * High Level Configuration Options 18 * (easy to change) 19 */ 20 21 #define CONFIG_MCFUART 22 #define CONFIG_SYS_UART_PORT (0) 23 24 #undef CONFIG_WATCHDOG 25 #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ 26 27 #define CONFIG_SYS_UNIFY_CACHE 28 29 #ifdef CONFIG_MCFFEC 30 # define CONFIG_MII_INIT 1 31 # define CONFIG_SYS_DISCOVER_PHY 32 # define CONFIG_SYS_RX_ETH_BUFFER 8 33 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 34 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ 35 # ifndef CONFIG_SYS_DISCOVER_PHY 36 # define FECDUPLEX FULL 37 # define FECSPEED _100BASET 38 # else 39 # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 40 # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 41 # endif 42 # endif /* CONFIG_SYS_DISCOVER_PHY */ 43 #endif 44 45 #define CONFIG_MCFRTC 46 #undef RTC_DEBUG 47 48 /* Timer */ 49 #define CONFIG_MCFTMR 50 51 /* I2C */ 52 #define CONFIG_SYS_I2C 53 #define CONFIG_SYS_I2C_FSL 54 #define CONFIG_SYS_FSL_I2C_SPEED 80000 55 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 56 #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 57 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 58 59 #define CONFIG_UDP_CHECKSUM 60 61 #ifdef CONFIG_MCFFEC 62 # define CONFIG_IPADDR 192.162.1.2 63 # define CONFIG_NETMASK 255.255.255.0 64 # define CONFIG_SERVERIP 192.162.1.1 65 # define CONFIG_GATEWAYIP 192.162.1.1 66 #endif /* FEC_ENET */ 67 68 #define CONFIG_HOSTNAME "M5329EVB" 69 #define CONFIG_EXTRA_ENV_SETTINGS \ 70 "netdev=eth0\0" \ 71 "loadaddr=40010000\0" \ 72 "u-boot=u-boot.bin\0" \ 73 "load=tftp ${loadaddr) ${u-boot}\0" \ 74 "upd=run load; run prog\0" \ 75 "prog=prot off 0 3ffff;" \ 76 "era 0 3ffff;" \ 77 "cp.b ${loadaddr} 0 ${filesize};" \ 78 "save\0" \ 79 "" 80 81 #define CONFIG_PRAM 512 /* 512 KB */ 82 83 #define CONFIG_SYS_LOAD_ADDR 0x40010000 84 85 #define CONFIG_SYS_CLK 80000000 86 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 87 88 #define CONFIG_SYS_MBAR 0xFC000000 89 90 #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) 91 92 /* 93 * Low Level Configuration Settings 94 * (address mappings, register initial values, etc.) 95 * You should know what you are doing if you make changes here. 96 */ 97 /*----------------------------------------------------------------------- 98 * Definitions for initial stack pointer and data area (in DPRAM) 99 */ 100 #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 101 #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 102 #define CONFIG_SYS_INIT_RAM_CTRL 0x221 103 #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) 104 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 105 106 /*----------------------------------------------------------------------- 107 * Start addresses for the final memory configuration 108 * (Set up by the startup code) 109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 110 */ 111 #define CONFIG_SYS_SDRAM_BASE 0x40000000 112 #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ 113 #define CONFIG_SYS_SDRAM_CFG1 0x53722730 114 #define CONFIG_SYS_SDRAM_CFG2 0x56670000 115 #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 116 #define CONFIG_SYS_SDRAM_EMOD 0x40010000 117 #define CONFIG_SYS_SDRAM_MODE 0x018D0000 118 119 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 120 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 121 122 #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 123 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 124 125 /* 126 * For booting Linux, the board info and command line data 127 * have to be in the first 8 MB of memory, since this is 128 * the maximum mapped by the Linux kernel during initialization ?? 129 */ 130 #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 131 #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 132 133 /*----------------------------------------------------------------------- 134 * FLASH organization 135 */ 136 #ifdef CONFIG_SYS_FLASH_CFI 137 # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ 138 # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 139 # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 140 # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 141 #endif 142 143 #ifdef CONFIG_NANDFLASH_SIZE 144 # define CONFIG_SYS_MAX_NAND_DEVICE 1 145 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE 146 # define CONFIG_SYS_NAND_SIZE 1 147 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } 148 # define NAND_ALLOW_ERASE_ALL 1 149 # define CONFIG_JFFS2_NAND 1 150 # define CONFIG_JFFS2_DEV "nand0" 151 # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) 152 # define CONFIG_JFFS2_PART_OFFSET 0x00000000 153 #endif 154 155 #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 156 157 /* Configuration for environment 158 * Environment is embedded in u-boot in the second sector of the flash 159 */ 160 161 #define LDS_BOARD_TEXT \ 162 . = DEFINED(env_offset) ? env_offset : .; \ 163 env/embedded.o(.text*); 164 165 /*----------------------------------------------------------------------- 166 * Cache Configuration 167 */ 168 #define CONFIG_SYS_CACHELINE_SIZE 16 169 170 #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 171 CONFIG_SYS_INIT_RAM_SIZE - 8) 172 #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 173 CONFIG_SYS_INIT_RAM_SIZE - 4) 174 #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) 175 #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 176 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 177 CF_ACR_EN | CF_ACR_SM_ALL) 178 #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ 179 CF_CACR_DCM_P) 180 181 /*----------------------------------------------------------------------- 182 * Chipselect bank definitions 183 */ 184 /* 185 * CS0 - NOR Flash 1, 2, 4, or 8MB 186 * CS1 - CompactFlash and registers 187 * CS2 - NAND Flash 16, 32, or 64MB 188 * CS3 - Available 189 * CS4 - Available 190 * CS5 - Available 191 */ 192 #define CONFIG_SYS_CS0_BASE 0 193 #define CONFIG_SYS_CS0_MASK 0x007f0001 194 #define CONFIG_SYS_CS0_CTRL 0x00001fa0 195 196 #define CONFIG_SYS_CS1_BASE 0x10000000 197 #define CONFIG_SYS_CS1_MASK 0x001f0001 198 #define CONFIG_SYS_CS1_CTRL 0x002A3780 199 200 #ifdef CONFIG_NANDFLASH_SIZE 201 #define CONFIG_SYS_CS2_BASE 0x20000000 202 #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) 203 #define CONFIG_SYS_CS2_CTRL 0x00001f60 204 #endif 205 206 #endif /* _M5329EVB_H */ 207