1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * esd vme8349 U-Boot configuration file 4 * Copyright (c) 2008, 2009 esd gmbh Hannover Germany 5 * 6 * (C) Copyright 2006-2010 7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 8 * 9 * reinhard.arlt@esd-electronics.de 10 * Based on the MPC8349EMDS config. 11 */ 12 13 /* 14 * vme8349 board configuration file. 15 */ 16 17 #ifndef __CONFIG_H 18 #define __CONFIG_H 19 20 /* 21 * High Level Configuration Options 22 */ 23 #define CONFIG_E300 1 /* E300 Family */ 24 25 /* Don't enable PCI2 on vme834x - it doesn't exist physically. */ 26 #undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ 27 28 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 29 30 /* 31 * DDR Setup 32 */ 33 #define CONFIG_DDR_ECC /* only for ECC DDR module */ 34 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ 35 #define CONFIG_SPD_EEPROM 36 #define SPD_EEPROM_ADDRESS 0x54 37 #define CONFIG_SYS_READ_SPD vme8349_read_spd 38 #define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ 39 40 /* 41 * 32-bit data path mode. 42 * 43 * Please note that using this mode for devices with the real density of 64-bit 44 * effectively reduces the amount of available memory due to the effect of 45 * wrapping around while translating address to row/columns, for example in the 46 * 256MB module the upper 128MB get aliased with contents of the lower 47 * 128MB); normally this define should be used for devices with real 32-bit 48 * data path. 49 */ 50 #undef CONFIG_DDR_32BIT 51 52 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ 53 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ 54 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) 55 #define CONFIG_DDR_2T_TIMING 56 #define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ 57 | DDRCDR_ODT \ 58 | DDRCDR_Q_DRN) 59 /* 0x80080001 */ 60 61 /* 62 * FLASH on the Local Bus 63 */ 64 #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ 65 #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ 66 67 68 #define CONFIG_SYS_WINDOW1_BASE 0xf0000000 69 70 71 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 72 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ 73 74 #undef CONFIG_SYS_FLASH_CHECKSUM 75 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ 76 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ 77 78 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 79 80 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 81 #define CONFIG_SYS_RAMBOOT 82 #else 83 #undef CONFIG_SYS_RAMBOOT 84 #endif 85 86 #define CONFIG_SYS_INIT_RAM_LOCK 1 87 #define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ 88 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ 89 90 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ 91 GENERATED_GBL_DATA_SIZE) 92 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 93 94 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ 95 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ 96 97 #undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ 98 99 /* 100 * Serial Port 101 */ 102 #define CONFIG_SYS_NS16550_SERIAL 103 #define CONFIG_SYS_NS16550_REG_SIZE 1 104 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 105 106 #define CONFIG_SYS_BAUDRATE_TABLE \ 107 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 108 109 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 110 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 111 112 /* I2C */ 113 #define CONFIG_SYS_I2C 114 #define CONFIG_SYS_I2C_FSL 115 #define CONFIG_SYS_FSL_I2C_SPEED 400000 116 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 117 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 118 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 119 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 120 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 121 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } 122 /* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ 123 124 #define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ 125 126 /* TSEC */ 127 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 128 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 129 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 130 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) 131 132 /* 133 * General PCI 134 * Addresses are mapped 1-1. 135 */ 136 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 137 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 138 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ 139 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 140 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE 141 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ 142 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 143 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 144 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ 145 146 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 147 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE 148 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ 149 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 150 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE 151 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ 152 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 153 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 154 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ 155 156 #if defined(CONFIG_PCI) 157 158 159 #if !defined(CONFIG_PCI_PNP) 160 #define PCI_ENET0_IOADDR 0xFIXME 161 #define PCI_ENET0_MEMADDR 0xFIXME 162 #define PCI_IDSEL_NUMBER 0xFIXME 163 #endif 164 165 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 166 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 167 168 #endif /* CONFIG_PCI */ 169 170 /* 171 * TSEC configuration 172 */ 173 174 #if defined(CONFIG_TSEC_ENET) 175 176 #define CONFIG_GMII /* MII PHY management */ 177 #define CONFIG_TSEC1 178 #define CONFIG_TSEC1_NAME "TSEC0" 179 #define CONFIG_TSEC2 180 #define CONFIG_TSEC2_NAME "TSEC1" 181 #define CONFIG_PHY_M88E1111 182 #define TSEC1_PHY_ADDR 0x08 183 #define TSEC2_PHY_ADDR 0x10 184 #define TSEC1_PHYIDX 0 185 #define TSEC2_PHYIDX 0 186 #define TSEC1_FLAGS TSEC_GIGABIT 187 #define TSEC2_FLAGS TSEC_GIGABIT 188 189 /* Options are: TSEC[0-1] */ 190 #define CONFIG_ETHPRIME "TSEC0" 191 192 #endif /* CONFIG_TSEC_ENET */ 193 194 /* 195 * Environment 196 */ 197 #ifndef CONFIG_SYS_RAMBOOT 198 /* Address and size of Redundant Environment Sector */ 199 #endif 200 201 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 202 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 203 204 /* 205 * BOOTP options 206 */ 207 #define CONFIG_BOOTP_BOOTFILESIZE 208 209 #define CONFIG_SYS_RTC_BUS_NUM 0x01 210 #define CONFIG_SYS_I2C_RTC_ADDR 0x32 211 212 /* Pass Ethernet MAC to VxWorks */ 213 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 214 215 #undef CONFIG_WATCHDOG /* watchdog disabled */ 216 217 /* 218 * Miscellaneous configurable options 219 */ 220 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 221 222 /* 223 * For booting Linux, the board info and command line data 224 * have to be in the first 256 MB of memory, since this is 225 * the maximum mapped by the Linux kernel during initialization. 226 */ 227 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ 228 229 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ 230 231 /* System IO Config */ 232 #define CONFIG_SYS_SICRH 0 233 #define CONFIG_SYS_SICRL SICRL_LDP_A 234 235 #define CONFIG_SYS_GPIO1_PRELIM 236 #define CONFIG_SYS_GPIO1_DIR 0x00100000 237 #define CONFIG_SYS_GPIO1_DAT 0x00100000 238 239 #define CONFIG_SYS_GPIO2_PRELIM 240 #define CONFIG_SYS_GPIO2_DIR 0x78900000 241 #define CONFIG_SYS_GPIO2_DAT 0x70100000 242 243 #ifdef CONFIG_PCI 244 #define CONFIG_PCI_INDIRECT_BRIDGE 245 #endif 246 247 #if defined(CONFIG_CMD_KGDB) 248 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ 249 #endif 250 251 /* 252 * Environment Configuration 253 */ 254 255 #if defined(CONFIG_TSEC_ENET) 256 #define CONFIG_HAS_ETH0 257 #define CONFIG_HAS_ETH1 258 #endif 259 260 #define CONFIG_HOSTNAME "VME8349" 261 #define CONFIG_ROOTPATH "/tftpboot/rootfs" 262 #define CONFIG_BOOTFILE "uImage" 263 264 #define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ 265 266 #define CONFIG_EXTRA_ENV_SETTINGS \ 267 "netdev=eth0\0" \ 268 "hostname=vme8349\0" \ 269 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 270 "nfsroot=${serverip}:${rootpath}\0" \ 271 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 272 "addip=setenv bootargs ${bootargs} " \ 273 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 274 ":${hostname}:${netdev}:off panic=1\0" \ 275 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 276 "flash_nfs=run nfsargs addip addtty;" \ 277 "bootm ${kernel_addr}\0" \ 278 "flash_self=run ramargs addip addtty;" \ 279 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 280 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 281 "bootm\0" \ 282 "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ 283 "update=protect off fff00000 fff3ffff; " \ 284 "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ 285 "upd=run load update\0" \ 286 "fdtaddr=780000\0" \ 287 "fdtfile=vme8349.dtb\0" \ 288 "" 289 290 #define CONFIG_NFSBOOTCOMMAND \ 291 "setenv bootargs root=/dev/nfs rw " \ 292 "nfsroot=$serverip:$rootpath " \ 293 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ 294 "$netdev:off " \ 295 "console=$consoledev,$baudrate $othbootargs;" \ 296 "tftp $loadaddr $bootfile;" \ 297 "tftp $fdtaddr $fdtfile;" \ 298 "bootm $loadaddr - $fdtaddr" 299 300 #define CONFIG_RAMBOOTCOMMAND \ 301 "setenv bootargs root=/dev/ram rw " \ 302 "console=$consoledev,$baudrate $othbootargs;" \ 303 "tftp $ramdiskaddr $ramdiskfile;" \ 304 "tftp $loadaddr $bootfile;" \ 305 "tftp $fdtaddr $fdtfile;" \ 306 "bootm $loadaddr $ramdiskaddr $fdtaddr" 307 308 #define CONFIG_BOOTCOMMAND "run flash_self" 309 310 #ifndef __ASSEMBLY__ 311 int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, 312 unsigned char *buffer, int len); 313 #endif 314 315 #endif /* __CONFIG_H */ 316