1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Nexell Co., Ltd. 4 * 5 * Author: junghyun, kim <jhkim@nexell.co.kr> 6 */ 7 8 #include <linux/types.h> 9 #include <linux/io.h> 10 11 #include "s5pxx18_soc_disptop.h" 12 #include "s5pxx18_soc_mipi.h" 13 14 static struct nx_mipi_register_set *__g_pregister[NUMBER_OF_MIPI_MODULE]; 15 16 int nx_mipi_smoke_test(u32 module_index) 17 { 18 register struct nx_mipi_register_set *pregister; 19 20 pregister = __g_pregister[module_index]; 21 22 if (pregister->csis_config_ch0 != 0x000000FC) 23 return false; 24 25 if (pregister->dsim_intmsk != 0xB337FFFF) 26 return false; 27 28 writel(0xDEADC0DE, &pregister->csis_dphyctrl); 29 writel(0xFFFFFFFF, &pregister->csis_ctrl2); 30 writel(0xDEADC0DE, &pregister->dsim_msync); 31 32 if (pregister->csis_dphyctrl != 0xDE80001E) 33 return false; 34 35 if ((pregister->csis_ctrl2 & (~1)) != 0xEEE00010) 36 return false; 37 38 if (pregister->dsim_msync != 0xDE80C0DE) 39 return false; 40 41 return true; 42 } 43 44 void nx_mipi_set_base_address(u32 module_index, void *base_address) 45 { 46 __g_pregister[module_index] = 47 (struct nx_mipi_register_set *)base_address; 48 } 49 50 void *nx_mipi_get_base_address(u32 module_index) 51 { 52 return (void *)__g_pregister[module_index]; 53 } 54 55 u32 nx_mipi_get_physical_address(u32 module_index) 56 { 57 const u32 physical_addr[] = PHY_BASEADDR_MIPI_LIST; 58 59 return physical_addr[module_index]; 60 } 61 62 #define __nx_mipi_valid_dsi_intmask__ \ 63 (~((1 << 26) | (1 << 23) | (1 << 22) | (1 << 19))) 64 65 void nx_mipi_set_interrupt_enable(u32 module_index, u32 int_num, int enable) 66 { 67 register struct nx_mipi_register_set *pregister; 68 register u32 regvalue; 69 70 pregister = __g_pregister[module_index]; 71 if (int_num < 32) { 72 regvalue = pregister->csis_intmsk; 73 regvalue &= ~(1ul << int_num); 74 regvalue |= (u32)enable << int_num; 75 writel(regvalue, &pregister->csis_intmsk); 76 } else { 77 regvalue = pregister->dsim_intmsk; 78 regvalue &= ~(1ul << (int_num - 32)); 79 regvalue |= (u32)enable << (int_num - 32); 80 writel(regvalue, &pregister->dsim_intmsk); 81 } 82 } 83 84 int nx_mipi_get_interrupt_enable(u32 module_index, u32 int_num) 85 { 86 if (int_num < 32) 87 return (int)((__g_pregister[module_index]->csis_intmsk >> 88 int_num) & 0x01); 89 else 90 return (int)((__g_pregister[module_index]->dsim_intmsk >> 91 (int_num - 32)) & 0x01); 92 } 93 94 int nx_mipi_get_interrupt_pending(u32 module_index, u32 int_num) 95 { 96 register struct nx_mipi_register_set *pregister; 97 register u32 regvalue; 98 int ret; 99 100 pregister = __g_pregister[module_index]; 101 if (int_num < 32) { 102 regvalue = pregister->csis_intmsk; 103 regvalue &= pregister->csis_intsrc; 104 ret = (int)((regvalue >> int_num) & 0x01); 105 } else { 106 regvalue = pregister->dsim_intmsk; 107 regvalue &= pregister->dsim_intsrc; 108 ret = (int)((regvalue >> (int_num - 32)) & 0x01); 109 } 110 111 return ret; 112 } 113 114 void nx_mipi_clear_interrupt_pending(u32 module_index, u32 int_num) 115 { 116 register struct nx_mipi_register_set *pregister; 117 118 pregister = __g_pregister[module_index]; 119 if (int_num < 32) 120 writel(1ul << int_num, &pregister->csis_intsrc); 121 else 122 writel(1ul << (int_num - 32), &pregister->dsim_intsrc); 123 } 124 125 void nx_mipi_set_interrupt_enable_all(u32 module_index, int enable) 126 { 127 register struct nx_mipi_register_set *pregister; 128 129 pregister = __g_pregister[module_index]; 130 if (enable) 131 writel(__nx_mipi_valid_dsi_intmask__, &pregister->dsim_intmsk); 132 else 133 writel(0, &pregister->dsim_intmsk); 134 } 135 136 int nx_mipi_get_interrupt_enable_all(u32 module_index) 137 { 138 if (__g_pregister[module_index]->csis_intmsk) 139 return true; 140 141 if (__g_pregister[module_index]->dsim_intmsk) 142 return true; 143 144 return false; 145 } 146 147 int nx_mipi_get_interrupt_pending_all(u32 module_index) 148 { 149 register struct nx_mipi_register_set *pregister; 150 register u32 regvalue; 151 152 pregister = __g_pregister[module_index]; 153 regvalue = pregister->csis_intmsk; 154 regvalue &= pregister->csis_intsrc; 155 156 if (regvalue) 157 return true; 158 159 regvalue = pregister->dsim_intmsk; 160 regvalue &= pregister->dsim_intsrc; 161 162 if (regvalue) 163 return true; 164 165 return false; 166 } 167 168 void nx_mipi_clear_interrupt_pending_all(u32 module_index) 169 { 170 register struct nx_mipi_register_set *pregister; 171 172 pregister = __g_pregister[module_index]; 173 writel(__nx_mipi_valid_dsi_intmask__, &pregister->dsim_intsrc); 174 } 175 176 int32_t nx_mipi_get_interrupt_pending_number(u32 module_index) 177 { 178 register struct nx_mipi_register_set *pregister; 179 register u32 regvalue; 180 int i; 181 182 pregister = __g_pregister[module_index]; 183 regvalue = pregister->csis_intmsk; 184 regvalue &= pregister->csis_intsrc; 185 if (regvalue != 0) { 186 for (i = 0; i < 32; i++) { 187 if (regvalue & 1ul) 188 return i; 189 regvalue >>= 1; 190 } 191 } 192 193 regvalue = pregister->dsim_intmsk; 194 regvalue &= pregister->dsim_intsrc; 195 if (regvalue != 0) { 196 for (i = 0; i < 32; i++) { 197 if (regvalue & 1ul) 198 return i + 32; 199 regvalue >>= 1; 200 } 201 } 202 return -1; 203 } 204 205 #define writereg(regname, mask, value) \ 206 regvalue = pregister->(regname); \ 207 regvalue = (regvalue & (~(mask))) | (value); \ 208 writel(regvalue, &pregister->(regname)) 209 210 void nx_mipi_dsi_get_status(u32 module_index, u32 *pulps, u32 *pstop, 211 u32 *pispllstable, u32 *pisinreset, 212 u32 *pisbackward, u32 *pishsclockready) 213 { 214 register struct nx_mipi_register_set *pregister; 215 register u32 regvalue; 216 217 pregister = __g_pregister[module_index]; 218 regvalue = pregister->dsim_status; 219 if (pulps) { 220 *pulps = 0; 221 if (regvalue & (1 << 4)) 222 *pulps |= (1 << 0); 223 if (regvalue & (1 << 5)) 224 *pulps |= (1 << 1); 225 if (regvalue & (1 << 6)) 226 *pulps |= (1 << 2); 227 if (regvalue & (1 << 7)) 228 *pulps |= (1 << 3); 229 if (regvalue & (1 << 9)) 230 *pulps |= (1 << 4); 231 } 232 233 if (pstop) { 234 *pstop = 0; 235 if (regvalue & (1 << 0)) 236 *pstop |= (1 << 0); 237 if (regvalue & (1 << 1)) 238 *pstop |= (1 << 1); 239 if (regvalue & (1 << 2)) 240 *pstop |= (1 << 2); 241 if (regvalue & (1 << 3)) 242 *pstop |= (1 << 3); 243 if (regvalue & (1 << 8)) 244 *pstop |= (1 << 4); 245 } 246 247 if (pispllstable) 248 *pispllstable = (regvalue >> 31) & 1; 249 250 if (pisinreset) 251 *pisinreset = ((regvalue >> 20) & 1) ? 0 : 1; 252 253 if (pisbackward) 254 *pisbackward = (regvalue >> 16) & 1; 255 256 if (pishsclockready) 257 *pishsclockready = (regvalue >> 10) & 1; 258 } 259 260 void nx_mipi_dsi_software_reset(u32 module_index) 261 { 262 register struct nx_mipi_register_set *pregister; 263 264 pregister = __g_pregister[module_index]; 265 266 writel(0x00010001, &pregister->dsim_swrst); 267 268 while (0 != (readl(&pregister->dsim_status) & (1 << 20))) 269 ; 270 271 writel(0x00000000, &pregister->dsim_swrst); 272 } 273 274 void nx_mipi_dsi_set_clock(u32 module_index, int enable_txhsclock, 275 int use_external_clock, int enable_byte_clock, 276 int enable_escclock_clock_lane, 277 int enable_escclock_data_lane0, 278 int enable_escclock_data_lane1, 279 int enable_escclock_data_lane2, 280 int enable_escclock_data_lane3, 281 int enable_escprescaler, u32 escprescalervalue) 282 { 283 register struct nx_mipi_register_set *pregister; 284 register u32 regvalue; 285 286 pregister = __g_pregister[module_index]; 287 regvalue = 0; 288 regvalue |= (enable_txhsclock << 31); 289 regvalue |= (use_external_clock << 27); 290 regvalue |= (enable_byte_clock << 24); 291 regvalue |= (enable_escclock_clock_lane << 19); 292 regvalue |= (enable_escclock_data_lane0 << 20); 293 regvalue |= (enable_escclock_data_lane1 << 21); 294 regvalue |= (enable_escclock_data_lane2 << 22); 295 regvalue |= (enable_escclock_data_lane3 << 23); 296 regvalue |= (enable_escprescaler << 28); 297 regvalue |= escprescalervalue; 298 299 writel(regvalue, &pregister->dsim_clkctrl); 300 } 301 302 void nx_mipi_dsi_set_timeout(u32 module_index, u32 bta_tout, u32 lpdrtout) 303 { 304 register struct nx_mipi_register_set *pregister; 305 register u32 regvalue; 306 307 pregister = __g_pregister[module_index]; 308 regvalue = 0; 309 regvalue |= (bta_tout << 16); 310 regvalue |= (lpdrtout << 0); 311 312 writel(regvalue, &pregister->dsim_timeout); 313 } 314 315 void nx_mipi_dsi_set_config_video_mode(u32 module_index, 316 int enable_auto_flush_main_display_fifo, 317 int enable_auto_vertical_count, 318 int enable_burst, 319 enum nx_mipi_dsi_syncmode sync_mode, 320 int enable_eo_tpacket, 321 int enable_hsync_end_packet, 322 int enable_hfp, int enable_hbp, 323 int enable_hsa, 324 u32 number_of_virtual_channel, 325 enum nx_mipi_dsi_format format, 326 u32 number_of_words_in_hfp, 327 u32 number_of_words_in_hbp, 328 u32 number_of_words_in_hsync, 329 u32 number_of_lines_in_vfp, 330 u32 number_of_lines_in_vbp, 331 u32 number_of_lines_in_vsync, 332 u32 number_of_lines_in_command_allow) 333 { 334 register struct nx_mipi_register_set *pregister; 335 register u32 regvalue; 336 u32 newvalue; 337 338 pregister = __g_pregister[module_index]; 339 newvalue = (1 << 25); 340 newvalue |= ((1 - enable_auto_flush_main_display_fifo) << 29); 341 newvalue |= (enable_auto_vertical_count << 24); 342 newvalue |= (enable_burst << 26); 343 newvalue |= (sync_mode << 27); 344 newvalue |= ((1 - enable_eo_tpacket) << 28); 345 newvalue |= (enable_hsync_end_packet << 23); 346 newvalue |= ((1 - enable_hfp) << 22); 347 newvalue |= ((1 - enable_hbp) << 21); 348 newvalue |= ((1 - enable_hsa) << 20); 349 newvalue |= (number_of_virtual_channel << 18); 350 newvalue |= (format << 12); 351 352 writereg(dsim_config, 0xFFFFFF00, newvalue); 353 354 newvalue = (number_of_lines_in_command_allow << 28); 355 newvalue |= (number_of_lines_in_vfp << 16); 356 newvalue |= (number_of_lines_in_vbp << 0); 357 358 writel(newvalue, &pregister->dsim_mvporch); 359 360 newvalue = (number_of_words_in_hfp << 16); 361 newvalue |= (number_of_words_in_hbp << 0); 362 363 writel(newvalue, &pregister->dsim_mhporch); 364 365 newvalue = (number_of_words_in_hsync << 0); 366 newvalue |= (number_of_lines_in_vsync << 22); 367 368 writel(newvalue, &pregister->dsim_msync); 369 } 370 371 void nx_mipi_dsi_set_config_command_mode(u32 module_index, 372 int 373 enable_auto_flush_main_display_fifo, 374 int enable_eo_tpacket, 375 u32 number_of_virtual_channel, 376 enum nx_mipi_dsi_format format) 377 { 378 register struct nx_mipi_register_set *pregister; 379 register u32 regvalue; 380 u32 newvalue; 381 382 pregister = __g_pregister[module_index]; 383 newvalue = (0 << 25); 384 newvalue |= (enable_auto_flush_main_display_fifo << 29); 385 newvalue |= (enable_eo_tpacket << 28); 386 newvalue |= (number_of_virtual_channel << 18); 387 newvalue |= (format << 12); 388 writereg(dsim_config, 0xFFFFFF00, newvalue); 389 } 390 391 void nx_mipi_dsi_set_escape_mode(u32 module_index, u32 stop_state_count, 392 int force_stop_state, int force_bta, 393 enum nx_mipi_dsi_lpmode cmdin_lp, 394 enum nx_mipi_dsi_lpmode txinlp) 395 { 396 register struct nx_mipi_register_set *pregister; 397 register u32 regvalue; 398 u32 newvalue; 399 400 pregister = __g_pregister[module_index]; 401 newvalue = (stop_state_count << 21); 402 newvalue |= (force_stop_state << 20); 403 newvalue |= (force_bta << 16); 404 newvalue |= (cmdin_lp << 7); 405 newvalue |= (txinlp << 6); 406 writereg(dsim_escmode, 0xFFFFFFC0, newvalue); 407 } 408 409 void nx_mipi_dsi_set_escape_lp(u32 module_index, 410 enum nx_mipi_dsi_lpmode cmdin_lp, 411 enum nx_mipi_dsi_lpmode txinlp) 412 { 413 register struct nx_mipi_register_set *pregister; 414 register u32 regvalue; 415 u32 newvalue = 0; 416 417 pregister = __g_pregister[module_index]; 418 newvalue |= (cmdin_lp << 7); 419 newvalue |= (txinlp << 6); 420 writereg(dsim_escmode, 0xC0, newvalue); 421 } 422 423 void nx_mipi_dsi_remote_reset_trigger(u32 module_index) 424 { 425 register struct nx_mipi_register_set *pregister; 426 register u32 regvalue; 427 u32 newvalue; 428 429 pregister = __g_pregister[module_index]; 430 newvalue = (1 << 4); 431 writereg(dsim_escmode, (1 << 4), newvalue); 432 433 while (readl(&pregister->dsim_escmode) & (1 << 4)) 434 ; 435 } 436 437 void nx_mipi_dsi_set_ulps(u32 module_index, int ulpsclocklane, int ulpsdatalane) 438 { 439 register struct nx_mipi_register_set *pregister; 440 register u32 regvalue; 441 442 pregister = __g_pregister[module_index]; 443 regvalue = pregister->dsim_escmode; 444 445 if (ulpsclocklane) { 446 regvalue &= ~(1 << 0); 447 regvalue |= (1 << 1); 448 } else { 449 regvalue |= (1 << 0); 450 } 451 452 if (ulpsdatalane) { 453 regvalue &= ~(1 << 2); 454 regvalue |= (1 << 3); 455 } else { 456 regvalue |= (1 << 2); 457 } 458 459 writel(regvalue, &pregister->dsim_escmode); 460 461 if (ulpsclocklane) 462 while ((1 << 9) == 463 (readl(&pregister->dsim_status) & (1 << 9))) 464 ; 465 else 466 while (0 != (readl(&pregister->dsim_status) & (1 << 9))) 467 ; 468 469 if (ulpsdatalane) 470 while ((15 << 4) == 471 (readl(&pregister->dsim_status) & (15 << 4))) 472 ; 473 else 474 while (0 != (readl(&pregister->dsim_status) & (15 << 4))) 475 ; 476 477 if (!ulpsclocklane) 478 regvalue &= (3 << 0); 479 480 if (!ulpsdatalane) 481 regvalue |= (3 << 2); 482 483 writel(regvalue, &pregister->dsim_escmode); 484 } 485 486 void nx_mipi_dsi_set_size(u32 module_index, u32 width, u32 height) 487 { 488 register struct nx_mipi_register_set *pregister; 489 register u32 regvalue; 490 u32 newvalue; 491 492 pregister = __g_pregister[module_index]; 493 newvalue = (height << 16); 494 newvalue |= (width << 0); 495 writereg(dsim_mdresol, 0x0FFFFFFF, newvalue); 496 } 497 498 void nx_mipi_dsi_set_enable(u32 module_index, int enable) 499 { 500 register struct nx_mipi_register_set *pregister; 501 register u32 regvalue; 502 503 pregister = __g_pregister[module_index]; 504 writereg(dsim_mdresol, (1 << 31), (enable << 31)); 505 } 506 507 void nx_mipi_dsi_set_phy(u32 module_index, u32 number_of_data_lanes, 508 int enable_clock_lane, int enable_data_lane0, 509 int enable_data_lane1, int enable_data_lane2, 510 int enable_data_lane3, int swap_clock_lane, 511 int swap_data_lane) 512 { 513 register struct nx_mipi_register_set *pregister; 514 register u32 regvalue; 515 u32 newvalue; 516 517 pregister = __g_pregister[module_index]; 518 newvalue = (number_of_data_lanes << 5); 519 newvalue |= (enable_clock_lane << 0); 520 newvalue |= (enable_data_lane0 << 1); 521 newvalue |= (enable_data_lane1 << 2); 522 newvalue |= (enable_data_lane2 << 3); 523 newvalue |= (enable_data_lane3 << 4); 524 writereg(dsim_config, 0xFF, newvalue); 525 newvalue = (swap_clock_lane << 1); 526 newvalue |= (swap_data_lane << 0); 527 writereg(dsim_phyacchr1, 0x3, newvalue); 528 } 529 530 void nx_mipi_dsi_set_pll(u32 module_index, int enable, u32 pllstabletimer, 531 u32 m_pllpms, u32 m_bandctl, u32 m_dphyctl, 532 u32 b_dphyctl) 533 { 534 register struct nx_mipi_register_set *pregister; 535 register u32 regvalue; 536 u32 newvalue; 537 538 pregister = __g_pregister[module_index]; 539 if (!enable) { 540 newvalue = (enable << 23); 541 newvalue |= (m_pllpms << 1); 542 newvalue |= (m_bandctl << 24); 543 writereg(dsim_pllctrl, 0x0FFFFFFF, newvalue); 544 } 545 546 writel(m_dphyctl, &pregister->dsim_phyacchr); 547 writel(pllstabletimer, &pregister->dsim_plltmr); 548 writel((b_dphyctl << 9), &pregister->dsim_phyacchr1); 549 550 if (enable) { 551 newvalue = (enable << 23); 552 newvalue |= (m_pllpms << 1); 553 newvalue |= (m_bandctl << 24); 554 writereg(dsim_pllctrl, 0x0FFFFFFF, newvalue); 555 } 556 } 557 558 void nx_mipi_dsi_write_pkheader(u32 module_index, u32 data) 559 { 560 register struct nx_mipi_register_set *pregister; 561 562 pregister = __g_pregister[module_index]; 563 writel(data, &pregister->dsim_pkthdr); 564 } 565 566 void nx_mipi_dsi_write_payload(u32 module_index, u32 data) 567 { 568 register struct nx_mipi_register_set *pregister; 569 570 pregister = __g_pregister[module_index]; 571 writel(data, &pregister->dsim_payload); 572 } 573 574 u32 nx_mipi_dsi_read_fifo_status(u32 module_index) 575 { 576 register struct nx_mipi_register_set *pregister; 577 578 pregister = __g_pregister[module_index]; 579 return readl(&pregister->dsim_fifoctrl); 580 } 581