1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2017 NXP 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 */ 7 8 #ifndef _ASM_ARCH_IMX8M_CLOCK_H 9 #define _ASM_ARCH_IMX8M_CLOCK_H 10 11 #ifndef __ASSEMBLY__ 12 #include <linux/bitops.h> 13 #endif 14 15 enum pll_clocks { 16 ANATOP_ARM_PLL, 17 ANATOP_GPU_PLL, 18 ANATOP_SYSTEM_PLL1, 19 ANATOP_SYSTEM_PLL2, 20 ANATOP_SYSTEM_PLL3, 21 ANATOP_AUDIO_PLL1, 22 ANATOP_AUDIO_PLL2, 23 ANATOP_VIDEO_PLL1, 24 ANATOP_VIDEO_PLL2, 25 ANATOP_DRAM_PLL, 26 }; 27 28 enum clk_root_index { 29 ARM_A53_CLK_ROOT = 0, 30 ARM_M4_CLK_ROOT = 1, 31 VPU_A53_CLK_ROOT = 2, 32 GPU_CORE_CLK_ROOT = 3, 33 GPU_SHADER_CLK_ROOT = 4, 34 MAIN_AXI_CLK_ROOT = 16, 35 ENET_AXI_CLK_ROOT = 17, 36 NAND_USDHC_BUS_CLK_ROOT = 18, 37 VPU_BUS_CLK_ROOT = 19, 38 DISPLAY_AXI_CLK_ROOT = 20, 39 DISPLAY_APB_CLK_ROOT = 21, 40 DISPLAY_RTRM_CLK_ROOT = 22, 41 USB_BUS_CLK_ROOT = 23, 42 GPU_AXI_CLK_ROOT = 24, 43 GPU_AHB_CLK_ROOT = 25, 44 NOC_CLK_ROOT = 26, 45 NOC_APB_CLK_ROOT = 27, 46 AHB_CLK_ROOT = 32, 47 IPG_CLK_ROOT = 33, 48 AUDIO_AHB_CLK_ROOT = 34, 49 MIPI_DSI_ESC_RX_CLK_ROOT = 36, 50 DRAM_SEL_CFG = 48, 51 CORE_SEL_CFG = 49, 52 DRAM_ALT_CLK_ROOT = 64, 53 DRAM_APB_CLK_ROOT = 65, 54 VPU_G1_CLK_ROOT = 66, 55 VPU_G2_CLK_ROOT = 67, 56 DISPLAY_DTRC_CLK_ROOT = 68, 57 DISPLAY_DC8000_CLK_ROOT = 69, 58 PCIE1_CTRL_CLK_ROOT = 70, 59 PCIE1_PHY_CLK_ROOT = 71, 60 PCIE1_AUX_CLK_ROOT = 72, 61 DC_PIXEL_CLK_ROOT = 73, 62 LCDIF_PIXEL_CLK_ROOT = 74, 63 SAI1_CLK_ROOT = 75, 64 SAI2_CLK_ROOT = 76, 65 SAI3_CLK_ROOT = 77, 66 SAI4_CLK_ROOT = 78, 67 SAI5_CLK_ROOT = 79, 68 SAI6_CLK_ROOT = 80, 69 SPDIF1_CLK_ROOT = 81, 70 SPDIF2_CLK_ROOT = 82, 71 ENET_REF_CLK_ROOT = 83, 72 ENET_TIMER_CLK_ROOT = 84, 73 ENET_PHY_REF_CLK_ROOT = 85, 74 NAND_CLK_ROOT = 86, 75 QSPI_CLK_ROOT = 87, 76 USDHC1_CLK_ROOT = 88, 77 USDHC2_CLK_ROOT = 89, 78 I2C1_CLK_ROOT = 90, 79 I2C2_CLK_ROOT = 91, 80 I2C3_CLK_ROOT = 92, 81 I2C4_CLK_ROOT = 93, 82 UART1_CLK_ROOT = 94, 83 UART2_CLK_ROOT = 95, 84 UART3_CLK_ROOT = 96, 85 UART4_CLK_ROOT = 97, 86 USB_CORE_REF_CLK_ROOT = 98, 87 USB_PHY_REF_CLK_ROOT = 99, 88 GIC_CLK_ROOT = 100, 89 ECSPI1_CLK_ROOT = 101, 90 ECSPI2_CLK_ROOT = 102, 91 PWM1_CLK_ROOT = 103, 92 PWM2_CLK_ROOT = 104, 93 PWM3_CLK_ROOT = 105, 94 PWM4_CLK_ROOT = 106, 95 GPT1_CLK_ROOT = 107, 96 GPT2_CLK_ROOT = 108, 97 GPT3_CLK_ROOT = 109, 98 GPT4_CLK_ROOT = 110, 99 GPT5_CLK_ROOT = 111, 100 GPT6_CLK_ROOT = 112, 101 TRACE_CLK_ROOT = 113, 102 WDOG_CLK_ROOT = 114, 103 WRCLK_CLK_ROOT = 115, 104 IPP_DO_CLKO1 = 116, 105 IPP_DO_CLKO2 = 117, 106 MIPI_DSI_CORE_CLK_ROOT = 118, 107 MIPI_DSI_PHY_REF_CLK_ROOT = 119, 108 MIPI_DSI_DBI_CLK_ROOT = 120, 109 OLD_MIPI_DSI_ESC_CLK_ROOT = 121, 110 MIPI_CSI1_CORE_CLK_ROOT = 122, 111 MIPI_CSI1_PHY_REF_CLK_ROOT = 123, 112 MIPI_CSI1_ESC_CLK_ROOT = 124, 113 MIPI_CSI2_CORE_CLK_ROOT = 125, 114 MIPI_CSI2_PHY_REF_CLK_ROOT = 126, 115 MIPI_CSI2_ESC_CLK_ROOT = 127, 116 PCIE2_CTRL_CLK_ROOT = 128, 117 PCIE2_PHY_CLK_ROOT = 129, 118 PCIE2_AUX_CLK_ROOT = 130, 119 ECSPI3_CLK_ROOT = 131, 120 OLD_MIPI_DSI_ESC_RX_ROOT = 132, 121 DISPLAY_HDMI_CLK_ROOT = 133, 122 CLK_ROOT_MAX, 123 }; 124 125 enum clk_root_src { 126 OSC_25M_CLK, 127 ARM_PLL_CLK, 128 DRAM_PLL1_CLK, 129 VIDEO_PLL2_CLK, 130 VPU_PLL_CLK, 131 GPU_PLL_CLK, 132 SYSTEM_PLL1_800M_CLK, 133 SYSTEM_PLL1_400M_CLK, 134 SYSTEM_PLL1_266M_CLK, 135 SYSTEM_PLL1_200M_CLK, 136 SYSTEM_PLL1_160M_CLK, 137 SYSTEM_PLL1_133M_CLK, 138 SYSTEM_PLL1_100M_CLK, 139 SYSTEM_PLL1_80M_CLK, 140 SYSTEM_PLL1_40M_CLK, 141 SYSTEM_PLL2_1000M_CLK, 142 SYSTEM_PLL2_500M_CLK, 143 SYSTEM_PLL2_333M_CLK, 144 SYSTEM_PLL2_250M_CLK, 145 SYSTEM_PLL2_200M_CLK, 146 SYSTEM_PLL2_166M_CLK, 147 SYSTEM_PLL2_125M_CLK, 148 SYSTEM_PLL2_100M_CLK, 149 SYSTEM_PLL2_50M_CLK, 150 SYSTEM_PLL3_CLK, 151 AUDIO_PLL1_CLK, 152 AUDIO_PLL2_CLK, 153 VIDEO_PLL_CLK, 154 OSC_32K_CLK, 155 EXT_CLK_1, 156 EXT_CLK_2, 157 EXT_CLK_3, 158 EXT_CLK_4, 159 OSC_27M_CLK, 160 ARM_A53_ALT_CLK, 161 }; 162 163 /* CCGR index */ 164 enum clk_ccgr_index { 165 CCGR_DVFS = 0, 166 CCGR_ANAMIX = 1, 167 CCGR_CPU = 2, 168 CCGR_CSU = 4, 169 CCGR_DRAM1 = 5, 170 CCGR_DRAM2_OBSOLETE = 6, 171 CCGR_ECSPI1 = 7, 172 CCGR_ECSPI2 = 8, 173 CCGR_ECSPI3 = 9, 174 CCGR_ENET1 = 10, 175 CCGR_GPIO1 = 11, 176 CCGR_GPIO2 = 12, 177 CCGR_GPIO3 = 13, 178 CCGR_GPIO4 = 14, 179 CCGR_GPIO5 = 15, 180 CCGR_GPT1 = 16, 181 CCGR_GPT2 = 17, 182 CCGR_GPT3 = 18, 183 CCGR_GPT4 = 19, 184 CCGR_GPT5 = 20, 185 CCGR_GPT6 = 21, 186 CCGR_HS = 22, 187 CCGR_I2C1 = 23, 188 CCGR_I2C2 = 24, 189 CCGR_I2C3 = 25, 190 CCGR_I2C4 = 26, 191 CCGR_IOMUX = 27, 192 CCGR_IOMUX1 = 28, 193 CCGR_IOMUX2 = 29, 194 CCGR_IOMUX3 = 30, 195 CCGR_IOMUX4 = 31, 196 CCGR_M4 = 32, 197 CCGR_MU = 33, 198 CCGR_OCOTP = 34, 199 CCGR_OCRAM = 35, 200 CCGR_OCRAM_S = 36, 201 CCGR_PCIE = 37, 202 CCGR_PERFMON1 = 38, 203 CCGR_PERFMON2 = 39, 204 CCGR_PWM1 = 40, 205 CCGR_PWM2 = 41, 206 CCGR_PWM3 = 42, 207 CCGR_PWM4 = 43, 208 CCGR_QOS = 44, 209 CCGR_DISMIX = 45, 210 CCGR_MEGAMIX = 46, 211 CCGR_QSPI = 47, 212 CCGR_RAWNAND = 48, 213 CCGR_RDC = 49, 214 CCGR_ROM = 50, 215 CCGR_SAI1 = 51, 216 CCGR_SAI2 = 52, 217 CCGR_SAI3 = 53, 218 CCGR_SAI4 = 54, 219 CCGR_SAI5 = 55, 220 CCGR_SAI6 = 56, 221 CCGR_SCTR = 57, 222 CCGR_SDMA1 = 58, 223 CCGR_SDMA2 = 59, 224 CCGR_SEC_DEBUG = 60, 225 CCGR_SEMA1 = 61, 226 CCGR_SEMA2 = 62, 227 CCGR_SIM_DISPLAY = 63, 228 CCGR_SIM_ENET = 64, 229 CCGR_SIM_M = 65, 230 CCGR_SIM_MAIN = 66, 231 CCGR_SIM_S = 67, 232 CCGR_SIM_WAKEUP = 68, 233 CCGR_SIM_USB = 69, 234 CCGR_SIM_VPU = 70, 235 CCGR_SNVS = 71, 236 CCGR_TRACE = 72, 237 CCGR_UART1 = 73, 238 CCGR_UART2 = 74, 239 CCGR_UART3 = 75, 240 CCGR_UART4 = 76, 241 CCGR_USB_CTRL1 = 77, 242 CCGR_USB_CTRL2 = 78, 243 CCGR_USB_PHY1 = 79, 244 CCGR_USB_PHY2 = 80, 245 CCGR_USDHC1 = 81, 246 CCGR_USDHC2 = 82, 247 CCGR_WDOG1 = 83, 248 CCGR_WDOG2 = 84, 249 CCGR_WDOG3 = 85, 250 CCGR_VA53 = 86, 251 CCGR_GPU = 87, 252 CCGR_HEVC = 88, 253 CCGR_AVC = 89, 254 CCGR_VP9 = 90, 255 CCGR_HEVC_INTER = 91, 256 CCGR_GIC = 92, 257 CCGR_DISPLAY = 93, 258 CCGR_HDMI = 94, 259 CCGR_HDMI_PHY = 95, 260 CCGR_XTAL = 96, 261 CCGR_PLL = 97, 262 CCGR_TSENSOR = 98, 263 CCGR_VPU_DEC = 99, 264 CCGR_PCIE2 = 100, 265 CCGR_MIPI_CSI1 = 101, 266 CCGR_MIPI_CSI2 = 102, 267 CCGR_MAX, 268 }; 269 270 /* src index */ 271 enum clk_src_index { 272 CLK_SRC_CKIL_SYNC_REQ = 0, 273 CLK_SRC_ARM_PLL_EN = 1, 274 CLK_SRC_GPU_PLL_EN = 2, 275 CLK_SRC_VPU_PLL_EN = 3, 276 CLK_SRC_DRAM_PLL_EN = 4, 277 CLK_SRC_SYSTEM_PLL1_EN = 5, 278 CLK_SRC_SYSTEM_PLL2_EN = 6, 279 CLK_SRC_SYSTEM_PLL3_EN = 7, 280 CLK_SRC_AUDIO_PLL1_EN = 8, 281 CLK_SRC_AUDIO_PLL2_EN = 9, 282 CLK_SRC_VIDEO_PLL1_EN = 10, 283 CLK_SRC_VIDEO_PLL2_EN = 11, 284 CLK_SRC_ARM_PLL = 12, 285 CLK_SRC_GPU_PLL = 13, 286 CLK_SRC_VPU_PLL = 14, 287 CLK_SRC_DRAM_PLL = 15, 288 CLK_SRC_SYSTEM_PLL1_800M = 16, 289 CLK_SRC_SYSTEM_PLL1_400M = 17, 290 CLK_SRC_SYSTEM_PLL1_266M = 18, 291 CLK_SRC_SYSTEM_PLL1_200M = 19, 292 CLK_SRC_SYSTEM_PLL1_160M = 20, 293 CLK_SRC_SYSTEM_PLL1_133M = 21, 294 CLK_SRC_SYSTEM_PLL1_100M = 22, 295 CLK_SRC_SYSTEM_PLL1_80M = 23, 296 CLK_SRC_SYSTEM_PLL1_40M = 24, 297 CLK_SRC_SYSTEM_PLL2_1000M = 25, 298 CLK_SRC_SYSTEM_PLL2_500M = 26, 299 CLK_SRC_SYSTEM_PLL2_333M = 27, 300 CLK_SRC_SYSTEM_PLL2_250M = 28, 301 CLK_SRC_SYSTEM_PLL2_200M = 29, 302 CLK_SRC_SYSTEM_PLL2_166M = 30, 303 CLK_SRC_SYSTEM_PLL2_125M = 31, 304 CLK_SRC_SYSTEM_PLL2_100M = 32, 305 CLK_SRC_SYSTEM_PLL2_50M = 33, 306 CLK_SRC_SYSTEM_PLL3 = 34, 307 CLK_SRC_AUDIO_PLL1 = 35, 308 CLK_SRC_AUDIO_PLL2 = 36, 309 CLK_SRC_VIDEO_PLL1 = 37, 310 CLK_SRC_VIDEO_PLL2 = 38, 311 CLK_SRC_OSC_25M = 39, 312 CLK_SRC_OSC_27M = 40, 313 }; 314 315 /* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/ 316 #define FRAC_PLL_LOCK_MASK BIT(31) 317 #define FRAC_PLL_CLKE_MASK BIT(21) 318 #define FRAC_PLL_PD_MASK BIT(19) 319 #define FRAC_PLL_REFCLK_SEL_MASK (0x3 << 16) 320 #define FRAC_PLL_LOCK_SEL_MASK BIT(15) 321 #define FRAC_PLL_BYPASS_MASK BIT(14) 322 #define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13) 323 #define FRAC_PLL_NEWDIV_VAL_MASK BIT(12) 324 #define FRAC_PLL_NEWDIV_ACK_MASK BIT(11) 325 #define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5)) 326 #define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5) 327 #define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5 328 #define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f 329 #define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f) 330 331 #define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16) 332 #define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16) 333 #define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16) 334 #define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16) 335 336 #define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7) 337 #define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7 338 #define FRAC_PLL_INT_DIV_CTL_MASK 0x7f 339 #define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f) 340 341 /* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */ 342 #define SSCG_PLL_LOCK_MASK BIT(31) 343 #define SSCG_PLL_CLKE_MASK BIT(25) 344 #define SSCG_PLL_DIV2_CLKE_MASK BIT(23) 345 #define SSCG_PLL_DIV3_CLKE_MASK BIT(21) 346 #define SSCG_PLL_DIV4_CLKE_MASK BIT(19) 347 #define SSCG_PLL_DIV5_CLKE_MASK BIT(17) 348 #define SSCG_PLL_DIV6_CLKE_MASK BIT(15) 349 #define SSCG_PLL_DIV8_CLKE_MASK BIT(13) 350 #define SSCG_PLL_DIV10_CLKE_MASK BIT(11) 351 #define SSCG_PLL_DIV20_CLKE_MASK BIT(9) 352 #define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9) 353 #define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9) 354 #define SSCG_PLL_PLL3_CLKE_MASK BIT(9) 355 #define SSCG_PLL_PD_MASK BIT(7) 356 #define SSCG_PLL_BYPASS1_MASK BIT(5) 357 #define SSCG_PLL_BYPASS2_MASK BIT(4) 358 #define SSCG_PLL_LOCK_SEL_MASK BIT(3) 359 #define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2) 360 #define SSCG_PLL_REFCLK_SEL_MASK 0x3 361 #define SSCG_PLL_REFCLK_SEL_OSC_25M (0) 362 #define SSCG_PLL_REFCLK_SEL_OSC_27M (1) 363 #define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2) 364 #define SSCG_PLL_REFCLK_SEL_CLK_PN (3) 365 366 #define SSCG_PLL_SSDS_MASK BIT(8) 367 #define SSCG_PLL_SSMD_MASK (0x7 << 5) 368 #define SSCG_PLL_SSMF_MASK (0xf << 1) 369 #define SSCG_PLL_SSE_MASK 0x1 370 371 #define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25) 372 #define SSCG_PLL_REF_DIVR1_SHIFT 25 373 #define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK) 374 #define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19) 375 #define SSCG_PLL_REF_DIVR2_SHIFT 19 376 #define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK) 377 #define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13) 378 #define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13 379 #define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \ 380 SSCG_PLL_FEEDBACK_DIV_F1_MASK) 381 #define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7) 382 #define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7 383 #define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \ 384 SSCG_PLL_FEEDBACK_DIV_F2_MASK) 385 #define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1) 386 #define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1 387 #define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \ 388 SSCG_PLL_OUTPUT_DIV_VAL_MASK) 389 #define SSCG_PLL_FILTER_RANGE_MASK 0x1 390 391 #define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16) 392 #define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8) 393 #define HW_DIGPROG_MINOR_MASK 0xff 394 395 #define HW_OSC_27M_CLKE_MASK BIT(4) 396 #define HW_OSC_25M_CLKE_MASK BIT(2) 397 #define HW_OSC_32K_SEL_MASK 0x1 398 #define HW_OSC_32K_SEL_RTC 0x1 399 #define HW_OSC_32K_SEL_25M_DIV800 0x0 400 401 #define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20) 402 #define HW_FRAC_ARM_PLL_DIV_SHIFT 20 403 #define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16) 404 #define HW_FRAC_VPU_PLL_DIV_SHIFT 16 405 #define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12) 406 #define HW_FRAC_GPU_PLL_DIV_SHIFT 12 407 #define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10) 408 #define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10 409 #define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4) 410 #define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4 411 #define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7 412 #define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0 413 414 #define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16) 415 #define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16 416 #define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14) 417 #define HW_SSCG_DRAM_PLL_DIV_SHIFT 14 418 #define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8) 419 #define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8 420 #define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4) 421 #define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4 422 #define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7 423 #define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0 424 425 enum frac_pll_out_val { 426 FRAC_PLL_OUT_1000M, 427 FRAC_PLL_OUT_800M, 428 }; 429 430 void init_nand_clk(void); 431 #endif 432