1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
4 */
5
6 #include <clk.h>
7 #include <common.h>
8 #include <dm.h>
9 #include <reset.h>
10 #include <wdt.h>
11 #include <asm/io.h>
12 #include <linux/bitops.h>
13
14 #define DW_WDT_CR 0x00
15 #define DW_WDT_TORR 0x04
16 #define DW_WDT_CRR 0x0C
17
18 #define DW_WDT_CR_EN_OFFSET 0x00
19 #define DW_WDT_CR_RMOD_OFFSET 0x01
20 #define DW_WDT_CRR_RESTART_VAL 0x76
21
22 struct designware_wdt_priv {
23 void __iomem *base;
24 unsigned int clk_khz;
25 };
26
27 /*
28 * Set the watchdog time interval.
29 * Counter is 32 bit.
30 */
designware_wdt_settimeout(void __iomem * base,unsigned int clk_khz,unsigned int timeout)31 static int designware_wdt_settimeout(void __iomem *base, unsigned int clk_khz,
32 unsigned int timeout)
33 {
34 signed int i;
35
36 /* calculate the timeout range value */
37 i = fls(timeout * clk_khz - 1) - 16;
38 i = clamp(i, 0, 15);
39
40 writel(i | (i << 4), base + DW_WDT_TORR);
41
42 return 0;
43 }
44
designware_wdt_enable(void __iomem * base)45 static void designware_wdt_enable(void __iomem *base)
46 {
47 writel(BIT(DW_WDT_CR_EN_OFFSET), base + DW_WDT_CR);
48 }
49
designware_wdt_is_enabled(void __iomem * base)50 static unsigned int designware_wdt_is_enabled(void __iomem *base)
51 {
52 return readl(base + DW_WDT_CR) & BIT(0);
53 }
54
designware_wdt_reset_common(void __iomem * base)55 static void designware_wdt_reset_common(void __iomem *base)
56 {
57 if (designware_wdt_is_enabled(base))
58 /* restart the watchdog counter */
59 writel(DW_WDT_CRR_RESTART_VAL, base + DW_WDT_CRR);
60 }
61
62 #if !CONFIG_IS_ENABLED(WDT)
hw_watchdog_reset(void)63 void hw_watchdog_reset(void)
64 {
65 designware_wdt_reset_common((void __iomem *)CONFIG_DW_WDT_BASE);
66 }
67
hw_watchdog_init(void)68 void hw_watchdog_init(void)
69 {
70 /* reset to disable the watchdog */
71 hw_watchdog_reset();
72 /* set timer in miliseconds */
73 designware_wdt_settimeout((void __iomem *)CONFIG_DW_WDT_BASE,
74 CONFIG_DW_WDT_CLOCK_KHZ,
75 CONFIG_WATCHDOG_TIMEOUT_MSECS);
76 /* enable the watchdog */
77 designware_wdt_enable((void __iomem *)CONFIG_DW_WDT_BASE);
78 /* reset the watchdog */
79 hw_watchdog_reset();
80 }
81 #else
designware_wdt_reset(struct udevice * dev)82 static int designware_wdt_reset(struct udevice *dev)
83 {
84 struct designware_wdt_priv *priv = dev_get_priv(dev);
85
86 designware_wdt_reset_common(priv->base);
87
88 return 0;
89 }
90
designware_wdt_stop(struct udevice * dev)91 static int designware_wdt_stop(struct udevice *dev)
92 {
93 struct designware_wdt_priv *priv = dev_get_priv(dev);
94
95 designware_wdt_reset(dev);
96 writel(0, priv->base + DW_WDT_CR);
97
98 return 0;
99 }
100
designware_wdt_start(struct udevice * dev,u64 timeout,ulong flags)101 static int designware_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
102 {
103 struct designware_wdt_priv *priv = dev_get_priv(dev);
104
105 designware_wdt_stop(dev);
106
107 /* set timer in miliseconds */
108 designware_wdt_settimeout(priv->base, priv->clk_khz, timeout);
109
110 designware_wdt_enable(priv->base);
111
112 /* reset the watchdog */
113 return designware_wdt_reset(dev);
114 }
115
designware_wdt_probe(struct udevice * dev)116 static int designware_wdt_probe(struct udevice *dev)
117 {
118 struct designware_wdt_priv *priv = dev_get_priv(dev);
119 __maybe_unused int ret;
120
121 priv->base = dev_remap_addr(dev);
122 if (!priv->base)
123 return -EINVAL;
124
125 #if CONFIG_IS_ENABLED(CLK)
126 struct clk clk;
127
128 ret = clk_get_by_index(dev, 0, &clk);
129 if (ret)
130 return ret;
131
132 ret = clk_enable(&clk);
133 if (ret)
134 goto err;
135
136 priv->clk_khz = clk_get_rate(&clk) / 1000;
137 if (!priv->clk_khz) {
138 ret = -EINVAL;
139 goto err;
140 }
141 #else
142 priv->clk_khz = CONFIG_DW_WDT_CLOCK_KHZ;
143 #endif
144
145 if (CONFIG_IS_ENABLED(DM_RESET)) {
146 struct reset_ctl_bulk resets;
147
148 ret = reset_get_bulk(dev, &resets);
149 if (ret)
150 goto err;
151
152 ret = reset_deassert_bulk(&resets);
153 if (ret)
154 goto err;
155 }
156
157 /* reset to disable the watchdog */
158 return designware_wdt_stop(dev);
159
160 err:
161 #if CONFIG_IS_ENABLED(CLK)
162 clk_free(&clk);
163 #endif
164 return ret;
165 }
166
167 static const struct wdt_ops designware_wdt_ops = {
168 .start = designware_wdt_start,
169 .reset = designware_wdt_reset,
170 .stop = designware_wdt_stop,
171 };
172
173 static const struct udevice_id designware_wdt_ids[] = {
174 { .compatible = "snps,dw-wdt"},
175 {}
176 };
177
178 U_BOOT_DRIVER(designware_wdt) = {
179 .name = "designware_wdt",
180 .id = UCLASS_WDT,
181 .of_match = designware_wdt_ids,
182 .priv_auto = sizeof(struct designware_wdt_priv),
183 .probe = designware_wdt_probe,
184 .ops = &designware_wdt_ops,
185 .flags = DM_FLAG_PRE_RELOC,
186 };
187 #endif
188