1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Marvell Armada XP development board
4 * (DB-MV784MP-GP)
5 *
6 * Copyright (C) 2013-2014 Marvell
7 *
8 * Lior Amsalem <alior@marvell.com>
9 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 *
12 * Note: this Device Tree assumes that the bootloader has remapped the
13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
15 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
16 * boards were delivered with an older version of the bootloader that
17 * left internal registers mapped at 0xd0000000. If you are in this
18 * situation, you should either update your bootloader (preferred
19 * solution) or the below Device Tree should be adjusted.
20 */
21
22/dts-v1/;
23#include <dt-bindings/gpio/gpio.h>
24#include "armada-xp-mv78460.dtsi"
25
26/ {
27	model = "Marvell Armada XP Development Board DB-MV784MP-GP";
28	compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
29
30	chosen {
31		stdout-path = "serial0:115200n8";
32	};
33
34	aliases {
35		spi0 = &spi0;
36	};
37
38	memory@0 {
39		device_type = "memory";
40		/*
41                 * 8 GB of plug-in RAM modules by default.The amount
42                 * of memory available can be changed by the
43                 * bootloader according the size of the module
44                 * actually plugged. However, memory between
45                 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
46                 * the address range used for I/O (internal registers,
47                 * MBus windows).
48		 */
49		reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
50		      <0x00000001 0x00000000 0x00000001 0x00000000>;
51	};
52
53	cpus {
54		pm_pic {
55			ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
56				     <&gpio0 17 GPIO_ACTIVE_LOW>,
57				     <&gpio0 18 GPIO_ACTIVE_LOW>;
58		};
59	};
60
61	soc {
62		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
63			  MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
64			  MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
65			  MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
66			  MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000
67			  MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>;
68
69		devbus-bootcs {
70			status = "okay";
71
72			/* Device Bus parameters are required */
73
74			/* Read parameters */
75			devbus,bus-width    = <16>;
76			devbus,turn-off-ps  = <60000>;
77			devbus,badr-skew-ps = <0>;
78			devbus,acc-first-ps = <124000>;
79			devbus,acc-next-ps  = <248000>;
80			devbus,rd-setup-ps  = <0>;
81			devbus,rd-hold-ps   = <0>;
82
83			/* Write parameters */
84			devbus,sync-enable = <0>;
85			devbus,wr-high-ps  = <60000>;
86			devbus,wr-low-ps   = <60000>;
87			devbus,ale-wr-ps   = <60000>;
88
89			/* NOR 16 MiB */
90			nor@0 {
91				compatible = "cfi-flash";
92				reg = <0 0x1000000>;
93				bank-width = <2>;
94			};
95		};
96
97		internal-regs {
98			serial@12000 {
99				status = "okay";
100			};
101			serial@12100 {
102				status = "okay";
103			};
104			serial@12200 {
105				status = "okay";
106			};
107			serial@12300 {
108				status = "okay";
109			};
110			pinctrl {
111				pinctrl-0 = <&pic_pins>;
112				pinctrl-names = "default";
113				pic_pins: pic-pins-0 {
114					marvell,pins = "mpp16", "mpp17",
115						       "mpp18";
116					marvell,function = "gpio";
117				};
118			};
119			sata@a0000 {
120				nr-ports = <2>;
121				status = "okay";
122			};
123
124			ethernet@70000 {
125				status = "okay";
126				phy = <&phy0>;
127				phy-mode = "qsgmii";
128				buffer-manager = <&bm>;
129				bm,pool-long = <0>;
130			};
131			ethernet@74000 {
132				status = "okay";
133				phy = <&phy1>;
134				phy-mode = "qsgmii";
135				buffer-manager = <&bm>;
136				bm,pool-long = <1>;
137			};
138			ethernet@30000 {
139				status = "okay";
140				phy = <&phy2>;
141				phy-mode = "qsgmii";
142				buffer-manager = <&bm>;
143				bm,pool-long = <2>;
144			};
145			ethernet@34000 {
146				status = "okay";
147				phy = <&phy3>;
148				phy-mode = "qsgmii";
149				buffer-manager = <&bm>;
150				bm,pool-long = <3>;
151			};
152
153			/* Front-side USB slot */
154			usb@50000 {
155				status = "okay";
156			};
157
158			/* Back-side USB slot */
159			usb@51000 {
160				status = "okay";
161			};
162
163			bm@c0000 {
164				status = "okay";
165			};
166
167			nand@d0000 {
168				status = "okay";
169				label = "pxa3xx_nand-0";
170				num-cs = <1>;
171				marvell,nand-keep-config;
172				nand-on-flash-bbt;
173			};
174		};
175
176		bm-bppi {
177			status = "okay";
178		};
179	};
180};
181
182&pciec {
183	status = "okay";
184
185	/*
186	 * The 3 slots are physically present as
187	 * standard PCIe slots on the board.
188	 */
189	pcie@1,0 {
190		/* Port 0, Lane 0 */
191		status = "okay";
192	};
193	pcie@9,0 {
194		/* Port 2, Lane 0 */
195		status = "okay";
196	};
197	pcie@a,0 {
198		/* Port 3, Lane 0 */
199		status = "okay";
200	};
201};
202
203&mdio {
204	phy0: ethernet-phy@0 {
205		reg = <16>;
206	};
207
208	phy1: ethernet-phy@1 {
209		reg = <17>;
210	};
211
212	phy2: ethernet-phy@2 {
213		reg = <18>;
214	};
215
216	phy3: ethernet-phy@3 {
217		reg = <19>;
218	};
219};
220
221&spi0 {
222	status = "okay";
223
224	spi-flash@0 {
225		#address-cells = <1>;
226		#size-cells = <1>;
227		compatible = "n25q128a13", "jedec,spi-nor";
228		reg = <0>; /* Chip select 0 */
229		spi-max-frequency = <108000000>;
230	};
231};
232