1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * ColdFire Internal Memory Map and Defines 4 * 5 * Copyright 2004-2012 Freescale Semiconductor, Inc. 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 7 */ 8 9 #ifndef __IMMAP_H 10 #define __IMMAP_H 11 12 #if defined(CONFIG_MCF520x) 13 #include <asm/immap_520x.h> 14 #include <asm/m520x.h> 15 16 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 17 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 18 19 /* Timer */ 20 #ifdef CONFIG_MCFTMR 21 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 22 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 23 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 24 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 25 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 26 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 27 #define CONFIG_SYS_TMRINTR_PRI (6) 28 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 29 #endif 30 31 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 32 #define CONFIG_SYS_NUM_IRQS (128) 33 #endif /* CONFIG_M520x */ 34 35 #ifdef CONFIG_M52277 36 #include <asm/immap_5227x.h> 37 #include <asm/m5227x.h> 38 39 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 40 41 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 42 43 #ifdef CONFIG_LCD 44 #define CONFIG_SYS_LCD_BASE (MMAP_LCD) 45 #endif 46 47 /* Timer */ 48 #ifdef CONFIG_MCFTMR 49 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 50 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 51 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 52 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 53 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 54 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 55 #define CONFIG_SYS_TMRINTR_PRI (6) 56 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 57 #endif 58 59 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 60 #define CONFIG_SYS_NUM_IRQS (128) 61 #endif /* CONFIG_M52277 */ 62 63 #ifdef CONFIG_M5235 64 #include <asm/immap_5235.h> 65 #include <asm/m5235.h> 66 67 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 68 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 69 70 /* Timer */ 71 #ifdef CONFIG_MCFTMR 72 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 73 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 74 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 75 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 76 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 77 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 78 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 79 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 80 #endif 81 82 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 83 #define CONFIG_SYS_NUM_IRQS (128) 84 #endif /* CONFIG_M5235 */ 85 86 #ifdef CONFIG_M5249 87 #include <asm/immap_5249.h> 88 #include <asm/m5249.h> 89 90 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 91 92 #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 93 #define CONFIG_SYS_NUM_IRQS (64) 94 95 /* Timer */ 96 #ifdef CONFIG_MCFTMR 97 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 98 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 99 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 100 #define CONFIG_SYS_TMRINTR_NO (31) 101 #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 102 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 103 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 104 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 105 #endif 106 #endif /* CONFIG_M5249 */ 107 108 #ifdef CONFIG_M5253 109 #include <asm/immap_5253.h> 110 #include <asm/m5249.h> 111 #include <asm/m5253.h> 112 113 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 114 115 #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 116 #define CONFIG_SYS_NUM_IRQS (64) 117 118 /* Timer */ 119 #ifdef CONFIG_MCFTMR 120 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 121 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 122 #define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) 123 #define CONFIG_SYS_TMRINTR_NO (27) 124 #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 125 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 126 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL3 | MCFSIM_ICR_PRI3) 127 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 2000000) - 1) << 8) 128 #endif 129 #endif /* CONFIG_M5253 */ 130 131 #ifdef CONFIG_M5271 132 #include <asm/immap_5271.h> 133 #include <asm/m5271.h> 134 135 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 136 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 137 138 /* Timer */ 139 #ifdef CONFIG_MCFTMR 140 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 141 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 142 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 143 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 144 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 145 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 146 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Interrupt level 3, priority 6 */ 147 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 148 #endif 149 150 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 151 #define CONFIG_SYS_NUM_IRQS (128) 152 #endif /* CONFIG_M5271 */ 153 154 #ifdef CONFIG_M5272 155 #include <asm/immap_5272.h> 156 #include <asm/m5272.h> 157 158 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 159 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 160 161 #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 162 #define CONFIG_SYS_NUM_IRQS (64) 163 164 /* Timer */ 165 #ifdef CONFIG_MCFTMR 166 #define CONFIG_SYS_UDELAY_BASE (MMAP_TMR0) 167 #define CONFIG_SYS_TMR_BASE (MMAP_TMR3) 168 #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *)(CONFIG_SYS_INTR_BASE))->int_isr) 169 #define CONFIG_SYS_TMRINTR_NO (INT_TMR3) 170 #define CONFIG_SYS_TMRINTR_MASK (INT_ISR_INT24) 171 #define CONFIG_SYS_TMRINTR_PEND (0) 172 #define CONFIG_SYS_TMRINTR_PRI (INT_ICR1_TMR3PI | INT_ICR1_TMR3IPL(5)) 173 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 174 #endif 175 #endif /* CONFIG_M5272 */ 176 177 #ifdef CONFIG_M5275 178 #include <asm/immap_5275.h> 179 #include <asm/m5275.h> 180 181 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 182 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 183 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 184 185 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 186 #define CONFIG_SYS_NUM_IRQS (192) 187 188 /* Timer */ 189 #ifdef CONFIG_MCFTMR 190 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 191 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 192 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 193 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 194 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRL_INT22) 195 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 196 #define CONFIG_SYS_TMRINTR_PRI (0x1E) 197 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 198 #endif 199 #endif /* CONFIG_M5275 */ 200 201 #ifdef CONFIG_M5282 202 #include <asm/immap_5282.h> 203 #include <asm/m5282.h> 204 205 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 206 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) 207 208 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 209 #define CONFIG_SYS_NUM_IRQS (128) 210 211 /* Timer */ 212 #ifdef CONFIG_MCFTMR 213 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 214 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR3) 215 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprl0) 216 #define CONFIG_SYS_TMRINTR_NO (INT0_LO_DTMR3) 217 #define CONFIG_SYS_TMRINTR_MASK (1 << INT0_LO_DTMR3) 218 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 219 #define CONFIG_SYS_TMRINTR_PRI (0x1E) /* Level must include inorder to work */ 220 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 221 #endif 222 #endif /* CONFIG_M5282 */ 223 224 #ifdef CONFIG_M5307 225 #include <asm/immap_5307.h> 226 #include <asm/m5307.h> 227 228 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ 229 (CONFIG_SYS_UART_PORT * 0x40)) 230 #define CONFIG_SYS_INTR_BASE (MMAP_INTC) 231 #define CONFIG_SYS_NUM_IRQS (64) 232 233 /* Timer */ 234 #ifdef CONFIG_MCFTMR 235 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 236 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 237 #define CONFIG_SYS_TMRPND_REG (((volatile intctrl_t *) \ 238 (CONFIG_SYS_INTR_BASE))->ipr) 239 #define CONFIG_SYS_TMRINTR_NO (31) 240 #define CONFIG_SYS_TMRINTR_MASK (0x00000400) 241 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 242 #define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | \ 243 MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) 244 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 245 #endif 246 #endif /* CONFIG_M5307 */ 247 248 #if defined(CONFIG_MCF5301x) 249 #include <asm/immap_5301x.h> 250 #include <asm/m5301x.h> 251 252 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 253 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 254 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 255 256 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 257 258 /* Timer */ 259 #ifdef CONFIG_MCFTMR 260 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 261 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 262 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 263 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 264 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 265 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 266 #define CONFIG_SYS_TMRINTR_PRI (6) 267 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 268 #endif 269 270 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 271 #define CONFIG_SYS_NUM_IRQS (128) 272 #endif /* CONFIG_M5301x */ 273 274 #if defined(CONFIG_M5329) || defined(CONFIG_M5373) 275 #include <asm/immap_5329.h> 276 #include <asm/m5329.h> 277 278 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC) 279 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 280 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 281 282 /* Timer */ 283 #ifdef CONFIG_MCFTMR 284 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 285 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 286 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 287 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 288 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 289 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 290 #define CONFIG_SYS_TMRINTR_PRI (6) 291 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 292 #endif 293 294 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 295 #define CONFIG_SYS_NUM_IRQS (128) 296 #endif /* CONFIG_M5329 && CONFIG_M5373 */ 297 298 #if defined(CONFIG_M54418) 299 #include <asm/immap_5441x.h> 300 #include <asm/m5441x.h> 301 302 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 303 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 304 305 #if (CONFIG_SYS_UART_PORT < 4) 306 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + \ 307 (CONFIG_SYS_UART_PORT * 0x4000)) 308 #else 309 #define CONFIG_SYS_UART_BASE (MMAP_UART4 + \ 310 ((CONFIG_SYS_UART_PORT - 4) * 0x4000)) 311 #endif 312 313 #define MMAP_DSPI MMAP_DSPI0 314 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 315 316 /* Timer */ 317 #ifdef CONFIG_MCFTMR 318 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 319 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 320 #define CONFIG_SYS_TMRPND_REG (((int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 321 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 322 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 323 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 324 #define CONFIG_SYS_TMRINTR_PRI (6) 325 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 326 #endif 327 328 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 329 #define CONFIG_SYS_NUM_IRQS (192) 330 331 #endif /* CONFIG_M54418 */ 332 333 #if defined(CONFIG_M54451) || defined(CONFIG_M54455) 334 #include <asm/immap_5445x.h> 335 #include <asm/m5445x.h> 336 337 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 338 #if defined(CONFIG_M54455EVB) 339 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 340 #endif 341 342 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x4000)) 343 344 #define CONFIG_SYS_MCFRTC_BASE (MMAP_RTC) 345 346 /* Timer */ 347 #ifdef CONFIG_MCFTMR 348 #define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) 349 #define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) 350 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 351 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_DTMR1) 352 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT33) 353 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 354 #define CONFIG_SYS_TMRINTR_PRI (6) 355 #define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) 356 #endif 357 358 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 359 #define CONFIG_SYS_NUM_IRQS (128) 360 361 #ifdef CONFIG_PCI 362 #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) 363 #define CONFIG_SYS_PCI_BAR5 (CONFIG_SYS_SDRAM_BASE) 364 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 365 #define CONFIG_SYS_PCI_TBATR5 (CONFIG_SYS_SDRAM_BASE) 366 #endif 367 #endif /* CONFIG_M54451 || CONFIG_M54455 */ 368 369 #ifdef CONFIG_M547x 370 #include <asm/immap_547x_8x.h> 371 #include <asm/m547x_8x.h> 372 373 #ifdef CONFIG_FSLDMAFEC 374 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 375 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 376 377 #define FEC0_RX_TASK 0 378 #define FEC0_TX_TASK 1 379 #define FEC0_RX_PRIORITY 6 380 #define FEC0_TX_PRIORITY 7 381 #define FEC0_RX_INIT 16 382 #define FEC0_TX_INIT 17 383 #define FEC1_RX_TASK 2 384 #define FEC1_TX_TASK 3 385 #define FEC1_RX_PRIORITY 6 386 #define FEC1_TX_PRIORITY 7 387 #define FEC1_RX_INIT 30 388 #define FEC1_TX_INIT 31 389 #endif 390 391 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) 392 393 #ifdef CONFIG_SLTTMR 394 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) 395 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0) 396 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 397 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) 398 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 399 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 400 #define CONFIG_SYS_TMRINTR_PRI (0x1E) 401 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 402 #endif 403 404 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 405 #define CONFIG_SYS_NUM_IRQS (128) 406 407 #ifdef CONFIG_PCI 408 #define CONFIG_SYS_PCI_BAR0 (0x40000000) 409 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) 410 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 411 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) 412 #endif 413 #endif /* CONFIG_M547x */ 414 415 #ifdef CONFIG_M548x 416 #include <asm/immap_547x_8x.h> 417 #include <asm/m547x_8x.h> 418 419 #ifdef CONFIG_FSLDMAFEC 420 #define CONFIG_SYS_FEC0_IOBASE (MMAP_FEC0) 421 #define CONFIG_SYS_FEC1_IOBASE (MMAP_FEC1) 422 423 #define FEC0_RX_TASK 0 424 #define FEC0_TX_TASK 1 425 #define FEC0_RX_PRIORITY 6 426 #define FEC0_TX_PRIORITY 7 427 #define FEC0_RX_INIT 16 428 #define FEC0_TX_INIT 17 429 #define FEC1_RX_TASK 2 430 #define FEC1_TX_TASK 3 431 #define FEC1_RX_PRIORITY 6 432 #define FEC1_TX_PRIORITY 7 433 #define FEC1_RX_INIT 30 434 #define FEC1_TX_INIT 31 435 #endif 436 437 #define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x100)) 438 439 /* Timer */ 440 #ifdef CONFIG_SLTTMR 441 #define CONFIG_SYS_UDELAY_BASE (MMAP_SLT1) 442 #define CONFIG_SYS_TMR_BASE (MMAP_SLT0) 443 #define CONFIG_SYS_TMRPND_REG (((volatile int0_t *)(CONFIG_SYS_INTR_BASE))->iprh0) 444 #define CONFIG_SYS_TMRINTR_NO (INT0_HI_SLT0) 445 #define CONFIG_SYS_TMRINTR_MASK (INTC_IPRH_INT54) 446 #define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) 447 #define CONFIG_SYS_TMRINTR_PRI (0x1E) 448 #define CONFIG_SYS_TIMER_PRESCALER (gd->bus_clk / 1000000) 449 #endif 450 451 #define CONFIG_SYS_INTR_BASE (MMAP_INTC0) 452 #define CONFIG_SYS_NUM_IRQS (128) 453 454 #ifdef CONFIG_PCI 455 #define CONFIG_SYS_PCI_BAR0 (CONFIG_SYS_MBAR) 456 #define CONFIG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) 457 #define CONFIG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) 458 #define CONFIG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) 459 #endif 460 #endif /* CONFIG_M548x */ 461 462 #endif /* __IMMAP_H */ 463