1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd.
4 */
5 #include <common.h>
6 #include <clk.h>
7 #include <cpu_func.h>
8 #include <dm.h>
9 #include <fastboot.h>
10 #include <init.h>
11 #include <log.h>
12 #include <ram.h>
13 #include <syscon.h>
14 #include <asm/cache.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #include <asm/arch-rockchip/boot_mode.h>
18 #include <asm/arch-rockchip/clock.h>
19 #include <asm/arch-rockchip/periph.h>
20 #include <asm/arch-rockchip/misc.h>
21 #include <power/regulator.h>
22
23 DECLARE_GLOBAL_DATA_PTR;
24
rk_board_late_init(void)25 __weak int rk_board_late_init(void)
26 {
27 return 0;
28 }
29
board_late_init(void)30 int board_late_init(void)
31 {
32 setup_boot_mode();
33
34 return rk_board_late_init();
35 }
36
board_init(void)37 int board_init(void)
38 {
39 int ret;
40
41 #ifdef CONFIG_DM_REGULATOR
42 ret = regulators_enable_boot_on(false);
43 if (ret)
44 debug("%s: Cannot enable boot on regulator\n", __func__);
45 #endif
46
47 return 0;
48 }
49
50 #if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
enable_caches(void)51 void enable_caches(void)
52 {
53 /* Enable D-cache. I-cache is already enabled in start.S */
54 dcache_enable();
55 }
56 #endif
57
58 #if defined(CONFIG_USB_GADGET)
59 #include <usb.h>
60
61 #if defined(CONFIG_USB_GADGET_DWC2_OTG)
62 #include <usb/dwc2_udc.h>
63
64 static struct dwc2_plat_otg_data otg_data = {
65 .rx_fifo_sz = 512,
66 .np_tx_fifo_sz = 16,
67 .tx_fifo_sz = 128,
68 };
69
board_usb_init(int index,enum usb_init_type init)70 int board_usb_init(int index, enum usb_init_type init)
71 {
72 ofnode node;
73 const char *mode;
74 bool matched = false;
75
76 /* find the usb_otg node */
77 node = ofnode_by_compatible(ofnode_null(), "snps,dwc2");
78 while (ofnode_valid(node)) {
79 mode = ofnode_read_string(node, "dr_mode");
80 if (mode && strcmp(mode, "otg") == 0) {
81 matched = true;
82 break;
83 }
84
85 node = ofnode_by_compatible(node, "snps,dwc2");
86 }
87 if (!matched) {
88 debug("Not found usb_otg device\n");
89 return -ENODEV;
90 }
91 otg_data.regs_otg = ofnode_get_addr(node);
92
93 #ifdef CONFIG_ROCKCHIP_RK3288
94 int ret;
95 u32 phandle, offset;
96 ofnode phy_node;
97
98 ret = ofnode_read_u32(node, "phys", &phandle);
99 if (ret)
100 return ret;
101
102 node = ofnode_get_by_phandle(phandle);
103 if (!ofnode_valid(node)) {
104 debug("Not found usb phy device\n");
105 return -ENODEV;
106 }
107
108 phy_node = ofnode_get_parent(node);
109 if (!ofnode_valid(node)) {
110 debug("Not found usb phy device\n");
111 return -ENODEV;
112 }
113
114 otg_data.phy_of_node = phy_node;
115 ret = ofnode_read_u32(node, "reg", &offset);
116 if (ret)
117 return ret;
118 otg_data.regs_phy = offset +
119 (u32)syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
120 #endif
121 return dwc2_udc_probe(&otg_data);
122 }
123
board_usb_cleanup(int index,enum usb_init_type init)124 int board_usb_cleanup(int index, enum usb_init_type init)
125 {
126 return 0;
127 }
128 #endif /* CONFIG_USB_GADGET_DWC2_OTG */
129
130 #if defined(CONFIG_USB_DWC3_GADGET) && !defined(CONFIG_DM_USB_GADGET)
131 #include <dwc3-uboot.h>
132
133 static struct dwc3_device dwc3_device_data = {
134 .maximum_speed = USB_SPEED_HIGH,
135 .base = 0xfe800000,
136 .dr_mode = USB_DR_MODE_PERIPHERAL,
137 .index = 0,
138 .dis_u2_susphy_quirk = 1,
139 .hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
140 };
141
usb_gadget_handle_interrupts(int index)142 int usb_gadget_handle_interrupts(int index)
143 {
144 dwc3_uboot_handle_interrupt(0);
145 return 0;
146 }
147
board_usb_init(int index,enum usb_init_type init)148 int board_usb_init(int index, enum usb_init_type init)
149 {
150 return dwc3_uboot_init(&dwc3_device_data);
151 }
152 #endif /* CONFIG_USB_DWC3_GADGET */
153
154 #endif /* CONFIG_USB_GADGET */
155
156 #if CONFIG_IS_ENABLED(FASTBOOT)
fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)157 int fastboot_set_reboot_flag(enum fastboot_reboot_reason reason)
158 {
159 if (reason != FASTBOOT_REBOOT_REASON_BOOTLOADER)
160 return -ENOTSUPP;
161
162 printf("Setting reboot to fastboot flag ...\n");
163 /* Set boot mode to fastboot */
164 writel(BOOT_FASTBOOT, CONFIG_ROCKCHIP_BOOT_MODE_REG);
165
166 return 0;
167 }
168 #endif
169
170 #ifdef CONFIG_MISC_INIT_R
misc_init_r(void)171 __weak int misc_init_r(void)
172 {
173 const u32 cpuid_offset = 0x7;
174 const u32 cpuid_length = 0x10;
175 u8 cpuid[cpuid_length];
176 int ret;
177
178 ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
179 if (ret)
180 return ret;
181
182 ret = rockchip_cpuid_set(cpuid, cpuid_length);
183 if (ret)
184 return ret;
185
186 ret = rockchip_setup_macaddr();
187
188 return ret;
189 }
190 #endif
191