1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Xilinx Zynq MPSoC Firmware driver 4 * 5 * Copyright (C) 2018-2019 Xilinx, Inc. 6 */ 7 8 #ifndef _ZYNQMP_FIRMWARE_H_ 9 #define _ZYNQMP_FIRMWARE_H_ 10 11 enum pm_api_id { 12 PM_GET_API_VERSION = 1, 13 PM_SET_CONFIGURATION, 14 PM_GET_NODE_STATUS, 15 PM_GET_OPERATING_CHARACTERISTIC, 16 PM_REGISTER_NOTIFIER, 17 PM_REQUEST_SUSPEND, 18 PM_SELF_SUSPEND, 19 PM_FORCE_POWERDOWN, 20 PM_ABORT_SUSPEND, 21 PM_REQUEST_WAKEUP, 22 PM_SET_WAKEUP_SOURCE, 23 PM_SYSTEM_SHUTDOWN, 24 PM_REQUEST_NODE, 25 PM_RELEASE_NODE, 26 PM_SET_REQUIREMENT, 27 PM_SET_MAX_LATENCY, 28 PM_RESET_ASSERT, 29 PM_RESET_GET_STATUS, 30 PM_MMIO_WRITE, 31 PM_MMIO_READ, 32 PM_PM_INIT_FINALIZE, 33 PM_FPGA_LOAD, 34 PM_FPGA_GET_STATUS, 35 PM_GET_CHIPID, 36 PM_SECURE_SHA = 26, 37 PM_SECURE_RSA, 38 PM_PINCTRL_REQUEST, 39 PM_PINCTRL_RELEASE, 40 PM_PINCTRL_GET_FUNCTION, 41 PM_PINCTRL_SET_FUNCTION, 42 PM_PINCTRL_CONFIG_PARAM_GET, 43 PM_PINCTRL_CONFIG_PARAM_SET, 44 PM_IOCTL, 45 PM_QUERY_DATA, 46 PM_CLOCK_ENABLE, 47 PM_CLOCK_DISABLE, 48 PM_CLOCK_GETSTATE, 49 PM_CLOCK_SETDIVIDER, 50 PM_CLOCK_GETDIVIDER, 51 PM_CLOCK_SETRATE, 52 PM_CLOCK_GETRATE, 53 PM_CLOCK_SETPARENT, 54 PM_CLOCK_GETPARENT, 55 PM_SECURE_IMAGE, 56 PM_FPGA_READ = 46, 57 PM_SECURE_AES, 58 PM_CLOCK_PLL_GETPARAM = 49, 59 PM_REGISTER_ACCESS = 52, 60 PM_EFUSE_ACCESS, 61 PM_FEATURE_CHECK = 63, 62 PM_API_MAX, 63 }; 64 65 enum pm_query_id { 66 PM_QID_INVALID = 0, 67 PM_QID_CLOCK_GET_NAME = 1, 68 PM_QID_CLOCK_GET_TOPOLOGY = 2, 69 PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS = 3, 70 PM_QID_CLOCK_GET_PARENTS = 4, 71 PM_QID_CLOCK_GET_ATTRIBUTES = 5, 72 PM_QID_PINCTRL_GET_NUM_PINS = 6, 73 PM_QID_PINCTRL_GET_NUM_FUNCTIONS = 7, 74 PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS = 8, 75 PM_QID_PINCTRL_GET_FUNCTION_NAME = 9, 76 PM_QID_PINCTRL_GET_FUNCTION_GROUPS = 10, 77 PM_QID_PINCTRL_GET_PIN_GROUPS = 11, 78 PM_QID_CLOCK_GET_NUM_CLOCKS = 12, 79 PM_QID_CLOCK_GET_MAX_DIVISOR = 13, 80 }; 81 82 #define PM_SIP_SVC 0xc2000000 83 84 #define ZYNQMP_PM_VERSION_MAJOR 1 85 #define ZYNQMP_PM_VERSION_MINOR 0 86 #define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16 87 #define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF 88 89 #define ZYNQMP_PM_VERSION \ 90 ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \ 91 ZYNQMP_PM_VERSION_MINOR) 92 93 #define ZYNQMP_PM_VERSION_INVALID ~0 94 95 #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) 96 97 /* 98 * Return payload size 99 * Not every firmware call expects the same amount of return bytes, however the 100 * firmware driver always copies 5 bytes from RX buffer to the ret_payload 101 * buffer. Therefore allocating with this defined value is recommended to avoid 102 * overflows. 103 */ 104 #define PAYLOAD_ARG_CNT 5U 105 106 unsigned int zynqmp_firmware_version(void); 107 void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size); 108 int xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, 109 u32 arg3, u32 *ret_payload); 110 111 #endif /* _ZYNQMP_FIRMWARE_H_ */ 112