1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009 Industrie Dial Face S.p.A.
4 * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
5 *
6 * (C) Copyright 2001
7 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
8 */
9
10 /*
11 * This provides a bit-banged interface to the ethernet MII management
12 * channel.
13 */
14
15 #include <common.h>
16 #include <ioports.h>
17 #include <ppc_asm.tmpl>
18 #include <miiphy.h>
19 #include <asm/global_data.h>
20
21 #define BB_MII_RELOCATE(v,off) (v += (v?off:0))
22
23 DECLARE_GLOBAL_DATA_PTR;
24
25 #ifndef CONFIG_BITBANGMII_MULTI
26
27 /*
28 * If CONFIG_BITBANGMII_MULTI is not defined we use a
29 * compatibility layer with the previous miiphybb implementation
30 * based on macros usage.
31 *
32 */
bb_mii_init_wrap(struct bb_miiphy_bus * bus)33 static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
34 {
35 #ifdef MII_INIT
36 MII_INIT;
37 #endif
38 return 0;
39 }
40
bb_mdio_active_wrap(struct bb_miiphy_bus * bus)41 static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
42 {
43 #ifdef MDIO_DECLARE
44 MDIO_DECLARE;
45 #endif
46 MDIO_ACTIVE;
47 return 0;
48 }
49
bb_mdio_tristate_wrap(struct bb_miiphy_bus * bus)50 static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
51 {
52 #ifdef MDIO_DECLARE
53 MDIO_DECLARE;
54 #endif
55 MDIO_TRISTATE;
56 return 0;
57 }
58
bb_set_mdio_wrap(struct bb_miiphy_bus * bus,int v)59 static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
60 {
61 #ifdef MDIO_DECLARE
62 MDIO_DECLARE;
63 #endif
64 MDIO(v);
65 return 0;
66 }
67
bb_get_mdio_wrap(struct bb_miiphy_bus * bus,int * v)68 static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
69 {
70 #ifdef MDIO_DECLARE
71 MDIO_DECLARE;
72 #endif
73 *v = MDIO_READ;
74 return 0;
75 }
76
bb_set_mdc_wrap(struct bb_miiphy_bus * bus,int v)77 static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
78 {
79 #ifdef MDC_DECLARE
80 MDC_DECLARE;
81 #endif
82 MDC(v);
83 return 0;
84 }
85
bb_delay_wrap(struct bb_miiphy_bus * bus)86 static int bb_delay_wrap(struct bb_miiphy_bus *bus)
87 {
88 MIIDELAY;
89 return 0;
90 }
91
92 struct bb_miiphy_bus bb_miiphy_buses[] = {
93 {
94 .name = BB_MII_DEVNAME,
95 .init = bb_mii_init_wrap,
96 .mdio_active = bb_mdio_active_wrap,
97 .mdio_tristate = bb_mdio_tristate_wrap,
98 .set_mdio = bb_set_mdio_wrap,
99 .get_mdio = bb_get_mdio_wrap,
100 .set_mdc = bb_set_mdc_wrap,
101 .delay = bb_delay_wrap,
102 }
103 };
104
105 int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
106 sizeof(bb_miiphy_buses[0]);
107 #endif
108
bb_miiphy_init(void)109 int bb_miiphy_init(void)
110 {
111 int i;
112
113 for (i = 0; i < bb_miiphy_buses_num; i++) {
114 #if defined(CONFIG_NEEDS_MANUAL_RELOC)
115 /* Relocate the hook pointers*/
116 BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
117 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
118 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
119 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
120 BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
121 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
122 BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
123 #endif
124 if (bb_miiphy_buses[i].init != NULL) {
125 bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
126 }
127 }
128
129 return 0;
130 }
131
bb_miiphy_getbus(const char * devname)132 static inline struct bb_miiphy_bus *bb_miiphy_getbus(const char *devname)
133 {
134 #ifdef CONFIG_BITBANGMII_MULTI
135 int i;
136
137 /* Search the correct bus */
138 for (i = 0; i < bb_miiphy_buses_num; i++) {
139 if (!strcmp(bb_miiphy_buses[i].name, devname)) {
140 return &bb_miiphy_buses[i];
141 }
142 }
143 return NULL;
144 #else
145 /* We have just one bitbanging bus */
146 return &bb_miiphy_buses[0];
147 #endif
148 }
149
150 /*****************************************************************************
151 *
152 * Utility to send the preamble, address, and register (common to read
153 * and write).
154 */
miiphy_pre(struct bb_miiphy_bus * bus,char read,unsigned char addr,unsigned char reg)155 static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
156 unsigned char addr, unsigned char reg)
157 {
158 int j;
159
160 /*
161 * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
162 * The IEEE spec says this is a PHY optional requirement. The AMD
163 * 79C874 requires one after power up and one after a MII communications
164 * error. This means that we are doing more preambles than we need,
165 * but it is safer and will be much more robust.
166 */
167
168 bus->mdio_active(bus);
169 bus->set_mdio(bus, 1);
170 for (j = 0; j < 32; j++) {
171 bus->set_mdc(bus, 0);
172 bus->delay(bus);
173 bus->set_mdc(bus, 1);
174 bus->delay(bus);
175 }
176
177 /* send the start bit (01) and the read opcode (10) or write (10) */
178 bus->set_mdc(bus, 0);
179 bus->set_mdio(bus, 0);
180 bus->delay(bus);
181 bus->set_mdc(bus, 1);
182 bus->delay(bus);
183 bus->set_mdc(bus, 0);
184 bus->set_mdio(bus, 1);
185 bus->delay(bus);
186 bus->set_mdc(bus, 1);
187 bus->delay(bus);
188 bus->set_mdc(bus, 0);
189 bus->set_mdio(bus, read);
190 bus->delay(bus);
191 bus->set_mdc(bus, 1);
192 bus->delay(bus);
193 bus->set_mdc(bus, 0);
194 bus->set_mdio(bus, !read);
195 bus->delay(bus);
196 bus->set_mdc(bus, 1);
197 bus->delay(bus);
198
199 /* send the PHY address */
200 for (j = 0; j < 5; j++) {
201 bus->set_mdc(bus, 0);
202 if ((addr & 0x10) == 0) {
203 bus->set_mdio(bus, 0);
204 } else {
205 bus->set_mdio(bus, 1);
206 }
207 bus->delay(bus);
208 bus->set_mdc(bus, 1);
209 bus->delay(bus);
210 addr <<= 1;
211 }
212
213 /* send the register address */
214 for (j = 0; j < 5; j++) {
215 bus->set_mdc(bus, 0);
216 if ((reg & 0x10) == 0) {
217 bus->set_mdio(bus, 0);
218 } else {
219 bus->set_mdio(bus, 1);
220 }
221 bus->delay(bus);
222 bus->set_mdc(bus, 1);
223 bus->delay(bus);
224 reg <<= 1;
225 }
226 }
227
228 /*****************************************************************************
229 *
230 * Read a MII PHY register.
231 *
232 * Returns:
233 * 0 on success
234 */
bb_miiphy_read(struct mii_dev * miidev,int addr,int devad,int reg)235 int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg)
236 {
237 unsigned short rdreg; /* register working value */
238 int v;
239 int j; /* counter */
240 struct bb_miiphy_bus *bus;
241
242 bus = bb_miiphy_getbus(miidev->name);
243 if (bus == NULL) {
244 return -1;
245 }
246
247 miiphy_pre (bus, 1, addr, reg);
248
249 /* tri-state our MDIO I/O pin so we can read */
250 bus->set_mdc(bus, 0);
251 bus->mdio_tristate(bus);
252 bus->delay(bus);
253 bus->set_mdc(bus, 1);
254 bus->delay(bus);
255
256 /* check the turnaround bit: the PHY should be driving it to zero */
257 bus->get_mdio(bus, &v);
258 if (v != 0) {
259 /* puts ("PHY didn't drive TA low\n"); */
260 for (j = 0; j < 32; j++) {
261 bus->set_mdc(bus, 0);
262 bus->delay(bus);
263 bus->set_mdc(bus, 1);
264 bus->delay(bus);
265 }
266 /* There is no PHY, return */
267 return -1;
268 }
269
270 bus->set_mdc(bus, 0);
271 bus->delay(bus);
272
273 /* read 16 bits of register data, MSB first */
274 rdreg = 0;
275 for (j = 0; j < 16; j++) {
276 bus->set_mdc(bus, 1);
277 bus->delay(bus);
278 rdreg <<= 1;
279 bus->get_mdio(bus, &v);
280 rdreg |= (v & 0x1);
281 bus->set_mdc(bus, 0);
282 bus->delay(bus);
283 }
284
285 bus->set_mdc(bus, 1);
286 bus->delay(bus);
287 bus->set_mdc(bus, 0);
288 bus->delay(bus);
289 bus->set_mdc(bus, 1);
290 bus->delay(bus);
291
292 #ifdef DEBUG
293 printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg);
294 #endif
295
296 return rdreg;
297 }
298
299
300 /*****************************************************************************
301 *
302 * Write a MII PHY register.
303 *
304 * Returns:
305 * 0 on success
306 */
bb_miiphy_write(struct mii_dev * miidev,int addr,int devad,int reg,u16 value)307 int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
308 u16 value)
309 {
310 struct bb_miiphy_bus *bus;
311 int j; /* counter */
312
313 bus = bb_miiphy_getbus(miidev->name);
314 if (bus == NULL) {
315 /* Bus not found! */
316 return -1;
317 }
318
319 miiphy_pre (bus, 0, addr, reg);
320
321 /* send the turnaround (10) */
322 bus->set_mdc(bus, 0);
323 bus->set_mdio(bus, 1);
324 bus->delay(bus);
325 bus->set_mdc(bus, 1);
326 bus->delay(bus);
327 bus->set_mdc(bus, 0);
328 bus->set_mdio(bus, 0);
329 bus->delay(bus);
330 bus->set_mdc(bus, 1);
331 bus->delay(bus);
332
333 /* write 16 bits of register data, MSB first */
334 for (j = 0; j < 16; j++) {
335 bus->set_mdc(bus, 0);
336 if ((value & 0x00008000) == 0) {
337 bus->set_mdio(bus, 0);
338 } else {
339 bus->set_mdio(bus, 1);
340 }
341 bus->delay(bus);
342 bus->set_mdc(bus, 1);
343 bus->delay(bus);
344 value <<= 1;
345 }
346
347 /*
348 * Tri-state the MDIO line.
349 */
350 bus->mdio_tristate(bus);
351 bus->set_mdc(bus, 0);
352 bus->delay(bus);
353 bus->set_mdc(bus, 1);
354 bus->delay(bus);
355
356 return 0;
357 }
358