1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018-2021 Marvell International Ltd.
4 */
5
6#include "cn9130.dtsi" /* include SoC device tree */
7#include "cn9130-db-dev-info.dtsi"
8
9/ {
10	model = "DB-CN-9130";
11	compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
12		     "marvell,cn9030", "marvell,armada-ap806-quad",
13		     "marvell,armada-ap806";
14
15	chosen {
16		stdout-path = "serial0:115200n8";
17	};
18
19	aliases {
20		i2c0 = &cp0_i2c0;
21		gpio0 = &ap_gpio0;
22		gpio1 = &cp0_gpio0;
23		gpio2 = &cp0_gpio1;
24	};
25
26	memory@00000000 {
27		device_type = "memory";
28		reg = <0x0 0x0 0x0 0x80000000>;
29	};
30
31	cp0 {
32		config-space {
33			i2c@701000 {
34				/* U36 */
35				expander0: pca953x@21 {
36					compatible = "nxp,pca9555";
37					#gpio-cells = <2>;
38					reg = <0x21>;
39					status = "okay";
40				};
41			};
42			sdhci@780000 {
43				vqmmc-supply = <&cp0_reg_sd_vccq>;
44				vmmc-supply = <&cp0_reg_sd_vcc>;
45			};
46
47			ap_reg_mmc_vccq: ap_mmc_vccq@0 {
48				compatible = "regulator-gpio";
49				regulator-name = "ap_mmc_vccq";
50				regulator-min-microvolt = <1800000>;
51				regulator-max-microvolt = <3300000>;
52				gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
53				states = <1800000 0x1
54					  3300000 0x0>;
55			};
56			cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
57				compatible = "regulator-fixed";
58				regulator-name = "cp0-xhci0-vbus";
59				regulator-min-microvolt = <5000000>;
60				regulator-max-microvolt = <5000000>;
61				startup-delay-us = <100000>;
62				regulator-force-boot-off;
63				gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
64			};
65
66			cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
67				compatible = "regulator-fixed";
68				regulator-name = "cp0-xhci1-vbus";
69				regulator-min-microvolt = <5000000>;
70				regulator-max-microvolt = <5000000>;
71				startup-delay-us = <100000>;
72				regulator-force-boot-off;
73				gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
74			};
75			cp0_reg_sd_vccq: cp0_sd_vccq@0 {
76				compatible = "regulator-gpio";
77				regulator-name = "cp0_sd_vccq";
78				regulator-min-microvolt = <1800000>;
79				regulator-max-microvolt = <3300000>;
80				gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
81				states = <1800000 0x1
82					  3300000 0x0>;
83			};
84			cp0_reg_sd_vcc: cp0_sd_vcc@0 {
85				compatible = "regulator-fixed";
86				regulator-name = "cp0_sd_vcc";
87				regulator-min-microvolt = <3300000>;
88				regulator-max-microvolt = <3300000>;
89				gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
90				enable-active-high;
91				regulator-always-on;
92			};
93			cp0_reg_usb3_current_lim0:cp0_usb3_current_limiter@0 {
94				compatible = "regulator-fixed";
95				regulator-min-microamp = <900000>;
96				regulator-max-microamp = <900000>;
97				regulator-force-boot-off;
98				gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
99			};
100
101			cp0_reg_usb3_current_lim1: cp0_usb3_current_limiter@1 {
102				compatible = "regulator-fixed";
103				regulator-min-microamp = <900000>;
104				regulator-max-microamp = <900000>;
105				regulator-force-boot-off;
106				gpio = <&expander0 5 GPIO_ACTIVE_HIGH>;
107			};
108		};
109	};
110};
111
112&uart0 {
113	status = "okay";
114};
115
116/*
117 * AP related configuration
118 */
119&ap_pinctl {
120	/* MPP Bus:
121	 * SDIO  [0-10, 12]
122	 * UART0 [11,19]
123	 */
124		/*   0 1 2 3 4 5 6 7 8 9 */
125	pin-func = < 1 1 1 1 1 1 1 1 1 1
126		     1 3 1 0 0 0 0 0 0 3 >;
127};
128
129/* on-board eMMC - U9 */
130&ap_sdhci0 {
131	pinctrl-names = "default";
132	pinctrl-0 = <&ap_emmc_pins>;
133	vqmmc-supply = <&ap_reg_mmc_vccq>;
134	bus-width = <8>;
135	mmc-ddr-1_8v;
136	mmc-hs400-1_8v;
137	status = "okay";
138};
139
140/*
141 * CP related configuration
142 */
143&cp0_pinctl {
144	cp0_nand_pins: cp0-nand-pins {
145		marvell,pins = <15 16 17 18 19 20 21 22 23 24 25 26 27 >;
146		marvell,function = <1>;
147	};
148	cp0_nand_rb: cp0-nand-rb {
149		marvell,pins = < 13 >;
150		marvell,function = <2>;
151	};
152};
153
154/*
155 * CP0
156 */
157&cp0_i2c0 {
158	pinctrl-names = "default";
159	pinctrl-0 = <&cp0_i2c0_pins>;
160	status = "okay";
161	clock-frequency = <100000>;
162};
163
164&cp0_i2c1 {
165	status = "okay";
166};
167
168/* CON 28 */
169&cp0_sdhci0 {
170	pinctrl-names = "default";
171	pinctrl-0 = <&cp0_sdhci_pins>;
172	bus-width = <4>;
173	status = "okay";
174};
175
176/* U54 */
177&cp0_nand {
178	pinctrl-names = "default";
179	pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
180	status = "disabled";
181};
182
183/* U55 */
184&cp0_spi1 {
185	pinctrl-names = "default";
186	pinctrl-0 = <&cp0_spi0_pins>;
187	reg = <0x700680 0x50>,		/* control */
188	      <0x2000000 0x1000000>,	/* CS0 */
189	      <0 0xffffffff>,		/* CS1 */
190	      <0 0xffffffff>,		/* CS2 */
191	      <0 0xffffffff>;		/* CS3 */
192	status = "disabled";
193
194	spi-flash@0 {
195		#address-cells = <0x1>;
196		#size-cells = <0x1>;
197		compatible = "jedec,spi-nor", "spi-flash";
198		reg = <0x0>;
199		/* On-board MUX does not allow higher frequencies */
200		spi-max-frequency = <40000000>;
201
202		partitions {
203			compatible = "fixed-partitions";
204			#address-cells = <1>;
205			#size-cells = <1>;
206
207			partition@0 {
208				label = "U-Boot";
209				reg = <0x0 0x200000>;
210			};
211
212			partition@400000 {
213				label = "Filesystem";
214				reg = <0x200000 0xe00000>;
215			};
216		};
217	};
218};
219
220&cp0_comphy {
221	phy0 {
222		phy-type = <COMPHY_TYPE_PEX0>;
223	};
224
225	phy1 {
226		phy-type = <COMPHY_TYPE_PEX0>;
227	};
228
229	phy2 {
230		phy-type = <COMPHY_TYPE_PEX0>;
231	};
232
233	phy3 {
234		phy-type = <COMPHY_TYPE_PEX0>;
235	};
236
237	phy4 {
238		phy-type = <COMPHY_TYPE_SFI0>;
239		phy-speed = <COMPHY_SPEED_10_3125G>;
240	};
241
242	phy5 {
243		phy-type = <COMPHY_TYPE_SATA1>;
244	};
245};
246
247/* SLM-1521-V2, CON6 */
248&cp0_pcie0 {
249	num-lanes = <4>;
250	status = "disabled";
251};
252
253&cp0_mdio {
254	status = "okay";
255	phy0: ethernet-phy@0 {
256		reg = <0>;
257	};
258	phy1: ethernet-phy@1 {
259		reg = <1>;
260	};
261};
262
263&cp0_ethernet {
264	status = "okay";
265};
266
267/* SLM-1521-V2, CON9 */
268&cp0_eth0 {
269	status = "okay";
270	phy-mode = "sfi";
271};
272
273/* CON56 */
274&cp0_eth1 {
275	status = "okay";
276	phy = <&phy0>;
277	phy-mode = "rgmii-id";
278};
279
280/* CON57 */
281&cp0_eth2 {
282	status = "okay";
283	phy = <&phy1>;
284	phy-mode = "rgmii-id";
285};
286
287/* SLM-1521-V2, CON2 */
288&cp0_sata0 {
289	status = "okay";
290};
291
292&cp0_utmi0 {
293	status = "okay";
294};
295
296&cp0_utmi1 {
297	status = "okay";
298};
299
300&cp0_usb3_0 {
301	status = "okay";
302	vbus-supply = <&cp0_reg_usb3_vbus0>;
303	current-limiter = <&cp0_reg_usb3_current_lim0>;
304	vbus-disable-delay = <500>;
305};
306
307&cp0_usb3_1 {
308	status = "okay";
309	vbus-supply = <&cp0_reg_usb3_vbus1>;
310	current-limiter = <&cp0_reg_usb3_current_lim1>;
311	vbus-disable-delay = <500>;
312};
313
314&cp0_pcie0 {
315	status = "okay";
316};
317