1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/gpio/gpio.h>
6#include "imx28-pinfunc.h"
7
8/ {
9	#address-cells = <1>;
10	#size-cells = <1>;
11
12	interrupt-parent = <&icoll>;
13	/*
14	 * The decompressor and also some bootloaders rely on a
15	 * pre-existing /chosen node to be available to insert the
16	 * command line and merge other ATAGS info.
17	 */
18	chosen {};
19
20	aliases {
21		ethernet0 = &mac0;
22		ethernet1 = &mac1;
23		gpio0 = &gpio0;
24		gpio1 = &gpio1;
25		gpio2 = &gpio2;
26		gpio3 = &gpio3;
27		gpio4 = &gpio4;
28		saif0 = &saif0;
29		saif1 = &saif1;
30		serial0 = &auart0;
31		serial1 = &auart1;
32		serial2 = &auart2;
33		serial3 = &auart3;
34		serial4 = &auart4;
35		spi0 = &ssp1;
36		spi1 = &ssp2;
37		usbphy0 = &usbphy0;
38		usbphy1 = &usbphy1;
39	};
40
41	cpus {
42		#address-cells = <1>;
43		#size-cells = <0>;
44
45		cpu@0 {
46			compatible = "arm,arm926ej-s";
47			device_type = "cpu";
48			reg = <0>;
49		};
50	};
51
52	apb@80000000 {
53		compatible = "simple-bus";
54		#address-cells = <1>;
55		#size-cells = <1>;
56		reg = <0x80000000 0x80000>;
57		ranges;
58
59		apbh@80000000 {
60			compatible = "simple-bus";
61			#address-cells = <1>;
62			#size-cells = <1>;
63			reg = <0x80000000 0x3c900>;
64			ranges;
65
66			icoll: interrupt-controller@80000000 {
67				compatible = "fsl,imx28-icoll", "fsl,icoll";
68				interrupt-controller;
69				#interrupt-cells = <1>;
70				reg = <0x80000000 0x2000>;
71			};
72
73			hsadc: hsadc@80002000 {
74				reg = <0x80002000 0x2000>;
75				interrupts = <13>;
76				dmas = <&dma_apbh 12>;
77				dma-names = "rx";
78				status = "disabled";
79			};
80
81			dma_apbh: dma-apbh@80004000 {
82				compatible = "fsl,imx28-dma-apbh";
83				reg = <0x80004000 0x2000>;
84				interrupts = <82 83 84 85
85					      88 88 88 88
86					      88 88 88 88
87					      87 86 0 0>;
88				interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
89						  "gpmi0", "gmpi1", "gpmi2", "gmpi3",
90						  "gpmi4", "gmpi5", "gpmi6", "gmpi7",
91						  "hsadc", "lcdif", "empty", "empty";
92				#dma-cells = <1>;
93				dma-channels = <16>;
94				clocks = <&clks 25>;
95			};
96
97			perfmon: perfmon@80006000 {
98				reg = <0x80006000 0x800>;
99				interrupts = <27>;
100				status = "disabled";
101			};
102
103			gpmi: gpmi-nand@8000c000 {
104				compatible = "fsl,imx28-gpmi-nand";
105				#address-cells = <1>;
106				#size-cells = <1>;
107				reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
108				reg-names = "gpmi-nand", "bch";
109				interrupts = <41>;
110				interrupt-names = "bch";
111				clocks = <&clks 50>;
112				clock-names = "gpmi_io";
113				dmas = <&dma_apbh 4>;
114				dma-names = "rx-tx";
115				status = "disabled";
116			};
117
118			ssp0: spi@80010000 {
119				#address-cells = <1>;
120				#size-cells = <0>;
121				reg = <0x80010000 0x2000>;
122				interrupts = <96>;
123				clocks = <&clks 46>;
124				dmas = <&dma_apbh 0>;
125				dma-names = "rx-tx";
126				status = "disabled";
127			};
128
129			ssp1: spi@80012000 {
130				#address-cells = <1>;
131				#size-cells = <0>;
132				reg = <0x80012000 0x2000>;
133				interrupts = <97>;
134				clocks = <&clks 47>;
135				dmas = <&dma_apbh 1>;
136				dma-names = "rx-tx";
137				status = "disabled";
138			};
139
140			ssp2: spi@80014000 {
141				#address-cells = <1>;
142				#size-cells = <0>;
143				reg = <0x80014000 0x2000>;
144				interrupts = <98>;
145				clocks = <&clks 48>;
146				dmas = <&dma_apbh 2>;
147				dma-names = "rx-tx";
148				status = "disabled";
149			};
150
151			ssp3: spi@80016000 {
152				#address-cells = <1>;
153				#size-cells = <0>;
154				reg = <0x80016000 0x2000>;
155				interrupts = <99>;
156				clocks = <&clks 49>;
157				dmas = <&dma_apbh 3>;
158				dma-names = "rx-tx";
159				status = "disabled";
160			};
161
162			pinctrl: pinctrl@80018000 {
163				#address-cells = <1>;
164				#size-cells = <0>;
165				compatible = "fsl,imx28-pinctrl", "simple-bus";
166				reg = <0x80018000 0x2000>;
167
168				gpio0: gpio@0 {
169					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
170					reg = <0>;
171					interrupts = <127>;
172					gpio-controller;
173					#gpio-cells = <2>;
174					interrupt-controller;
175					#interrupt-cells = <2>;
176				};
177
178				gpio1: gpio@1 {
179					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
180					reg = <1>;
181					interrupts = <126>;
182					gpio-controller;
183					#gpio-cells = <2>;
184					interrupt-controller;
185					#interrupt-cells = <2>;
186				};
187
188				gpio2: gpio@2 {
189					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
190					reg = <2>;
191					interrupts = <125>;
192					gpio-controller;
193					#gpio-cells = <2>;
194					interrupt-controller;
195					#interrupt-cells = <2>;
196				};
197
198				gpio3: gpio@3 {
199					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
200					reg = <3>;
201					interrupts = <124>;
202					gpio-controller;
203					#gpio-cells = <2>;
204					interrupt-controller;
205					#interrupt-cells = <2>;
206				};
207
208				gpio4: gpio@4 {
209					compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
210					reg = <4>;
211					interrupts = <123>;
212					gpio-controller;
213					#gpio-cells = <2>;
214					interrupt-controller;
215					#interrupt-cells = <2>;
216				};
217
218				duart_pins_a: duart@0 {
219					reg = <0>;
220					fsl,pinmux-ids = <
221						MX28_PAD_PWM0__DUART_RX
222						MX28_PAD_PWM1__DUART_TX
223					>;
224					fsl,drive-strength = <MXS_DRIVE_4mA>;
225					fsl,voltage = <MXS_VOLTAGE_HIGH>;
226					fsl,pull-up = <MXS_PULL_DISABLE>;
227				};
228
229				duart_pins_b: duart@1 {
230					reg = <1>;
231					fsl,pinmux-ids = <
232						MX28_PAD_AUART0_CTS__DUART_RX
233						MX28_PAD_AUART0_RTS__DUART_TX
234					>;
235					fsl,drive-strength = <MXS_DRIVE_4mA>;
236					fsl,voltage = <MXS_VOLTAGE_HIGH>;
237					fsl,pull-up = <MXS_PULL_DISABLE>;
238				};
239
240				duart_4pins_a: duart-4pins@0 {
241					reg = <0>;
242					fsl,pinmux-ids = <
243						MX28_PAD_AUART0_CTS__DUART_RX
244						MX28_PAD_AUART0_RTS__DUART_TX
245						MX28_PAD_AUART0_RX__DUART_CTS
246						MX28_PAD_AUART0_TX__DUART_RTS
247					>;
248					fsl,drive-strength = <MXS_DRIVE_4mA>;
249					fsl,voltage = <MXS_VOLTAGE_HIGH>;
250					fsl,pull-up = <MXS_PULL_DISABLE>;
251				};
252
253				gpmi_pins_a: gpmi-nand@0 {
254					reg = <0>;
255					fsl,pinmux-ids = <
256						MX28_PAD_GPMI_D00__GPMI_D0
257						MX28_PAD_GPMI_D01__GPMI_D1
258						MX28_PAD_GPMI_D02__GPMI_D2
259						MX28_PAD_GPMI_D03__GPMI_D3
260						MX28_PAD_GPMI_D04__GPMI_D4
261						MX28_PAD_GPMI_D05__GPMI_D5
262						MX28_PAD_GPMI_D06__GPMI_D6
263						MX28_PAD_GPMI_D07__GPMI_D7
264						MX28_PAD_GPMI_CE0N__GPMI_CE0N
265						MX28_PAD_GPMI_RDY0__GPMI_READY0
266						MX28_PAD_GPMI_RDN__GPMI_RDN
267						MX28_PAD_GPMI_WRN__GPMI_WRN
268						MX28_PAD_GPMI_ALE__GPMI_ALE
269						MX28_PAD_GPMI_CLE__GPMI_CLE
270						MX28_PAD_GPMI_RESETN__GPMI_RESETN
271					>;
272					fsl,drive-strength = <MXS_DRIVE_4mA>;
273					fsl,voltage = <MXS_VOLTAGE_HIGH>;
274					fsl,pull-up = <MXS_PULL_DISABLE>;
275				};
276
277				gpmi_status_cfg: gpmi-status-cfg@0 {
278					reg = <0>;
279					fsl,pinmux-ids = <
280						MX28_PAD_GPMI_RDN__GPMI_RDN
281						MX28_PAD_GPMI_WRN__GPMI_WRN
282						MX28_PAD_GPMI_RESETN__GPMI_RESETN
283					>;
284					fsl,drive-strength = <MXS_DRIVE_12mA>;
285				};
286
287				auart0_pins_a: auart0@0 {
288					reg = <0>;
289					fsl,pinmux-ids = <
290						MX28_PAD_AUART0_RX__AUART0_RX
291						MX28_PAD_AUART0_TX__AUART0_TX
292						MX28_PAD_AUART0_CTS__AUART0_CTS
293						MX28_PAD_AUART0_RTS__AUART0_RTS
294					>;
295					fsl,drive-strength = <MXS_DRIVE_4mA>;
296					fsl,voltage = <MXS_VOLTAGE_HIGH>;
297					fsl,pull-up = <MXS_PULL_DISABLE>;
298				};
299
300				auart0_2pins_a: auart0-2pins@0 {
301					reg = <0>;
302					fsl,pinmux-ids = <
303						MX28_PAD_AUART0_RX__AUART0_RX
304						MX28_PAD_AUART0_TX__AUART0_TX
305					>;
306					fsl,drive-strength = <MXS_DRIVE_4mA>;
307					fsl,voltage = <MXS_VOLTAGE_HIGH>;
308					fsl,pull-up = <MXS_PULL_DISABLE>;
309				};
310
311				auart1_pins_a: auart1@0 {
312					reg = <0>;
313					fsl,pinmux-ids = <
314						MX28_PAD_AUART1_RX__AUART1_RX
315						MX28_PAD_AUART1_TX__AUART1_TX
316						MX28_PAD_AUART1_CTS__AUART1_CTS
317						MX28_PAD_AUART1_RTS__AUART1_RTS
318					>;
319					fsl,drive-strength = <MXS_DRIVE_4mA>;
320					fsl,voltage = <MXS_VOLTAGE_HIGH>;
321					fsl,pull-up = <MXS_PULL_DISABLE>;
322				};
323
324				auart1_2pins_a: auart1-2pins@0 {
325					reg = <0>;
326					fsl,pinmux-ids = <
327						MX28_PAD_AUART1_RX__AUART1_RX
328						MX28_PAD_AUART1_TX__AUART1_TX
329					>;
330					fsl,drive-strength = <MXS_DRIVE_4mA>;
331					fsl,voltage = <MXS_VOLTAGE_HIGH>;
332					fsl,pull-up = <MXS_PULL_DISABLE>;
333				};
334
335				auart2_2pins_a: auart2-2pins@0 {
336					reg = <0>;
337					fsl,pinmux-ids = <
338						MX28_PAD_SSP2_SCK__AUART2_RX
339						MX28_PAD_SSP2_MOSI__AUART2_TX
340					>;
341					fsl,drive-strength = <MXS_DRIVE_4mA>;
342					fsl,voltage = <MXS_VOLTAGE_HIGH>;
343					fsl,pull-up = <MXS_PULL_DISABLE>;
344				};
345
346				auart2_2pins_b: auart2-2pins@1 {
347					reg = <1>;
348					fsl,pinmux-ids = <
349						MX28_PAD_AUART2_RX__AUART2_RX
350						MX28_PAD_AUART2_TX__AUART2_TX
351					>;
352					fsl,drive-strength = <MXS_DRIVE_4mA>;
353					fsl,voltage = <MXS_VOLTAGE_HIGH>;
354					fsl,pull-up = <MXS_PULL_DISABLE>;
355				};
356
357				auart2_pins_a: auart2-pins@0 {
358					reg = <0>;
359					fsl,pinmux-ids = <
360						MX28_PAD_AUART2_RX__AUART2_RX
361						MX28_PAD_AUART2_TX__AUART2_TX
362						MX28_PAD_AUART2_CTS__AUART2_CTS
363						MX28_PAD_AUART2_RTS__AUART2_RTS
364					>;
365					fsl,drive-strength = <MXS_DRIVE_4mA>;
366					fsl,voltage = <MXS_VOLTAGE_HIGH>;
367					fsl,pull-up = <MXS_PULL_DISABLE>;
368				};
369
370				auart3_pins_a: auart3@0 {
371					reg = <0>;
372					fsl,pinmux-ids = <
373						MX28_PAD_AUART3_RX__AUART3_RX
374						MX28_PAD_AUART3_TX__AUART3_TX
375						MX28_PAD_AUART3_CTS__AUART3_CTS
376						MX28_PAD_AUART3_RTS__AUART3_RTS
377					>;
378					fsl,drive-strength = <MXS_DRIVE_4mA>;
379					fsl,voltage = <MXS_VOLTAGE_HIGH>;
380					fsl,pull-up = <MXS_PULL_DISABLE>;
381				};
382
383				auart3_2pins_a: auart3-2pins@0 {
384					reg = <0>;
385					fsl,pinmux-ids = <
386						MX28_PAD_SSP2_MISO__AUART3_RX
387						MX28_PAD_SSP2_SS0__AUART3_TX
388					>;
389					fsl,drive-strength = <MXS_DRIVE_4mA>;
390					fsl,voltage = <MXS_VOLTAGE_HIGH>;
391					fsl,pull-up = <MXS_PULL_DISABLE>;
392				};
393
394				auart3_2pins_b: auart3-2pins@1 {
395					reg = <1>;
396					fsl,pinmux-ids = <
397						MX28_PAD_AUART3_RX__AUART3_RX
398						MX28_PAD_AUART3_TX__AUART3_TX
399					>;
400					fsl,drive-strength = <MXS_DRIVE_4mA>;
401					fsl,voltage = <MXS_VOLTAGE_HIGH>;
402					fsl,pull-up = <MXS_PULL_DISABLE>;
403				};
404
405				auart4_2pins_a: auart4@0 {
406					reg = <0>;
407					fsl,pinmux-ids = <
408						MX28_PAD_SSP3_SCK__AUART4_TX
409						MX28_PAD_SSP3_MOSI__AUART4_RX
410					>;
411					fsl,drive-strength = <MXS_DRIVE_4mA>;
412					fsl,voltage = <MXS_VOLTAGE_HIGH>;
413					fsl,pull-up = <MXS_PULL_DISABLE>;
414				};
415
416				auart4_2pins_b: auart4@1 {
417					reg = <1>;
418					fsl,pinmux-ids = <
419						MX28_PAD_AUART0_CTS__AUART4_RX
420						MX28_PAD_AUART0_RTS__AUART4_TX
421					>;
422					fsl,drive-strength = <MXS_DRIVE_4mA>;
423					fsl,voltage = <MXS_VOLTAGE_HIGH>;
424					fsl,pull-up = <MXS_PULL_DISABLE>;
425				};
426
427				mac0_pins_a: mac0@0 {
428					reg = <0>;
429					fsl,pinmux-ids = <
430						MX28_PAD_ENET0_MDC__ENET0_MDC
431						MX28_PAD_ENET0_MDIO__ENET0_MDIO
432						MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
433						MX28_PAD_ENET0_RXD0__ENET0_RXD0
434						MX28_PAD_ENET0_RXD1__ENET0_RXD1
435						MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
436						MX28_PAD_ENET0_TXD0__ENET0_TXD0
437						MX28_PAD_ENET0_TXD1__ENET0_TXD1
438						MX28_PAD_ENET_CLK__CLKCTRL_ENET
439					>;
440					fsl,drive-strength = <MXS_DRIVE_8mA>;
441					fsl,voltage = <MXS_VOLTAGE_HIGH>;
442					fsl,pull-up = <MXS_PULL_ENABLE>;
443				};
444
445				mac0_pins_b: mac0@1 {
446					reg = <1>;
447					fsl,pinmux-ids = <
448						MX28_PAD_ENET0_MDC__ENET0_MDC
449						MX28_PAD_ENET0_MDIO__ENET0_MDIO
450						MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
451						MX28_PAD_ENET0_RXD0__ENET0_RXD0
452						MX28_PAD_ENET0_RXD1__ENET0_RXD1
453						MX28_PAD_ENET0_RXD2__ENET0_RXD2
454						MX28_PAD_ENET0_RXD3__ENET0_RXD3
455						MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
456						MX28_PAD_ENET0_TXD0__ENET0_TXD0
457						MX28_PAD_ENET0_TXD1__ENET0_TXD1
458						MX28_PAD_ENET0_TXD2__ENET0_TXD2
459						MX28_PAD_ENET0_TXD3__ENET0_TXD3
460						MX28_PAD_ENET_CLK__CLKCTRL_ENET
461						MX28_PAD_ENET0_COL__ENET0_COL
462						MX28_PAD_ENET0_CRS__ENET0_CRS
463						MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK
464						MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK
465						>;
466					fsl,drive-strength = <MXS_DRIVE_8mA>;
467					fsl,voltage = <MXS_VOLTAGE_HIGH>;
468					fsl,pull-up = <MXS_PULL_ENABLE>;
469				};
470
471				mac1_pins_a: mac1@0 {
472					reg = <0>;
473					fsl,pinmux-ids = <
474						MX28_PAD_ENET0_CRS__ENET1_RX_EN
475						MX28_PAD_ENET0_RXD2__ENET1_RXD0
476						MX28_PAD_ENET0_RXD3__ENET1_RXD1
477						MX28_PAD_ENET0_COL__ENET1_TX_EN
478						MX28_PAD_ENET0_TXD2__ENET1_TXD0
479						MX28_PAD_ENET0_TXD3__ENET1_TXD1
480					>;
481					fsl,drive-strength = <MXS_DRIVE_8mA>;
482					fsl,voltage = <MXS_VOLTAGE_HIGH>;
483					fsl,pull-up = <MXS_PULL_ENABLE>;
484				};
485
486				mmc0_8bit_pins_a: mmc0-8bit@0 {
487					reg = <0>;
488					fsl,pinmux-ids = <
489						MX28_PAD_SSP0_DATA0__SSP0_D0
490						MX28_PAD_SSP0_DATA1__SSP0_D1
491						MX28_PAD_SSP0_DATA2__SSP0_D2
492						MX28_PAD_SSP0_DATA3__SSP0_D3
493						MX28_PAD_SSP0_DATA4__SSP0_D4
494						MX28_PAD_SSP0_DATA5__SSP0_D5
495						MX28_PAD_SSP0_DATA6__SSP0_D6
496						MX28_PAD_SSP0_DATA7__SSP0_D7
497						MX28_PAD_SSP0_CMD__SSP0_CMD
498						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
499						MX28_PAD_SSP0_SCK__SSP0_SCK
500					>;
501					fsl,drive-strength = <MXS_DRIVE_8mA>;
502					fsl,voltage = <MXS_VOLTAGE_HIGH>;
503					fsl,pull-up = <MXS_PULL_ENABLE>;
504				};
505
506				mmc0_4bit_pins_a: mmc0-4bit@0 {
507					reg = <0>;
508					fsl,pinmux-ids = <
509						MX28_PAD_SSP0_DATA0__SSP0_D0
510						MX28_PAD_SSP0_DATA1__SSP0_D1
511						MX28_PAD_SSP0_DATA2__SSP0_D2
512						MX28_PAD_SSP0_DATA3__SSP0_D3
513						MX28_PAD_SSP0_CMD__SSP0_CMD
514						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
515						MX28_PAD_SSP0_SCK__SSP0_SCK
516					>;
517					fsl,drive-strength = <MXS_DRIVE_8mA>;
518					fsl,voltage = <MXS_VOLTAGE_HIGH>;
519					fsl,pull-up = <MXS_PULL_ENABLE>;
520				};
521
522				mmc0_cd_cfg: mmc0-cd-cfg@0 {
523					reg = <0>;
524					fsl,pinmux-ids = <
525						MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
526					>;
527					fsl,pull-up = <MXS_PULL_DISABLE>;
528				};
529
530				mmc0_sck_cfg: mmc0-sck-cfg@0 {
531					reg = <0>;
532					fsl,pinmux-ids = <
533						MX28_PAD_SSP0_SCK__SSP0_SCK
534					>;
535					fsl,drive-strength = <MXS_DRIVE_12mA>;
536					fsl,pull-up = <MXS_PULL_DISABLE>;
537				};
538
539				mmc1_4bit_pins_a: mmc1-4bit@0 {
540					reg = <0>;
541					fsl,pinmux-ids = <
542						MX28_PAD_GPMI_D00__SSP1_D0
543						MX28_PAD_GPMI_D01__SSP1_D1
544						MX28_PAD_GPMI_D02__SSP1_D2
545						MX28_PAD_GPMI_D03__SSP1_D3
546						MX28_PAD_GPMI_RDY1__SSP1_CMD
547						MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
548						MX28_PAD_GPMI_WRN__SSP1_SCK
549					>;
550					fsl,drive-strength = <MXS_DRIVE_8mA>;
551					fsl,voltage = <MXS_VOLTAGE_HIGH>;
552					fsl,pull-up = <MXS_PULL_ENABLE>;
553				};
554
555				mmc1_cd_cfg: mmc1-cd-cfg@0 {
556					reg = <0>;
557					fsl,pinmux-ids = <
558						MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT
559					>;
560					fsl,pull-up = <MXS_PULL_DISABLE>;
561				};
562
563				mmc1_sck_cfg: mmc1-sck-cfg@0 {
564					reg = <0>;
565					fsl,pinmux-ids = <
566						MX28_PAD_GPMI_WRN__SSP1_SCK
567					>;
568					fsl,drive-strength = <MXS_DRIVE_12mA>;
569					fsl,pull-up = <MXS_PULL_DISABLE>;
570				};
571
572
573				mmc2_4bit_pins_a: mmc2-4bit@0 {
574					reg = <0>;
575					fsl,pinmux-ids = <
576						MX28_PAD_SSP0_DATA4__SSP2_D0
577						MX28_PAD_SSP1_SCK__SSP2_D1
578						MX28_PAD_SSP1_CMD__SSP2_D2
579						MX28_PAD_SSP0_DATA5__SSP2_D3
580						MX28_PAD_SSP0_DATA6__SSP2_CMD
581						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
582						MX28_PAD_SSP0_DATA7__SSP2_SCK
583					>;
584					fsl,drive-strength = <MXS_DRIVE_8mA>;
585					fsl,voltage = <MXS_VOLTAGE_HIGH>;
586					fsl,pull-up = <MXS_PULL_ENABLE>;
587				};
588
589				mmc2_4bit_pins_b: mmc2-4bit@1 {
590					reg = <1>;
591					fsl,pinmux-ids = <
592						MX28_PAD_SSP2_SCK__SSP2_SCK
593						MX28_PAD_SSP2_MOSI__SSP2_CMD
594						MX28_PAD_SSP2_MISO__SSP2_D0
595						MX28_PAD_SSP2_SS0__SSP2_D3
596						MX28_PAD_SSP2_SS1__SSP2_D1
597						MX28_PAD_SSP2_SS2__SSP2_D2
598						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
599					>;
600					fsl,drive-strength = <MXS_DRIVE_8mA>;
601					fsl,voltage = <MXS_VOLTAGE_HIGH>;
602					fsl,pull-up = <MXS_PULL_ENABLE>;
603				};
604
605				mmc2_cd_cfg: mmc2-cd-cfg@0 {
606					reg = <0>;
607					fsl,pinmux-ids = <
608						MX28_PAD_AUART1_RX__SSP2_CARD_DETECT
609					>;
610					fsl,pull-up = <MXS_PULL_DISABLE>;
611				};
612
613				mmc2_sck_cfg_a: mmc2-sck-cfg@0 {
614					reg = <0>;
615					fsl,pinmux-ids = <
616						MX28_PAD_SSP0_DATA7__SSP2_SCK
617					>;
618					fsl,drive-strength = <MXS_DRIVE_12mA>;
619					fsl,pull-up = <MXS_PULL_DISABLE>;
620				};
621
622				mmc2_sck_cfg_b: mmc2-sck-cfg@1 {
623					reg = <1>;
624					fsl,pinmux-ids = <
625						MX28_PAD_SSP2_SCK__SSP2_SCK
626					>;
627					fsl,drive-strength = <MXS_DRIVE_12mA>;
628					fsl,pull-up = <MXS_PULL_DISABLE>;
629				};
630
631				i2c0_pins_a: i2c0@0 {
632					reg = <0>;
633					fsl,pinmux-ids = <
634						MX28_PAD_I2C0_SCL__I2C0_SCL
635						MX28_PAD_I2C0_SDA__I2C0_SDA
636					>;
637					fsl,drive-strength = <MXS_DRIVE_8mA>;
638					fsl,voltage = <MXS_VOLTAGE_HIGH>;
639					fsl,pull-up = <MXS_PULL_ENABLE>;
640				};
641
642				i2c0_pins_b: i2c0@1 {
643					reg = <1>;
644					fsl,pinmux-ids = <
645						MX28_PAD_AUART0_RX__I2C0_SCL
646						MX28_PAD_AUART0_TX__I2C0_SDA
647					>;
648					fsl,drive-strength = <MXS_DRIVE_8mA>;
649					fsl,voltage = <MXS_VOLTAGE_HIGH>;
650					fsl,pull-up = <MXS_PULL_ENABLE>;
651				};
652
653				i2c1_pins_a: i2c1@0 {
654					reg = <0>;
655					fsl,pinmux-ids = <
656						MX28_PAD_PWM0__I2C1_SCL
657						MX28_PAD_PWM1__I2C1_SDA
658					>;
659					fsl,drive-strength = <MXS_DRIVE_8mA>;
660					fsl,voltage = <MXS_VOLTAGE_HIGH>;
661					fsl,pull-up = <MXS_PULL_ENABLE>;
662				};
663
664				i2c1_pins_b: i2c1@1 {
665					reg = <1>;
666					fsl,pinmux-ids = <
667						MX28_PAD_AUART2_CTS__I2C1_SCL
668						MX28_PAD_AUART2_RTS__I2C1_SDA
669					>;
670					fsl,drive-strength = <MXS_DRIVE_8mA>;
671					fsl,voltage = <MXS_VOLTAGE_HIGH>;
672					fsl,pull-up = <MXS_PULL_ENABLE>;
673				};
674
675				saif0_pins_a: saif0@0 {
676					reg = <0>;
677					fsl,pinmux-ids = <
678						MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
679						MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
680						MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
681						MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
682					>;
683					fsl,drive-strength = <MXS_DRIVE_12mA>;
684					fsl,voltage = <MXS_VOLTAGE_HIGH>;
685					fsl,pull-up = <MXS_PULL_ENABLE>;
686				};
687
688				saif0_pins_b: saif0@1 {
689					reg = <1>;
690					fsl,pinmux-ids = <
691						MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
692						MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
693						MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
694					>;
695					fsl,drive-strength = <MXS_DRIVE_12mA>;
696					fsl,voltage = <MXS_VOLTAGE_HIGH>;
697					fsl,pull-up = <MXS_PULL_ENABLE>;
698				};
699
700				saif1_pins_a: saif1@0 {
701					reg = <0>;
702					fsl,pinmux-ids = <
703						MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
704					>;
705					fsl,drive-strength = <MXS_DRIVE_12mA>;
706					fsl,voltage = <MXS_VOLTAGE_HIGH>;
707					fsl,pull-up = <MXS_PULL_ENABLE>;
708				};
709
710				pwm0_pins_a: pwm0@0 {
711					reg = <0>;
712					fsl,pinmux-ids = <
713						MX28_PAD_PWM0__PWM_0
714					>;
715					fsl,drive-strength = <MXS_DRIVE_4mA>;
716					fsl,voltage = <MXS_VOLTAGE_HIGH>;
717					fsl,pull-up = <MXS_PULL_DISABLE>;
718				};
719
720				pwm2_pins_a: pwm2@0 {
721					reg = <0>;
722					fsl,pinmux-ids = <
723						MX28_PAD_PWM2__PWM_2
724					>;
725					fsl,drive-strength = <MXS_DRIVE_4mA>;
726					fsl,voltage = <MXS_VOLTAGE_HIGH>;
727					fsl,pull-up = <MXS_PULL_DISABLE>;
728				};
729
730				pwm3_pins_a: pwm3@0 {
731					reg = <0>;
732					fsl,pinmux-ids = <
733						MX28_PAD_PWM3__PWM_3
734					>;
735					fsl,drive-strength = <MXS_DRIVE_4mA>;
736					fsl,voltage = <MXS_VOLTAGE_HIGH>;
737					fsl,pull-up = <MXS_PULL_DISABLE>;
738				};
739
740				pwm3_pins_b: pwm3@1 {
741					reg = <1>;
742					fsl,pinmux-ids = <
743						MX28_PAD_SAIF0_MCLK__PWM_3
744					>;
745					fsl,drive-strength = <MXS_DRIVE_4mA>;
746					fsl,voltage = <MXS_VOLTAGE_HIGH>;
747					fsl,pull-up = <MXS_PULL_DISABLE>;
748				};
749
750				pwm4_pins_a: pwm4@0 {
751					reg = <0>;
752					fsl,pinmux-ids = <
753						MX28_PAD_PWM4__PWM_4
754					>;
755					fsl,drive-strength = <MXS_DRIVE_4mA>;
756					fsl,voltage = <MXS_VOLTAGE_HIGH>;
757					fsl,pull-up = <MXS_PULL_DISABLE>;
758				};
759
760				lcdif_24bit_pins_a: lcdif-24bit@0 {
761					reg = <0>;
762					fsl,pinmux-ids = <
763						MX28_PAD_LCD_D00__LCD_D0
764						MX28_PAD_LCD_D01__LCD_D1
765						MX28_PAD_LCD_D02__LCD_D2
766						MX28_PAD_LCD_D03__LCD_D3
767						MX28_PAD_LCD_D04__LCD_D4
768						MX28_PAD_LCD_D05__LCD_D5
769						MX28_PAD_LCD_D06__LCD_D6
770						MX28_PAD_LCD_D07__LCD_D7
771						MX28_PAD_LCD_D08__LCD_D8
772						MX28_PAD_LCD_D09__LCD_D9
773						MX28_PAD_LCD_D10__LCD_D10
774						MX28_PAD_LCD_D11__LCD_D11
775						MX28_PAD_LCD_D12__LCD_D12
776						MX28_PAD_LCD_D13__LCD_D13
777						MX28_PAD_LCD_D14__LCD_D14
778						MX28_PAD_LCD_D15__LCD_D15
779						MX28_PAD_LCD_D16__LCD_D16
780						MX28_PAD_LCD_D17__LCD_D17
781						MX28_PAD_LCD_D18__LCD_D18
782						MX28_PAD_LCD_D19__LCD_D19
783						MX28_PAD_LCD_D20__LCD_D20
784						MX28_PAD_LCD_D21__LCD_D21
785						MX28_PAD_LCD_D22__LCD_D22
786						MX28_PAD_LCD_D23__LCD_D23
787					>;
788					fsl,drive-strength = <MXS_DRIVE_4mA>;
789					fsl,voltage = <MXS_VOLTAGE_HIGH>;
790					fsl,pull-up = <MXS_PULL_DISABLE>;
791				};
792
793				lcdif_18bit_pins_a: lcdif-18bit@0 {
794					reg = <0>;
795					fsl,pinmux-ids = <
796						MX28_PAD_LCD_D00__LCD_D0
797						MX28_PAD_LCD_D01__LCD_D1
798						MX28_PAD_LCD_D02__LCD_D2
799						MX28_PAD_LCD_D03__LCD_D3
800						MX28_PAD_LCD_D04__LCD_D4
801						MX28_PAD_LCD_D05__LCD_D5
802						MX28_PAD_LCD_D06__LCD_D6
803						MX28_PAD_LCD_D07__LCD_D7
804						MX28_PAD_LCD_D08__LCD_D8
805						MX28_PAD_LCD_D09__LCD_D9
806						MX28_PAD_LCD_D10__LCD_D10
807						MX28_PAD_LCD_D11__LCD_D11
808						MX28_PAD_LCD_D12__LCD_D12
809						MX28_PAD_LCD_D13__LCD_D13
810						MX28_PAD_LCD_D14__LCD_D14
811						MX28_PAD_LCD_D15__LCD_D15
812						MX28_PAD_LCD_D16__LCD_D16
813						MX28_PAD_LCD_D17__LCD_D17
814					>;
815					fsl,drive-strength = <MXS_DRIVE_4mA>;
816					fsl,voltage = <MXS_VOLTAGE_HIGH>;
817					fsl,pull-up = <MXS_PULL_DISABLE>;
818				};
819
820				lcdif_16bit_pins_a: lcdif-16bit@0 {
821					reg = <0>;
822					fsl,pinmux-ids = <
823						MX28_PAD_LCD_D00__LCD_D0
824						MX28_PAD_LCD_D01__LCD_D1
825						MX28_PAD_LCD_D02__LCD_D2
826						MX28_PAD_LCD_D03__LCD_D3
827						MX28_PAD_LCD_D04__LCD_D4
828						MX28_PAD_LCD_D05__LCD_D5
829						MX28_PAD_LCD_D06__LCD_D6
830						MX28_PAD_LCD_D07__LCD_D7
831						MX28_PAD_LCD_D08__LCD_D8
832						MX28_PAD_LCD_D09__LCD_D9
833						MX28_PAD_LCD_D10__LCD_D10
834						MX28_PAD_LCD_D11__LCD_D11
835						MX28_PAD_LCD_D12__LCD_D12
836						MX28_PAD_LCD_D13__LCD_D13
837						MX28_PAD_LCD_D14__LCD_D14
838						MX28_PAD_LCD_D15__LCD_D15
839					>;
840					fsl,drive-strength = <MXS_DRIVE_4mA>;
841					fsl,voltage = <MXS_VOLTAGE_HIGH>;
842					fsl,pull-up = <MXS_PULL_DISABLE>;
843				};
844
845				lcdif_sync_pins_a: lcdif-sync@0 {
846					reg = <0>;
847					fsl,pinmux-ids = <
848						MX28_PAD_LCD_RS__LCD_DOTCLK
849						MX28_PAD_LCD_CS__LCD_ENABLE
850						MX28_PAD_LCD_RD_E__LCD_VSYNC
851						MX28_PAD_LCD_WR_RWN__LCD_HSYNC
852					>;
853					fsl,drive-strength = <MXS_DRIVE_4mA>;
854					fsl,voltage = <MXS_VOLTAGE_HIGH>;
855					fsl,pull-up = <MXS_PULL_DISABLE>;
856				};
857
858				can0_pins_a: can0@0 {
859					reg = <0>;
860					fsl,pinmux-ids = <
861						MX28_PAD_GPMI_RDY2__CAN0_TX
862						MX28_PAD_GPMI_RDY3__CAN0_RX
863					>;
864					fsl,drive-strength = <MXS_DRIVE_4mA>;
865					fsl,voltage = <MXS_VOLTAGE_HIGH>;
866					fsl,pull-up = <MXS_PULL_DISABLE>;
867				};
868
869				can1_pins_a: can1@0 {
870					reg = <0>;
871					fsl,pinmux-ids = <
872						MX28_PAD_GPMI_CE2N__CAN1_TX
873						MX28_PAD_GPMI_CE3N__CAN1_RX
874					>;
875					fsl,drive-strength = <MXS_DRIVE_4mA>;
876					fsl,voltage = <MXS_VOLTAGE_HIGH>;
877					fsl,pull-up = <MXS_PULL_DISABLE>;
878				};
879
880				spi2_pins_a: spi2@0 {
881					reg = <0>;
882					fsl,pinmux-ids = <
883						MX28_PAD_SSP2_SCK__SSP2_SCK
884						MX28_PAD_SSP2_MOSI__SSP2_CMD
885						MX28_PAD_SSP2_MISO__SSP2_D0
886						MX28_PAD_SSP2_SS0__SSP2_D3
887					>;
888					fsl,drive-strength = <MXS_DRIVE_8mA>;
889					fsl,voltage = <MXS_VOLTAGE_HIGH>;
890					fsl,pull-up = <MXS_PULL_ENABLE>;
891				};
892
893				spi3_pins_a: spi3@0 {
894					reg = <0>;
895					fsl,pinmux-ids = <
896						MX28_PAD_AUART2_RX__SSP3_D4
897						MX28_PAD_AUART2_TX__SSP3_D5
898						MX28_PAD_SSP3_SCK__SSP3_SCK
899						MX28_PAD_SSP3_MOSI__SSP3_CMD
900						MX28_PAD_SSP3_MISO__SSP3_D0
901						MX28_PAD_SSP3_SS0__SSP3_D3
902					>;
903					fsl,drive-strength = <MXS_DRIVE_8mA>;
904					fsl,voltage = <MXS_VOLTAGE_HIGH>;
905					fsl,pull-up = <MXS_PULL_DISABLE>;
906				};
907
908				spi3_pins_b: spi3@1 {
909					reg = <1>;
910					fsl,pinmux-ids = <
911						MX28_PAD_SSP3_SCK__SSP3_SCK
912						MX28_PAD_SSP3_MOSI__SSP3_CMD
913						MX28_PAD_SSP3_MISO__SSP3_D0
914						MX28_PAD_SSP3_SS0__SSP3_D3
915					>;
916					fsl,drive-strength = <MXS_DRIVE_8mA>;
917					fsl,voltage = <MXS_VOLTAGE_HIGH>;
918					fsl,pull-up = <MXS_PULL_ENABLE>;
919				};
920
921				usb0_pins_a: usb0@0 {
922					reg = <0>;
923					fsl,pinmux-ids = <
924						MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
925					>;
926					fsl,drive-strength = <MXS_DRIVE_12mA>;
927					fsl,voltage = <MXS_VOLTAGE_HIGH>;
928					fsl,pull-up = <MXS_PULL_DISABLE>;
929				};
930
931				usb0_pins_b: usb0@1 {
932					reg = <1>;
933					fsl,pinmux-ids = <
934						MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
935					>;
936					fsl,drive-strength = <MXS_DRIVE_12mA>;
937					fsl,voltage = <MXS_VOLTAGE_HIGH>;
938					fsl,pull-up = <MXS_PULL_DISABLE>;
939				};
940
941				usb1_pins_a: usb1@0 {
942					reg = <0>;
943					fsl,pinmux-ids = <
944						MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
945					>;
946					fsl,drive-strength = <MXS_DRIVE_12mA>;
947					fsl,voltage = <MXS_VOLTAGE_HIGH>;
948					fsl,pull-up = <MXS_PULL_DISABLE>;
949				};
950
951				usb0_id_pins_a: usb0id@0 {
952					reg = <0>;
953					fsl,pinmux-ids = <
954						MX28_PAD_AUART1_RTS__USB0_ID
955					>;
956					fsl,drive-strength = <MXS_DRIVE_12mA>;
957					fsl,voltage = <MXS_VOLTAGE_HIGH>;
958					fsl,pull-up = <MXS_PULL_ENABLE>;
959				};
960
961				usb0_id_pins_b: usb0id1@0 {
962					reg = <0>;
963					fsl,pinmux-ids = <
964						MX28_PAD_PWM2__USB0_ID
965					>;
966					fsl,drive-strength = <MXS_DRIVE_12mA>;
967					fsl,voltage = <MXS_VOLTAGE_HIGH>;
968					fsl,pull-up = <MXS_PULL_ENABLE>;
969				};
970
971			};
972
973			digctl: digctl@8001c000 {
974				compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
975				reg = <0x8001c000 0x2000>;
976				interrupts = <89>;
977				status = "disabled";
978			};
979
980			etm: etm@80022000 {
981				reg = <0x80022000 0x2000>;
982				status = "disabled";
983			};
984
985			dma_apbx: dma-apbx@80024000 {
986				compatible = "fsl,imx28-dma-apbx";
987				reg = <0x80024000 0x2000>;
988				interrupts = <78 79 66 0
989					      80 81 68 69
990					      70 71 72 73
991					      74 75 76 77>;
992				interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
993						  "saif0", "saif1", "i2c0", "i2c1",
994						  "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
995						  "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
996				#dma-cells = <1>;
997				dma-channels = <16>;
998				clocks = <&clks 26>;
999			};
1000
1001			dcp: dcp@80028000 {
1002				compatible = "fsl,imx28-dcp", "fsl,imx23-dcp";
1003				reg = <0x80028000 0x2000>;
1004				interrupts = <52 53 54>;
1005				status = "okay";
1006			};
1007
1008			pxp: pxp@8002a000 {
1009				reg = <0x8002a000 0x2000>;
1010				interrupts = <39>;
1011				status = "disabled";
1012			};
1013
1014			ocotp: ocotp@8002c000 {
1015				compatible = "fsl,imx28-ocotp", "fsl,ocotp";
1016				#address-cells = <1>;
1017				#size-cells = <1>;
1018				reg = <0x8002c000 0x2000>;
1019				clocks = <&clks 25>;
1020			};
1021
1022			axi-ahb@8002e000 {
1023				reg = <0x8002e000 0x2000>;
1024				status = "disabled";
1025			};
1026
1027			lcdif: lcdif@80030000 {
1028				compatible = "fsl,imx28-lcdif";
1029				reg = <0x80030000 0x2000>;
1030				interrupts = <38>;
1031				clocks = <&clks 55>;
1032				dmas = <&dma_apbh 13>;
1033				dma-names = "rx";
1034				status = "disabled";
1035			};
1036
1037			can0: can@80032000 {
1038				compatible = "fsl,imx28-flexcan";
1039				reg = <0x80032000 0x2000>;
1040				interrupts = <8>;
1041				clocks = <&clks 58>, <&clks 58>;
1042				clock-names = "ipg", "per";
1043				status = "disabled";
1044			};
1045
1046			can1: can@80034000 {
1047				compatible = "fsl,imx28-flexcan";
1048				reg = <0x80034000 0x2000>;
1049				interrupts = <9>;
1050				clocks = <&clks 59>, <&clks 59>;
1051				clock-names = "ipg", "per";
1052				status = "disabled";
1053			};
1054
1055			simdbg: simdbg@8003c000 {
1056				reg = <0x8003c000 0x200>;
1057				status = "disabled";
1058			};
1059
1060			simgpmisel: simgpmisel@8003c200 {
1061				reg = <0x8003c200 0x100>;
1062				status = "disabled";
1063			};
1064
1065			simsspsel: simsspsel@8003c300 {
1066				reg = <0x8003c300 0x100>;
1067				status = "disabled";
1068			};
1069
1070			simmemsel: simmemsel@8003c400 {
1071				reg = <0x8003c400 0x100>;
1072				status = "disabled";
1073			};
1074
1075			gpiomon: gpiomon@8003c500 {
1076				reg = <0x8003c500 0x100>;
1077				status = "disabled";
1078			};
1079
1080			simenet: simenet@8003c700 {
1081				reg = <0x8003c700 0x100>;
1082				status = "disabled";
1083			};
1084
1085			armjtag: armjtag@8003c800 {
1086				reg = <0x8003c800 0x100>;
1087				status = "disabled";
1088			};
1089		};
1090
1091		apbx@80040000 {
1092			compatible = "simple-bus";
1093			#address-cells = <1>;
1094			#size-cells = <1>;
1095			reg = <0x80040000 0x40000>;
1096			ranges;
1097
1098			clks: clkctrl@80040000 {
1099				compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
1100				reg = <0x80040000 0x2000>;
1101				#clock-cells = <1>;
1102			};
1103
1104			saif0: saif@80042000 {
1105				#sound-dai-cells = <0>;
1106				compatible = "fsl,imx28-saif";
1107				reg = <0x80042000 0x2000>;
1108				interrupts = <59>;
1109				#clock-cells = <0>;
1110				clocks = <&clks 53>;
1111				dmas = <&dma_apbx 4>;
1112				dma-names = "rx-tx";
1113				status = "disabled";
1114			};
1115
1116			power: power@80044000 {
1117				reg = <0x80044000 0x2000>;
1118				status = "disabled";
1119			};
1120
1121			saif1: saif@80046000 {
1122				#sound-dai-cells = <0>;
1123				compatible = "fsl,imx28-saif";
1124				reg = <0x80046000 0x2000>;
1125				interrupts = <58>;
1126				clocks = <&clks 54>;
1127				dmas = <&dma_apbx 5>;
1128				dma-names = "rx-tx";
1129				status = "disabled";
1130			};
1131
1132			lradc: lradc@80050000 {
1133				compatible = "fsl,imx28-lradc";
1134				reg = <0x80050000 0x2000>;
1135				interrupts = <10 14 15 16 17 18 19
1136						20 21 22 23 24 25>;
1137				status = "disabled";
1138				clocks = <&clks 41>;
1139				#io-channel-cells = <1>;
1140			};
1141
1142			spdif: spdif@80054000 {
1143				reg = <0x80054000 0x2000>;
1144				interrupts = <45>;
1145				dmas = <&dma_apbx 2>;
1146				dma-names = "tx";
1147				status = "disabled";
1148			};
1149
1150			mxs_rtc: rtc@80056000 {
1151				compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
1152				reg = <0x80056000 0x2000>;
1153				interrupts = <29>;
1154			};
1155
1156			i2c0: i2c@80058000 {
1157				#address-cells = <1>;
1158				#size-cells = <0>;
1159				compatible = "fsl,imx28-i2c";
1160				reg = <0x80058000 0x2000>;
1161				interrupts = <111>;
1162				clock-frequency = <100000>;
1163				dmas = <&dma_apbx 6>;
1164				dma-names = "rx-tx";
1165				status = "disabled";
1166			};
1167
1168			i2c1: i2c@8005a000 {
1169				#address-cells = <1>;
1170				#size-cells = <0>;
1171				compatible = "fsl,imx28-i2c";
1172				reg = <0x8005a000 0x2000>;
1173				interrupts = <110>;
1174				clock-frequency = <100000>;
1175				dmas = <&dma_apbx 7>;
1176				dma-names = "rx-tx";
1177				status = "disabled";
1178			};
1179
1180			pwm: pwm@80064000 {
1181				compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
1182				reg = <0x80064000 0x2000>;
1183				clocks = <&clks 44>;
1184				#pwm-cells = <2>;
1185				fsl,pwm-number = <8>;
1186				status = "disabled";
1187			};
1188
1189			timer: timrot@80068000 {
1190				compatible = "fsl,imx28-timrot", "fsl,timrot";
1191				reg = <0x80068000 0x2000>;
1192				interrupts = <48 49 50 51>;
1193				clocks = <&clks 26>;
1194			};
1195
1196			auart0: serial@8006a000 {
1197				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1198				reg = <0x8006a000 0x2000>;
1199				interrupts = <112>;
1200				dmas = <&dma_apbx 8>, <&dma_apbx 9>;
1201				dma-names = "rx", "tx";
1202				clocks = <&clks 45>;
1203				status = "disabled";
1204			};
1205
1206			auart1: serial@8006c000 {
1207				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1208				reg = <0x8006c000 0x2000>;
1209				interrupts = <113>;
1210				dmas = <&dma_apbx 10>, <&dma_apbx 11>;
1211				dma-names = "rx", "tx";
1212				clocks = <&clks 45>;
1213				status = "disabled";
1214			};
1215
1216			auart2: serial@8006e000 {
1217				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1218				reg = <0x8006e000 0x2000>;
1219				interrupts = <114>;
1220				dmas = <&dma_apbx 12>, <&dma_apbx 13>;
1221				dma-names = "rx", "tx";
1222				clocks = <&clks 45>;
1223				status = "disabled";
1224			};
1225
1226			auart3: serial@80070000 {
1227				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1228				reg = <0x80070000 0x2000>;
1229				interrupts = <115>;
1230				dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1231				dma-names = "rx", "tx";
1232				clocks = <&clks 45>;
1233				status = "disabled";
1234			};
1235
1236			auart4: serial@80072000 {
1237				compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1238				reg = <0x80072000 0x2000>;
1239				interrupts = <116>;
1240				dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1241				dma-names = "rx", "tx";
1242				clocks = <&clks 45>;
1243				status = "disabled";
1244			};
1245
1246			duart: serial@80074000 {
1247				compatible = "arm,pl011", "arm,primecell";
1248				reg = <0x80074000 0x1000>;
1249				interrupts = <47>;
1250				clocks = <&clks 45>, <&clks 26>;
1251				clock-names = "uart", "apb_pclk";
1252				status = "disabled";
1253			};
1254
1255			usbphy0: usbphy@8007c000 {
1256				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1257				reg = <0x8007c000 0x2000>;
1258				clocks = <&clks 62>;
1259				status = "disabled";
1260			};
1261
1262			usbphy1: usbphy@8007e000 {
1263				compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1264				reg = <0x8007e000 0x2000>;
1265				clocks = <&clks 63>;
1266				status = "disabled";
1267			};
1268		};
1269	};
1270
1271	ahb@80080000 {
1272		compatible = "simple-bus";
1273		#address-cells = <1>;
1274		#size-cells = <1>;
1275		reg = <0x80080000 0x80000>;
1276		ranges;
1277
1278		usb0: usb@80080000 {
1279			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1280			reg = <0x80080000 0x10000>;
1281			interrupts = <93>;
1282			clocks = <&clks 60>;
1283			fsl,usbphy = <&usbphy0>;
1284			status = "disabled";
1285		};
1286
1287		usb1: usb@80090000 {
1288			compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1289			reg = <0x80090000 0x10000>;
1290			interrupts = <92>;
1291			clocks = <&clks 61>;
1292			fsl,usbphy = <&usbphy1>;
1293			dr_mode = "host";
1294			status = "disabled";
1295		};
1296
1297		dflpt: dflpt@800c0000 {
1298			reg = <0x800c0000 0x10000>;
1299			status = "disabled";
1300		};
1301
1302		mac0: ethernet@800f0000 {
1303			compatible = "fsl,imx28-fec";
1304			reg = <0x800f0000 0x4000>;
1305			interrupts = <101>;
1306			clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1307			clock-names = "ipg", "ahb", "enet_out";
1308			status = "disabled";
1309		};
1310
1311		mac1: ethernet@800f4000 {
1312			compatible = "fsl,imx28-fec";
1313			reg = <0x800f4000 0x4000>;
1314			interrupts = <102>;
1315			clocks = <&clks 57>, <&clks 57>;
1316			clock-names = "ipg", "ahb";
1317			status = "disabled";
1318		};
1319
1320		etn_switch: switch@800f8000 {
1321			reg = <0x800f8000 0x8000>;
1322			status = "disabled";
1323		};
1324	};
1325
1326	iio-hwmon {
1327		compatible = "iio-hwmon";
1328		io-channels = <&lradc 8>;
1329	};
1330};
1331