1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright 2014 Iain Paton <ipaton0@gmail.com> 4 */ 5 6/dts-v1/; 7#include "imx6dl.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 model = "RIoTboard i.MX6S"; 12 compatible = "riot,imx6s-riotboard", "fsl,imx6dl"; 13 14 memory@10000000 { 15 device_type = "memory"; 16 reg = <0x10000000 0x40000000>; 17 }; 18 19 chosen { 20 stdout-path = "serial1:115200n8"; 21 }; 22 23 leds { 24 compatible = "gpio-leds"; 25 pinctrl-names = "default"; 26 pinctrl-0 = <&pinctrl_led>; 27 28 led0: user1 { 29 label = "user1"; 30 gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; 31 default-state = "on"; 32 linux,default-trigger = "heartbeat"; 33 }; 34 35 led1: user2 { 36 label = "user2"; 37 gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; 38 default-state = "off"; 39 }; 40 }; 41 42 sound { 43 compatible = "fsl,imx-audio-sgtl5000"; 44 model = "imx6-riotboard-sgtl5000"; 45 ssi-controller = <&ssi1>; 46 audio-codec = <&codec>; 47 audio-routing = 48 "MIC_IN", "Mic Jack", 49 "Mic Jack", "Mic Bias", 50 "Headphone Jack", "HP_OUT"; 51 mux-int-port = <1>; 52 mux-ext-port = <3>; 53 }; 54 55 reg_2p5v: regulator-2p5v { 56 compatible = "regulator-fixed"; 57 regulator-name = "2P5V"; 58 regulator-min-microvolt = <2500000>; 59 regulator-max-microvolt = <2500000>; 60 }; 61 62 reg_3p3v: regulator-3p3v { 63 compatible = "regulator-fixed"; 64 regulator-name = "3P3V"; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 }; 68 69 reg_usb_otg_vbus: regulator-usbotgvbus { 70 compatible = "regulator-fixed"; 71 regulator-name = "usb_otg_vbus"; 72 regulator-min-microvolt = <5000000>; 73 regulator-max-microvolt = <5000000>; 74 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; 75 }; 76}; 77 78&audmux { 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_audmux>; 81 status = "okay"; 82}; 83 84&clks { 85 fsl,pmic-stby-poweroff; 86}; 87 88&fec { 89 pinctrl-names = "default"; 90 pinctrl-0 = <&pinctrl_enet>; 91 phy-mode = "rgmii-id"; 92 phy-handle = <&rgmii_phy>; 93 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 94 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 95 fsl,err006687-workaround-present; 96 status = "okay"; 97 98 mdio { 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 /* Atheros AR8035 PHY */ 103 rgmii_phy: ethernet-phy@4 { 104 reg = <4>; 105 interrupts-extended = <&gpio1 28 IRQ_TYPE_LEVEL_LOW>; 106 reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; 107 reset-assert-us = <10000>; 108 reset-deassert-us = <1000>; 109 }; 110 }; 111}; 112 113&gpio1 { 114 gpio-line-names = 115 "", "", "SD2_WP", "", "SD2_CD", "I2C3_SCL", 116 "I2C3_SDA", "I2C4_SCL", 117 "I2C4_SDA", "", "", "", "", "", "", "", 118 "", "PWM3", "", "", "", "", "", "", 119 "", "", "", "", "", "", "", ""; 120}; 121 122&gpio3 { 123 gpio-line-names = 124 "", "", "", "", "", "", "", "", 125 "", "", "", "", "", "", "", "", 126 "", "", "", "", "", "", "USB_OTG_VBUS", "", 127 "UART3_TXD", "UART3_RXD", "", "", "EIM_D28", "", "", ""; 128}; 129 130&gpio4 { 131 gpio-line-names = 132 "", "", "", "", "", "", "UART4_TXD", "UART4_RXD", 133 "UART5_TXD", "UART5_RXD", "", "", "", "", "", "", 134 "GPIO4_16", "GPIO4_17", "GPIO4_18", "GPIO4_19", "", 135 "CSPI3_CLK", "CSPI3_MOSI", "CSPI3_MISO", 136 "CSPI3_CS0", "CSPI3_CS1", "GPIO4_26", "GPIO4_27", 137 "CSPI3_RDY", "PWM1", "PWM2", "GPIO4_31"; 138}; 139 140&gpio5 { 141 gpio-line-names = 142 "", "", "EIM_A25", "", "", "GPIO5_05", "GPIO5_06", 143 "GPIO5_07", 144 "GPIO5_08", "CSPI2_CS1", "CSPI2_MOSI", "CSPI2_MISO", 145 "CSPI2_CS0", "CSPI2_CLK", "", "", 146 "", "", "", "", "", "", "", "", 147 "", "", "", "", "", "", "", ""; 148}; 149 150&gpio7 { 151 gpio-line-names = 152 "SD3_CD", "SD3_WP", "", "", "", "", "", "", 153 "", "", "", "", "", "", "", "", 154 "", "", "", "", "", "", "", "", 155 "", "", "", "", "", "", "", ""; 156}; 157 158&hdmi { 159 ddc-i2c-bus = <&i2c2>; 160 status = "okay"; 161}; 162 163&i2c1 { 164 clock-frequency = <100000>; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_i2c1>; 167 status = "okay"; 168 169 codec: sgtl5000@a { 170 compatible = "fsl,sgtl5000"; 171 reg = <0x0a>; 172 clocks = <&clks IMX6QDL_CLK_CKO>; 173 VDDA-supply = <®_2p5v>; 174 VDDIO-supply = <®_3p3v>; 175 }; 176 177 pmic: pf0100@8 { 178 compatible = "fsl,pfuze100"; 179 reg = <0x08>; 180 interrupt-parent = <&gpio5>; 181 interrupts = <16 8>; 182 fsl,pmic-stby-poweroff; 183 184 regulators { 185 reg_vddcore: sw1ab { /* VDDARM_IN */ 186 regulator-min-microvolt = <300000>; 187 regulator-max-microvolt = <1875000>; 188 regulator-always-on; 189 }; 190 191 reg_vddsoc: sw1c { /* VDDSOC_IN */ 192 regulator-min-microvolt = <300000>; 193 regulator-max-microvolt = <1875000>; 194 regulator-always-on; 195 }; 196 197 reg_gen_3v3: sw2 { /* VDDHIGH_IN */ 198 regulator-min-microvolt = <800000>; 199 regulator-max-microvolt = <3300000>; 200 regulator-always-on; 201 }; 202 203 reg_ddr_1v5a: sw3a { /* NVCC_DRAM, NVCC_RGMII */ 204 regulator-min-microvolt = <400000>; 205 regulator-max-microvolt = <1975000>; 206 regulator-always-on; 207 }; 208 209 reg_ddr_1v5b: sw3b { /* NVCC_DRAM, NVCC_RGMII */ 210 regulator-min-microvolt = <400000>; 211 regulator-max-microvolt = <1975000>; 212 regulator-always-on; 213 }; 214 215 reg_ddr_vtt: sw4 { /* MIPI conn */ 216 regulator-min-microvolt = <400000>; 217 regulator-max-microvolt = <1975000>; 218 regulator-always-on; 219 }; 220 221 reg_5v_600mA: swbst { /* not used */ 222 regulator-min-microvolt = <5000000>; 223 regulator-max-microvolt = <5150000>; 224 }; 225 226 reg_snvs_3v: vsnvs { /* VDD_SNVS_IN */ 227 regulator-min-microvolt = <1500000>; 228 regulator-max-microvolt = <3000000>; 229 regulator-always-on; 230 }; 231 232 vref_reg: vrefddr { /* VREF_DDR */ 233 regulator-boot-on; 234 regulator-always-on; 235 }; 236 237 reg_vgen1_1v5: vgen1 { /* not used */ 238 regulator-min-microvolt = <800000>; 239 regulator-max-microvolt = <1550000>; 240 }; 241 242 reg_vgen2_1v2_eth: vgen2 { /* pcie ? */ 243 regulator-min-microvolt = <800000>; 244 regulator-max-microvolt = <1550000>; 245 regulator-always-on; 246 }; 247 248 reg_vgen3_2v8: vgen3 { /* not used */ 249 regulator-min-microvolt = <1800000>; 250 regulator-max-microvolt = <3300000>; 251 }; 252 reg_vgen4_1v8: vgen4 { /* NVCC_SD3 */ 253 regulator-min-microvolt = <1800000>; 254 regulator-max-microvolt = <3300000>; 255 regulator-always-on; 256 }; 257 258 reg_vgen5_2v5_sgtl: vgen5 { /* Pwr LED & 5V0_delayed enable */ 259 regulator-min-microvolt = <1800000>; 260 regulator-max-microvolt = <3300000>; 261 regulator-always-on; 262 }; 263 264 reg_vgen6_3v3: vgen6 { /* #V#_DELAYED enable, MIPI */ 265 regulator-min-microvolt = <1800000>; 266 regulator-max-microvolt = <3300000>; 267 regulator-always-on; 268 }; 269 }; 270 }; 271}; 272 273&i2c2 { 274 clock-frequency = <100000>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_i2c2>; 277 status = "okay"; 278}; 279 280&i2c4 { 281 clock-frequency = <100000>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_i2c4>; 284 clocks = <&clks 116>; 285 status = "okay"; 286}; 287 288&pwm1 { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_pwm1>; 291 status = "okay"; 292}; 293 294&pwm2 { 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_pwm2>; 297 status = "okay"; 298}; 299 300&pwm3 { 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_pwm3>; 303 status = "okay"; 304}; 305 306&pwm4 { 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_pwm4>; 309 status = "okay"; 310}; 311 312&ssi1 { 313 status = "okay"; 314}; 315 316&uart1 { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_uart1>; 319 status = "okay"; 320}; 321 322&uart2 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_uart2>; 325 status = "okay"; 326}; 327 328&uart3 { 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_uart3>; 331 status = "okay"; 332}; 333 334&uart4 { 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_uart4>; 337 status = "okay"; 338}; 339 340&uart5 { 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_uart5>; 343 status = "okay"; 344}; 345 346&usbh1 { 347 dr_mode = "host"; 348 disable-over-current; 349 status = "okay"; 350}; 351 352&usbotg { 353 vbus-supply = <®_usb_otg_vbus>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_usbotg>; 356 disable-over-current; 357 dr_mode = "otg"; 358 status = "okay"; 359}; 360 361&usdhc2 { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_usdhc2>; 364 cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; 365 wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 366 vmmc-supply = <®_3p3v>; 367 status = "okay"; 368}; 369 370&usdhc3 { 371 pinctrl-names = "default"; 372 pinctrl-0 = <&pinctrl_usdhc3>; 373 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 374 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 375 vmmc-supply = <®_3p3v>; 376 status = "okay"; 377}; 378 379&usdhc4 { 380 pinctrl-names = "default"; 381 pinctrl-0 = <&pinctrl_usdhc4>; 382 vmmc-supply = <®_3p3v>; 383 non-removable; 384 status = "okay"; 385}; 386 387&iomuxc { 388 pinctrl-names = "default"; 389 390 imx6-riotboard { 391 pinctrl_audmux: audmuxgrp { 392 fsl,pins = < 393 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 394 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 395 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 396 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 397 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ 398 >; 399 }; 400 401 pinctrl_ecspi1: ecspi1grp { 402 fsl,pins = < 403 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 404 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 405 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 406 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x000b1 /* CS0 */ 407 >; 408 }; 409 410 pinctrl_ecspi2: ecspi2grp { 411 fsl,pins = < 412 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x000b1 /* CS1 */ 413 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1 414 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1 415 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1 /* CS0 */ 416 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1 417 >; 418 }; 419 420 pinctrl_ecspi3: ecspi3grp { 421 fsl,pins = < 422 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 423 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 424 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 425 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1 /* CS0 */ 426 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x000b1 /* CS1 */ 427 >; 428 }; 429 430 pinctrl_enet: enetgrp { 431 fsl,pins = < 432 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 433 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 434 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 435 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 436 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 437 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 438 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 439 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 440 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ 441 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ 442 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ 443 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ 444 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ 445 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ 446 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ 447 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ 448 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ 449 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */ 450 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 451 >; 452 }; 453 454 pinctrl_i2c1: i2c1grp { 455 fsl,pins = < 456 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 457 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 458 >; 459 }; 460 461 pinctrl_i2c2: i2c2grp { 462 fsl,pins = < 463 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 464 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 465 >; 466 }; 467 468 pinctrl_i2c3: i2c3grp { 469 fsl,pins = < 470 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 471 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 472 >; 473 }; 474 475 pinctrl_i2c4: i2c4grp { 476 fsl,pins = < 477 MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 478 MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 479 >; 480 }; 481 482 pinctrl_led: ledgrp { 483 fsl,pins = < 484 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */ 485 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */ 486 >; 487 }; 488 489 pinctrl_pwm1: pwm1grp { 490 fsl,pins = < 491 MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1 492 >; 493 }; 494 495 pinctrl_pwm2: pwm2grp { 496 fsl,pins = < 497 MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1 498 >; 499 }; 500 501 pinctrl_pwm3: pwm3grp { 502 fsl,pins = < 503 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 504 >; 505 }; 506 507 pinctrl_pwm4: pwm4grp { 508 fsl,pins = < 509 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 510 >; 511 }; 512 513 pinctrl_uart1: uart1grp { 514 fsl,pins = < 515 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 516 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 517 >; 518 }; 519 520 pinctrl_uart2: uart2grp { 521 fsl,pins = < 522 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 523 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 524 >; 525 }; 526 527 pinctrl_uart3: uart3grp { 528 fsl,pins = < 529 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 530 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 531 >; 532 }; 533 534 pinctrl_uart4: uart4grp { 535 fsl,pins = < 536 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 537 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 538 >; 539 }; 540 541 pinctrl_uart5: uart5grp { 542 fsl,pins = < 543 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 544 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 545 >; 546 }; 547 548 pinctrl_usbotg: usbotggrp { 549 fsl,pins = < 550 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 551 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ 552 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0 553 >; 554 }; 555 556 pinctrl_usdhc2: usdhc2grp { 557 fsl,pins = < 558 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 559 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 560 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 561 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 562 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 563 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 564 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */ 565 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */ 566 >; 567 }; 568 569 pinctrl_usdhc3: usdhc3grp { 570 fsl,pins = < 571 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 572 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 573 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 574 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 575 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 576 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 577 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */ 578 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */ 579 >; 580 }; 581 582 pinctrl_usdhc4: usdhc4grp { 583 fsl,pins = < 584 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 585 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 586 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 587 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 588 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 589 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 590 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */ 591 >; 592 }; 593 }; 594}; 595