1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 63 }; 64 65 cpus { 66 #address-cells = <0x2>; 67 #size-cells = <0x0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 next-level-cache = <&l2>; 75 clocks = <&scpi_dvfs 0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x1>; 82 enable-method = "psci"; 83 next-level-cache = <&l2>; 84 clocks = <&scpi_dvfs 0>; 85 }; 86 87 cpu2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 next-level-cache = <&l2>; 93 clocks = <&scpi_dvfs 0>; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 next-level-cache = <&l2>; 102 clocks = <&scpi_dvfs 0>; 103 }; 104 105 l2: l2-cache0 { 106 compatible = "cache"; 107 }; 108 }; 109 110 sm: secure-monitor { 111 compatible = "amlogic,meson-gxbb-sm"; 112 }; 113 114 efuse: efuse { 115 compatible = "amlogic,meson-gxbb-efuse"; 116 clocks = <&clkc CLKID_EFUSE>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 read-only; 120 secure-monitor = <&sm>; 121 }; 122 123 psci { 124 compatible = "arm,psci-1.0"; 125 method = "smc"; 126 }; 127 128 reserved-memory { 129 #address-cells = <2>; 130 #size-cells = <2>; 131 ranges; 132 133 /* 16 MiB reserved for Hardware ROM Firmware */ 134 hwrom_reserved: hwrom@0 { 135 reg = <0x0 0x0 0x0 0x1000000>; 136 no-map; 137 }; 138 139 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 140 secmon_reserved: secmon@5000000 { 141 reg = <0x0 0x05000000 0x0 0x300000>; 142 no-map; 143 }; 144 }; 145 146 scpi { 147 compatible = "arm,scpi-pre-1.0"; 148 mboxes = <&mailbox 1 &mailbox 2>; 149 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 150 151 scpi_clocks: clocks { 152 compatible = "arm,scpi-clocks"; 153 154 scpi_dvfs: clock-controller { 155 compatible = "arm,scpi-dvfs-clocks"; 156 #clock-cells = <1>; 157 clock-indices = <0>; 158 clock-output-names = "vcpu"; 159 }; 160 }; 161 162 scpi_sensors: sensors { 163 compatible = "amlogic,meson-gxbb-scpi-sensors"; 164 #thermal-sensor-cells = <1>; 165 }; 166 }; 167 168 soc { 169 compatible = "simple-bus"; 170 #address-cells = <2>; 171 #size-cells = <2>; 172 ranges; 173 174 ethmac: ethernet@ff3f0000 { 175 compatible = "amlogic,meson-axg-dwmac", 176 "snps,dwmac-3.70a", 177 "snps,dwmac"; 178 reg = <0x0 0xff3f0000 0x0 0x10000>, 179 <0x0 0xff634540 0x0 0x8>; 180 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 181 interrupt-names = "macirq"; 182 clocks = <&clkc CLKID_ETH>, 183 <&clkc CLKID_FCLK_DIV2>, 184 <&clkc CLKID_MPLL2>, 185 <&clkc CLKID_FCLK_DIV2>; 186 clock-names = "stmmaceth", "clkin0", "clkin1", 187 "timing-adjustment"; 188 rx-fifo-depth = <4096>; 189 tx-fifo-depth = <2048>; 190 status = "disabled"; 191 }; 192 193 pdm: audio-controller@ff632000 { 194 compatible = "amlogic,axg-pdm"; 195 reg = <0x0 0xff632000 0x0 0x34>; 196 #sound-dai-cells = <0>; 197 sound-name-prefix = "PDM"; 198 clocks = <&clkc_audio AUD_CLKID_PDM>, 199 <&clkc_audio AUD_CLKID_PDM_DCLK>, 200 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 201 clock-names = "pclk", "dclk", "sysclk"; 202 status = "disabled"; 203 }; 204 205 periphs: bus@ff634000 { 206 compatible = "simple-bus"; 207 reg = <0x0 0xff634000 0x0 0x2000>; 208 #address-cells = <2>; 209 #size-cells = <2>; 210 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 211 212 hwrng: rng@18 { 213 compatible = "amlogic,meson-rng"; 214 reg = <0x0 0x18 0x0 0x4>; 215 clocks = <&clkc CLKID_RNG0>; 216 clock-names = "core"; 217 }; 218 219 pinctrl_periphs: pinctrl@480 { 220 compatible = "amlogic,meson-axg-periphs-pinctrl"; 221 #address-cells = <2>; 222 #size-cells = <2>; 223 ranges; 224 225 gpio: bank@480 { 226 reg = <0x0 0x00480 0x0 0x40>, 227 <0x0 0x004e8 0x0 0x14>, 228 <0x0 0x00520 0x0 0x14>, 229 <0x0 0x00430 0x0 0x3c>; 230 reg-names = "mux", "pull", "pull-enable", "gpio"; 231 gpio-controller; 232 #gpio-cells = <2>; 233 gpio-ranges = <&pinctrl_periphs 0 0 86>; 234 }; 235 236 i2c0_pins: i2c0 { 237 mux { 238 groups = "i2c0_sck", 239 "i2c0_sda"; 240 function = "i2c0"; 241 bias-disable; 242 }; 243 }; 244 245 i2c1_x_pins: i2c1_x { 246 mux { 247 groups = "i2c1_sck_x", 248 "i2c1_sda_x"; 249 function = "i2c1"; 250 bias-disable; 251 }; 252 }; 253 254 i2c1_z_pins: i2c1_z { 255 mux { 256 groups = "i2c1_sck_z", 257 "i2c1_sda_z"; 258 function = "i2c1"; 259 bias-disable; 260 }; 261 }; 262 263 i2c2_a_pins: i2c2_a { 264 mux { 265 groups = "i2c2_sck_a", 266 "i2c2_sda_a"; 267 function = "i2c2"; 268 bias-disable; 269 }; 270 }; 271 272 i2c2_x_pins: i2c2_x { 273 mux { 274 groups = "i2c2_sck_x", 275 "i2c2_sda_x"; 276 function = "i2c2"; 277 bias-disable; 278 }; 279 }; 280 281 i2c3_a6_pins: i2c3_a6 { 282 mux { 283 groups = "i2c3_sda_a6", 284 "i2c3_sck_a7"; 285 function = "i2c3"; 286 bias-disable; 287 }; 288 }; 289 290 i2c3_a12_pins: i2c3_a12 { 291 mux { 292 groups = "i2c3_sda_a12", 293 "i2c3_sck_a13"; 294 function = "i2c3"; 295 bias-disable; 296 }; 297 }; 298 299 i2c3_a19_pins: i2c3_a19 { 300 mux { 301 groups = "i2c3_sda_a19", 302 "i2c3_sck_a20"; 303 function = "i2c3"; 304 bias-disable; 305 }; 306 }; 307 308 emmc_pins: emmc { 309 mux-0 { 310 groups = "emmc_nand_d0", 311 "emmc_nand_d1", 312 "emmc_nand_d2", 313 "emmc_nand_d3", 314 "emmc_nand_d4", 315 "emmc_nand_d5", 316 "emmc_nand_d6", 317 "emmc_nand_d7", 318 "emmc_cmd"; 319 function = "emmc"; 320 bias-pull-up; 321 }; 322 323 mux-1 { 324 groups = "emmc_clk"; 325 function = "emmc"; 326 bias-disable; 327 }; 328 }; 329 330 emmc_ds_pins: emmc_ds { 331 mux { 332 groups = "emmc_ds"; 333 function = "emmc"; 334 bias-pull-down; 335 }; 336 }; 337 338 emmc_clk_gate_pins: emmc_clk_gate { 339 mux { 340 groups = "BOOT_8"; 341 function = "gpio_periphs"; 342 bias-pull-down; 343 }; 344 }; 345 346 eth_rgmii_x_pins: eth-x-rgmii { 347 mux { 348 groups = "eth_mdio_x", 349 "eth_mdc_x", 350 "eth_rgmii_rx_clk_x", 351 "eth_rx_dv_x", 352 "eth_rxd0_x", 353 "eth_rxd1_x", 354 "eth_rxd2_rgmii", 355 "eth_rxd3_rgmii", 356 "eth_rgmii_tx_clk", 357 "eth_txen_x", 358 "eth_txd0_x", 359 "eth_txd1_x", 360 "eth_txd2_rgmii", 361 "eth_txd3_rgmii"; 362 function = "eth"; 363 bias-disable; 364 }; 365 }; 366 367 eth_rgmii_y_pins: eth-y-rgmii { 368 mux { 369 groups = "eth_mdio_y", 370 "eth_mdc_y", 371 "eth_rgmii_rx_clk_y", 372 "eth_rx_dv_y", 373 "eth_rxd0_y", 374 "eth_rxd1_y", 375 "eth_rxd2_rgmii", 376 "eth_rxd3_rgmii", 377 "eth_rgmii_tx_clk", 378 "eth_txen_y", 379 "eth_txd0_y", 380 "eth_txd1_y", 381 "eth_txd2_rgmii", 382 "eth_txd3_rgmii"; 383 function = "eth"; 384 bias-disable; 385 }; 386 }; 387 388 eth_rmii_x_pins: eth-x-rmii { 389 mux { 390 groups = "eth_mdio_x", 391 "eth_mdc_x", 392 "eth_rgmii_rx_clk_x", 393 "eth_rx_dv_x", 394 "eth_rxd0_x", 395 "eth_rxd1_x", 396 "eth_txen_x", 397 "eth_txd0_x", 398 "eth_txd1_x"; 399 function = "eth"; 400 bias-disable; 401 }; 402 }; 403 404 eth_rmii_y_pins: eth-y-rmii { 405 mux { 406 groups = "eth_mdio_y", 407 "eth_mdc_y", 408 "eth_rgmii_rx_clk_y", 409 "eth_rx_dv_y", 410 "eth_rxd0_y", 411 "eth_rxd1_y", 412 "eth_txen_y", 413 "eth_txd0_y", 414 "eth_txd1_y"; 415 function = "eth"; 416 bias-disable; 417 }; 418 }; 419 420 mclk_b_pins: mclk_b { 421 mux { 422 groups = "mclk_b"; 423 function = "mclk_b"; 424 bias-disable; 425 }; 426 }; 427 428 mclk_c_pins: mclk_c { 429 mux { 430 groups = "mclk_c"; 431 function = "mclk_c"; 432 bias-disable; 433 }; 434 }; 435 436 pdm_dclk_a14_pins: pdm_dclk_a14 { 437 mux { 438 groups = "pdm_dclk_a14"; 439 function = "pdm"; 440 bias-disable; 441 }; 442 }; 443 444 pdm_dclk_a19_pins: pdm_dclk_a19 { 445 mux { 446 groups = "pdm_dclk_a19"; 447 function = "pdm"; 448 bias-disable; 449 }; 450 }; 451 452 pdm_din0_pins: pdm_din0 { 453 mux { 454 groups = "pdm_din0"; 455 function = "pdm"; 456 bias-disable; 457 }; 458 }; 459 460 pdm_din1_pins: pdm_din1 { 461 mux { 462 groups = "pdm_din1"; 463 function = "pdm"; 464 bias-disable; 465 }; 466 }; 467 468 pdm_din2_pins: pdm_din2 { 469 mux { 470 groups = "pdm_din2"; 471 function = "pdm"; 472 bias-disable; 473 }; 474 }; 475 476 pdm_din3_pins: pdm_din3 { 477 mux { 478 groups = "pdm_din3"; 479 function = "pdm"; 480 bias-disable; 481 }; 482 }; 483 484 pwm_a_a_pins: pwm_a_a { 485 mux { 486 groups = "pwm_a_a"; 487 function = "pwm_a"; 488 bias-disable; 489 }; 490 }; 491 492 pwm_a_x18_pins: pwm_a_x18 { 493 mux { 494 groups = "pwm_a_x18"; 495 function = "pwm_a"; 496 bias-disable; 497 }; 498 }; 499 500 pwm_a_x20_pins: pwm_a_x20 { 501 mux { 502 groups = "pwm_a_x20"; 503 function = "pwm_a"; 504 bias-disable; 505 }; 506 }; 507 508 pwm_a_z_pins: pwm_a_z { 509 mux { 510 groups = "pwm_a_z"; 511 function = "pwm_a"; 512 bias-disable; 513 }; 514 }; 515 516 pwm_b_a_pins: pwm_b_a { 517 mux { 518 groups = "pwm_b_a"; 519 function = "pwm_b"; 520 bias-disable; 521 }; 522 }; 523 524 pwm_b_x_pins: pwm_b_x { 525 mux { 526 groups = "pwm_b_x"; 527 function = "pwm_b"; 528 bias-disable; 529 }; 530 }; 531 532 pwm_b_z_pins: pwm_b_z { 533 mux { 534 groups = "pwm_b_z"; 535 function = "pwm_b"; 536 bias-disable; 537 }; 538 }; 539 540 pwm_c_a_pins: pwm_c_a { 541 mux { 542 groups = "pwm_c_a"; 543 function = "pwm_c"; 544 bias-disable; 545 }; 546 }; 547 548 pwm_c_x10_pins: pwm_c_x10 { 549 mux { 550 groups = "pwm_c_x10"; 551 function = "pwm_c"; 552 bias-disable; 553 }; 554 }; 555 556 pwm_c_x17_pins: pwm_c_x17 { 557 mux { 558 groups = "pwm_c_x17"; 559 function = "pwm_c"; 560 bias-disable; 561 }; 562 }; 563 564 pwm_d_x11_pins: pwm_d_x11 { 565 mux { 566 groups = "pwm_d_x11"; 567 function = "pwm_d"; 568 bias-disable; 569 }; 570 }; 571 572 pwm_d_x16_pins: pwm_d_x16 { 573 mux { 574 groups = "pwm_d_x16"; 575 function = "pwm_d"; 576 bias-disable; 577 }; 578 }; 579 580 sdio_pins: sdio { 581 mux-0 { 582 groups = "sdio_d0", 583 "sdio_d1", 584 "sdio_d2", 585 "sdio_d3", 586 "sdio_cmd"; 587 function = "sdio"; 588 bias-pull-up; 589 }; 590 591 mux-1 { 592 groups = "sdio_clk"; 593 function = "sdio"; 594 bias-disable; 595 }; 596 }; 597 598 sdio_clk_gate_pins: sdio_clk_gate { 599 mux { 600 groups = "GPIOX_4"; 601 function = "gpio_periphs"; 602 bias-pull-down; 603 }; 604 }; 605 606 spdif_in_z_pins: spdif_in_z { 607 mux { 608 groups = "spdif_in_z"; 609 function = "spdif_in"; 610 bias-disable; 611 }; 612 }; 613 614 spdif_in_a1_pins: spdif_in_a1 { 615 mux { 616 groups = "spdif_in_a1"; 617 function = "spdif_in"; 618 bias-disable; 619 }; 620 }; 621 622 spdif_in_a7_pins: spdif_in_a7 { 623 mux { 624 groups = "spdif_in_a7"; 625 function = "spdif_in"; 626 bias-disable; 627 }; 628 }; 629 630 spdif_in_a19_pins: spdif_in_a19 { 631 mux { 632 groups = "spdif_in_a19"; 633 function = "spdif_in"; 634 bias-disable; 635 }; 636 }; 637 638 spdif_in_a20_pins: spdif_in_a20 { 639 mux { 640 groups = "spdif_in_a20"; 641 function = "spdif_in"; 642 bias-disable; 643 }; 644 }; 645 646 spdif_out_a1_pins: spdif_out_a1 { 647 mux { 648 groups = "spdif_out_a1"; 649 function = "spdif_out"; 650 bias-disable; 651 }; 652 }; 653 654 spdif_out_a11_pins: spdif_out_a11 { 655 mux { 656 groups = "spdif_out_a11"; 657 function = "spdif_out"; 658 bias-disable; 659 }; 660 }; 661 662 spdif_out_a19_pins: spdif_out_a19 { 663 mux { 664 groups = "spdif_out_a19"; 665 function = "spdif_out"; 666 bias-disable; 667 }; 668 }; 669 670 spdif_out_a20_pins: spdif_out_a20 { 671 mux { 672 groups = "spdif_out_a20"; 673 function = "spdif_out"; 674 bias-disable; 675 }; 676 }; 677 678 spdif_out_z_pins: spdif_out_z { 679 mux { 680 groups = "spdif_out_z"; 681 function = "spdif_out"; 682 bias-disable; 683 }; 684 }; 685 686 spi0_pins: spi0 { 687 mux { 688 groups = "spi0_miso", 689 "spi0_mosi", 690 "spi0_clk"; 691 function = "spi0"; 692 bias-disable; 693 }; 694 }; 695 696 spi0_ss0_pins: spi0_ss0 { 697 mux { 698 groups = "spi0_ss0"; 699 function = "spi0"; 700 bias-disable; 701 }; 702 }; 703 704 spi0_ss1_pins: spi0_ss1 { 705 mux { 706 groups = "spi0_ss1"; 707 function = "spi0"; 708 bias-disable; 709 }; 710 }; 711 712 spi0_ss2_pins: spi0_ss2 { 713 mux { 714 groups = "spi0_ss2"; 715 function = "spi0"; 716 bias-disable; 717 }; 718 }; 719 720 spi1_a_pins: spi1_a { 721 mux { 722 groups = "spi1_miso_a", 723 "spi1_mosi_a", 724 "spi1_clk_a"; 725 function = "spi1"; 726 bias-disable; 727 }; 728 }; 729 730 spi1_ss0_a_pins: spi1_ss0_a { 731 mux { 732 groups = "spi1_ss0_a"; 733 function = "spi1"; 734 bias-disable; 735 }; 736 }; 737 738 spi1_ss1_pins: spi1_ss1 { 739 mux { 740 groups = "spi1_ss1"; 741 function = "spi1"; 742 bias-disable; 743 }; 744 }; 745 746 spi1_x_pins: spi1_x { 747 mux { 748 groups = "spi1_miso_x", 749 "spi1_mosi_x", 750 "spi1_clk_x"; 751 function = "spi1"; 752 bias-disable; 753 }; 754 }; 755 756 spi1_ss0_x_pins: spi1_ss0_x { 757 mux { 758 groups = "spi1_ss0_x"; 759 function = "spi1"; 760 bias-disable; 761 }; 762 }; 763 764 tdma_din0_pins: tdma_din0 { 765 mux { 766 groups = "tdma_din0"; 767 function = "tdma"; 768 bias-disable; 769 }; 770 }; 771 772 tdma_dout0_x14_pins: tdma_dout0_x14 { 773 mux { 774 groups = "tdma_dout0_x14"; 775 function = "tdma"; 776 bias-disable; 777 }; 778 }; 779 780 tdma_dout0_x15_pins: tdma_dout0_x15 { 781 mux { 782 groups = "tdma_dout0_x15"; 783 function = "tdma"; 784 bias-disable; 785 }; 786 }; 787 788 tdma_dout1_pins: tdma_dout1 { 789 mux { 790 groups = "tdma_dout1"; 791 function = "tdma"; 792 bias-disable; 793 }; 794 }; 795 796 tdma_din1_pins: tdma_din1 { 797 mux { 798 groups = "tdma_din1"; 799 function = "tdma"; 800 bias-disable; 801 }; 802 }; 803 804 tdma_fs_pins: tdma_fs { 805 mux { 806 groups = "tdma_fs"; 807 function = "tdma"; 808 bias-disable; 809 }; 810 }; 811 812 tdma_fs_slv_pins: tdma_fs_slv { 813 mux { 814 groups = "tdma_fs_slv"; 815 function = "tdma"; 816 bias-disable; 817 }; 818 }; 819 820 tdma_sclk_pins: tdma_sclk { 821 mux { 822 groups = "tdma_sclk"; 823 function = "tdma"; 824 bias-disable; 825 }; 826 }; 827 828 tdma_sclk_slv_pins: tdma_sclk_slv { 829 mux { 830 groups = "tdma_sclk_slv"; 831 function = "tdma"; 832 bias-disable; 833 }; 834 }; 835 836 tdmb_din0_pins: tdmb_din0 { 837 mux { 838 groups = "tdmb_din0"; 839 function = "tdmb"; 840 bias-disable; 841 }; 842 }; 843 844 tdmb_din1_pins: tdmb_din1 { 845 mux { 846 groups = "tdmb_din1"; 847 function = "tdmb"; 848 bias-disable; 849 }; 850 }; 851 852 tdmb_din2_pins: tdmb_din2 { 853 mux { 854 groups = "tdmb_din2"; 855 function = "tdmb"; 856 bias-disable; 857 }; 858 }; 859 860 tdmb_din3_pins: tdmb_din3 { 861 mux { 862 groups = "tdmb_din3"; 863 function = "tdmb"; 864 bias-disable; 865 }; 866 }; 867 868 tdmb_dout0_pins: tdmb_dout0 { 869 mux { 870 groups = "tdmb_dout0"; 871 function = "tdmb"; 872 bias-disable; 873 }; 874 }; 875 876 tdmb_dout1_pins: tdmb_dout1 { 877 mux { 878 groups = "tdmb_dout1"; 879 function = "tdmb"; 880 bias-disable; 881 }; 882 }; 883 884 tdmb_dout2_pins: tdmb_dout2 { 885 mux { 886 groups = "tdmb_dout2"; 887 function = "tdmb"; 888 bias-disable; 889 }; 890 }; 891 892 tdmb_dout3_pins: tdmb_dout3 { 893 mux { 894 groups = "tdmb_dout3"; 895 function = "tdmb"; 896 bias-disable; 897 }; 898 }; 899 900 tdmb_fs_pins: tdmb_fs { 901 mux { 902 groups = "tdmb_fs"; 903 function = "tdmb"; 904 bias-disable; 905 }; 906 }; 907 908 tdmb_fs_slv_pins: tdmb_fs_slv { 909 mux { 910 groups = "tdmb_fs_slv"; 911 function = "tdmb"; 912 bias-disable; 913 }; 914 }; 915 916 tdmb_sclk_pins: tdmb_sclk { 917 mux { 918 groups = "tdmb_sclk"; 919 function = "tdmb"; 920 bias-disable; 921 }; 922 }; 923 924 tdmb_sclk_slv_pins: tdmb_sclk_slv { 925 mux { 926 groups = "tdmb_sclk_slv"; 927 function = "tdmb"; 928 bias-disable; 929 }; 930 }; 931 932 tdmc_fs_pins: tdmc_fs { 933 mux { 934 groups = "tdmc_fs"; 935 function = "tdmc"; 936 bias-disable; 937 }; 938 }; 939 940 tdmc_fs_slv_pins: tdmc_fs_slv { 941 mux { 942 groups = "tdmc_fs_slv"; 943 function = "tdmc"; 944 bias-disable; 945 }; 946 }; 947 948 tdmc_sclk_pins: tdmc_sclk { 949 mux { 950 groups = "tdmc_sclk"; 951 function = "tdmc"; 952 bias-disable; 953 }; 954 }; 955 956 tdmc_sclk_slv_pins: tdmc_sclk_slv { 957 mux { 958 groups = "tdmc_sclk_slv"; 959 function = "tdmc"; 960 bias-disable; 961 }; 962 }; 963 964 tdmc_din0_pins: tdmc_din0 { 965 mux { 966 groups = "tdmc_din0"; 967 function = "tdmc"; 968 bias-disable; 969 }; 970 }; 971 972 tdmc_din1_pins: tdmc_din1 { 973 mux { 974 groups = "tdmc_din1"; 975 function = "tdmc"; 976 bias-disable; 977 }; 978 }; 979 980 tdmc_din2_pins: tdmc_din2 { 981 mux { 982 groups = "tdmc_din2"; 983 function = "tdmc"; 984 bias-disable; 985 }; 986 }; 987 988 tdmc_din3_pins: tdmc_din3 { 989 mux { 990 groups = "tdmc_din3"; 991 function = "tdmc"; 992 bias-disable; 993 }; 994 }; 995 996 tdmc_dout0_pins: tdmc_dout0 { 997 mux { 998 groups = "tdmc_dout0"; 999 function = "tdmc"; 1000 bias-disable; 1001 }; 1002 }; 1003 1004 tdmc_dout1_pins: tdmc_dout1 { 1005 mux { 1006 groups = "tdmc_dout1"; 1007 function = "tdmc"; 1008 bias-disable; 1009 }; 1010 }; 1011 1012 tdmc_dout2_pins: tdmc_dout2 { 1013 mux { 1014 groups = "tdmc_dout2"; 1015 function = "tdmc"; 1016 bias-disable; 1017 }; 1018 }; 1019 1020 tdmc_dout3_pins: tdmc_dout3 { 1021 mux { 1022 groups = "tdmc_dout3"; 1023 function = "tdmc"; 1024 bias-disable; 1025 }; 1026 }; 1027 1028 uart_a_pins: uart_a { 1029 mux { 1030 groups = "uart_tx_a", 1031 "uart_rx_a"; 1032 function = "uart_a"; 1033 bias-disable; 1034 }; 1035 }; 1036 1037 uart_a_cts_rts_pins: uart_a_cts_rts { 1038 mux { 1039 groups = "uart_cts_a", 1040 "uart_rts_a"; 1041 function = "uart_a"; 1042 bias-disable; 1043 }; 1044 }; 1045 1046 uart_b_x_pins: uart_b_x { 1047 mux { 1048 groups = "uart_tx_b_x", 1049 "uart_rx_b_x"; 1050 function = "uart_b"; 1051 bias-disable; 1052 }; 1053 }; 1054 1055 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1056 mux { 1057 groups = "uart_cts_b_x", 1058 "uart_rts_b_x"; 1059 function = "uart_b"; 1060 bias-disable; 1061 }; 1062 }; 1063 1064 uart_b_z_pins: uart_b_z { 1065 mux { 1066 groups = "uart_tx_b_z", 1067 "uart_rx_b_z"; 1068 function = "uart_b"; 1069 bias-disable; 1070 }; 1071 }; 1072 1073 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1074 mux { 1075 groups = "uart_cts_b_z", 1076 "uart_rts_b_z"; 1077 function = "uart_b"; 1078 bias-disable; 1079 }; 1080 }; 1081 1082 uart_ao_b_z_pins: uart_ao_b_z { 1083 mux { 1084 groups = "uart_ao_tx_b_z", 1085 "uart_ao_rx_b_z"; 1086 function = "uart_ao_b_z"; 1087 bias-disable; 1088 }; 1089 }; 1090 1091 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1092 mux { 1093 groups = "uart_ao_cts_b_z", 1094 "uart_ao_rts_b_z"; 1095 function = "uart_ao_b_z"; 1096 bias-disable; 1097 }; 1098 }; 1099 }; 1100 }; 1101 1102 hiubus: bus@ff63c000 { 1103 compatible = "simple-bus"; 1104 reg = <0x0 0xff63c000 0x0 0x1c00>; 1105 #address-cells = <2>; 1106 #size-cells = <2>; 1107 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1108 1109 sysctrl: system-controller@0 { 1110 compatible = "amlogic,meson-axg-hhi-sysctrl", 1111 "simple-mfd", "syscon"; 1112 reg = <0 0 0 0x400>; 1113 1114 clkc: clock-controller { 1115 compatible = "amlogic,axg-clkc"; 1116 #clock-cells = <1>; 1117 clocks = <&xtal>; 1118 clock-names = "xtal"; 1119 }; 1120 }; 1121 }; 1122 1123 mailbox: mailbox@ff63c404 { 1124 compatible = "amlogic,meson-gxbb-mhu"; 1125 reg = <0 0xff63c404 0 0x4c>; 1126 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1127 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1128 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1129 #mbox-cells = <1>; 1130 }; 1131 1132 audio: bus@ff642000 { 1133 compatible = "simple-bus"; 1134 reg = <0x0 0xff642000 0x0 0x2000>; 1135 #address-cells = <2>; 1136 #size-cells = <2>; 1137 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1138 1139 clkc_audio: clock-controller@0 { 1140 compatible = "amlogic,axg-audio-clkc"; 1141 reg = <0x0 0x0 0x0 0xb4>; 1142 #clock-cells = <1>; 1143 1144 clocks = <&clkc CLKID_AUDIO>, 1145 <&clkc CLKID_MPLL0>, 1146 <&clkc CLKID_MPLL1>, 1147 <&clkc CLKID_MPLL2>, 1148 <&clkc CLKID_MPLL3>, 1149 <&clkc CLKID_HIFI_PLL>, 1150 <&clkc CLKID_FCLK_DIV3>, 1151 <&clkc CLKID_FCLK_DIV4>, 1152 <&clkc CLKID_GP0_PLL>; 1153 clock-names = "pclk", 1154 "mst_in0", 1155 "mst_in1", 1156 "mst_in2", 1157 "mst_in3", 1158 "mst_in4", 1159 "mst_in5", 1160 "mst_in6", 1161 "mst_in7"; 1162 1163 resets = <&reset RESET_AUDIO>; 1164 }; 1165 1166 toddr_a: audio-controller@100 { 1167 compatible = "amlogic,axg-toddr"; 1168 reg = <0x0 0x100 0x0 0x2c>; 1169 #sound-dai-cells = <0>; 1170 sound-name-prefix = "TODDR_A"; 1171 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1172 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1173 resets = <&arb AXG_ARB_TODDR_A>; 1174 amlogic,fifo-depth = <512>; 1175 status = "disabled"; 1176 }; 1177 1178 toddr_b: audio-controller@140 { 1179 compatible = "amlogic,axg-toddr"; 1180 reg = <0x0 0x140 0x0 0x2c>; 1181 #sound-dai-cells = <0>; 1182 sound-name-prefix = "TODDR_B"; 1183 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1184 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1185 resets = <&arb AXG_ARB_TODDR_B>; 1186 amlogic,fifo-depth = <256>; 1187 status = "disabled"; 1188 }; 1189 1190 toddr_c: audio-controller@180 { 1191 compatible = "amlogic,axg-toddr"; 1192 reg = <0x0 0x180 0x0 0x2c>; 1193 #sound-dai-cells = <0>; 1194 sound-name-prefix = "TODDR_C"; 1195 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1196 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1197 resets = <&arb AXG_ARB_TODDR_C>; 1198 amlogic,fifo-depth = <256>; 1199 status = "disabled"; 1200 }; 1201 1202 frddr_a: audio-controller@1c0 { 1203 compatible = "amlogic,axg-frddr"; 1204 reg = <0x0 0x1c0 0x0 0x2c>; 1205 #sound-dai-cells = <0>; 1206 sound-name-prefix = "FRDDR_A"; 1207 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1208 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1209 resets = <&arb AXG_ARB_FRDDR_A>; 1210 amlogic,fifo-depth = <512>; 1211 status = "disabled"; 1212 }; 1213 1214 frddr_b: audio-controller@200 { 1215 compatible = "amlogic,axg-frddr"; 1216 reg = <0x0 0x200 0x0 0x2c>; 1217 #sound-dai-cells = <0>; 1218 sound-name-prefix = "FRDDR_B"; 1219 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1220 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1221 resets = <&arb AXG_ARB_FRDDR_B>; 1222 amlogic,fifo-depth = <256>; 1223 status = "disabled"; 1224 }; 1225 1226 frddr_c: audio-controller@240 { 1227 compatible = "amlogic,axg-frddr"; 1228 reg = <0x0 0x240 0x0 0x2c>; 1229 #sound-dai-cells = <0>; 1230 sound-name-prefix = "FRDDR_C"; 1231 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1232 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1233 resets = <&arb AXG_ARB_FRDDR_C>; 1234 amlogic,fifo-depth = <256>; 1235 status = "disabled"; 1236 }; 1237 1238 arb: reset-controller@280 { 1239 compatible = "amlogic,meson-axg-audio-arb"; 1240 reg = <0x0 0x280 0x0 0x4>; 1241 #reset-cells = <1>; 1242 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1243 }; 1244 1245 tdmin_a: audio-controller@300 { 1246 compatible = "amlogic,axg-tdmin"; 1247 reg = <0x0 0x300 0x0 0x40>; 1248 sound-name-prefix = "TDMIN_A"; 1249 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1250 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1251 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1252 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1253 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1254 clock-names = "pclk", "sclk", "sclk_sel", 1255 "lrclk", "lrclk_sel"; 1256 status = "disabled"; 1257 }; 1258 1259 tdmin_b: audio-controller@340 { 1260 compatible = "amlogic,axg-tdmin"; 1261 reg = <0x0 0x340 0x0 0x40>; 1262 sound-name-prefix = "TDMIN_B"; 1263 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1264 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1265 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1266 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1267 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1268 clock-names = "pclk", "sclk", "sclk_sel", 1269 "lrclk", "lrclk_sel"; 1270 status = "disabled"; 1271 }; 1272 1273 tdmin_c: audio-controller@380 { 1274 compatible = "amlogic,axg-tdmin"; 1275 reg = <0x0 0x380 0x0 0x40>; 1276 sound-name-prefix = "TDMIN_C"; 1277 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1278 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1279 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1280 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1281 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1282 clock-names = "pclk", "sclk", "sclk_sel", 1283 "lrclk", "lrclk_sel"; 1284 status = "disabled"; 1285 }; 1286 1287 tdmin_lb: audio-controller@3c0 { 1288 compatible = "amlogic,axg-tdmin"; 1289 reg = <0x0 0x3c0 0x0 0x40>; 1290 sound-name-prefix = "TDMIN_LB"; 1291 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1292 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1293 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1294 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1295 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1296 clock-names = "pclk", "sclk", "sclk_sel", 1297 "lrclk", "lrclk_sel"; 1298 status = "disabled"; 1299 }; 1300 1301 spdifin: audio-controller@400 { 1302 compatible = "amlogic,axg-spdifin"; 1303 reg = <0x0 0x400 0x0 0x30>; 1304 #sound-dai-cells = <0>; 1305 sound-name-prefix = "SPDIFIN"; 1306 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 1307 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1308 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1309 clock-names = "pclk", "refclk"; 1310 status = "disabled"; 1311 }; 1312 1313 spdifout: audio-controller@480 { 1314 compatible = "amlogic,axg-spdifout"; 1315 reg = <0x0 0x480 0x0 0x50>; 1316 #sound-dai-cells = <0>; 1317 sound-name-prefix = "SPDIFOUT"; 1318 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1319 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1320 clock-names = "pclk", "mclk"; 1321 status = "disabled"; 1322 }; 1323 1324 tdmout_a: audio-controller@500 { 1325 compatible = "amlogic,axg-tdmout"; 1326 reg = <0x0 0x500 0x0 0x40>; 1327 sound-name-prefix = "TDMOUT_A"; 1328 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1329 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1330 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1331 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1332 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1333 clock-names = "pclk", "sclk", "sclk_sel", 1334 "lrclk", "lrclk_sel"; 1335 status = "disabled"; 1336 }; 1337 1338 tdmout_b: audio-controller@540 { 1339 compatible = "amlogic,axg-tdmout"; 1340 reg = <0x0 0x540 0x0 0x40>; 1341 sound-name-prefix = "TDMOUT_B"; 1342 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1343 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1344 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1345 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1346 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1347 clock-names = "pclk", "sclk", "sclk_sel", 1348 "lrclk", "lrclk_sel"; 1349 status = "disabled"; 1350 }; 1351 1352 tdmout_c: audio-controller@580 { 1353 compatible = "amlogic,axg-tdmout"; 1354 reg = <0x0 0x580 0x0 0x40>; 1355 sound-name-prefix = "TDMOUT_C"; 1356 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1357 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1358 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1359 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1360 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1361 clock-names = "pclk", "sclk", "sclk_sel", 1362 "lrclk", "lrclk_sel"; 1363 status = "disabled"; 1364 }; 1365 }; 1366 1367 aobus: bus@ff800000 { 1368 compatible = "simple-bus"; 1369 reg = <0x0 0xff800000 0x0 0x100000>; 1370 #address-cells = <2>; 1371 #size-cells = <2>; 1372 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1373 1374 sysctrl_AO: sys-ctrl@0 { 1375 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1376 reg = <0x0 0x0 0x0 0x100>; 1377 1378 clkc_AO: clock-controller { 1379 compatible = "amlogic,meson-axg-aoclkc"; 1380 #clock-cells = <1>; 1381 #reset-cells = <1>; 1382 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1383 clock-names = "xtal", "mpeg-clk"; 1384 }; 1385 }; 1386 1387 pinctrl_aobus: pinctrl@14 { 1388 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1389 #address-cells = <2>; 1390 #size-cells = <2>; 1391 ranges; 1392 1393 gpio_ao: bank@14 { 1394 reg = <0x0 0x00014 0x0 0x8>, 1395 <0x0 0x0002c 0x0 0x4>, 1396 <0x0 0x00024 0x0 0x8>; 1397 reg-names = "mux", "pull", "gpio"; 1398 gpio-controller; 1399 #gpio-cells = <2>; 1400 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1401 }; 1402 1403 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1404 mux { 1405 groups = "i2c_ao_sck_4"; 1406 function = "i2c_ao"; 1407 bias-disable; 1408 }; 1409 }; 1410 1411 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1412 mux { 1413 groups = "i2c_ao_sck_8"; 1414 function = "i2c_ao"; 1415 bias-disable; 1416 }; 1417 }; 1418 1419 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1420 mux { 1421 groups = "i2c_ao_sck_10"; 1422 function = "i2c_ao"; 1423 bias-disable; 1424 }; 1425 }; 1426 1427 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1428 mux { 1429 groups = "i2c_ao_sda_5"; 1430 function = "i2c_ao"; 1431 bias-disable; 1432 }; 1433 }; 1434 1435 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1436 mux { 1437 groups = "i2c_ao_sda_9"; 1438 function = "i2c_ao"; 1439 bias-disable; 1440 }; 1441 }; 1442 1443 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1444 mux { 1445 groups = "i2c_ao_sda_11"; 1446 function = "i2c_ao"; 1447 bias-disable; 1448 }; 1449 }; 1450 1451 remote_input_ao_pins: remote_input_ao { 1452 mux { 1453 groups = "remote_input_ao"; 1454 function = "remote_input_ao"; 1455 bias-disable; 1456 }; 1457 }; 1458 1459 uart_ao_a_pins: uart_ao_a { 1460 mux { 1461 groups = "uart_ao_tx_a", 1462 "uart_ao_rx_a"; 1463 function = "uart_ao_a"; 1464 bias-disable; 1465 }; 1466 }; 1467 1468 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1469 mux { 1470 groups = "uart_ao_cts_a", 1471 "uart_ao_rts_a"; 1472 function = "uart_ao_a"; 1473 bias-disable; 1474 }; 1475 }; 1476 1477 uart_ao_b_pins: uart_ao_b { 1478 mux { 1479 groups = "uart_ao_tx_b", 1480 "uart_ao_rx_b"; 1481 function = "uart_ao_b"; 1482 bias-disable; 1483 }; 1484 }; 1485 1486 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1487 mux { 1488 groups = "uart_ao_cts_b", 1489 "uart_ao_rts_b"; 1490 function = "uart_ao_b"; 1491 bias-disable; 1492 }; 1493 }; 1494 }; 1495 1496 sec_AO: ao-secure@140 { 1497 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1498 reg = <0x0 0x140 0x0 0x140>; 1499 amlogic,has-chip-id; 1500 }; 1501 1502 pwm_AO_cd: pwm@2000 { 1503 compatible = "amlogic,meson-axg-ao-pwm"; 1504 reg = <0x0 0x02000 0x0 0x20>; 1505 #pwm-cells = <3>; 1506 status = "disabled"; 1507 }; 1508 1509 uart_AO: serial@3000 { 1510 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1511 reg = <0x0 0x3000 0x0 0x18>; 1512 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1513 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1514 clock-names = "xtal", "pclk", "baud"; 1515 status = "disabled"; 1516 }; 1517 1518 uart_AO_B: serial@4000 { 1519 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1520 reg = <0x0 0x4000 0x0 0x18>; 1521 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1522 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1523 clock-names = "xtal", "pclk", "baud"; 1524 status = "disabled"; 1525 }; 1526 1527 i2c_AO: i2c@5000 { 1528 compatible = "amlogic,meson-axg-i2c"; 1529 reg = <0x0 0x05000 0x0 0x20>; 1530 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1531 clocks = <&clkc CLKID_AO_I2C>; 1532 #address-cells = <1>; 1533 #size-cells = <0>; 1534 status = "disabled"; 1535 }; 1536 1537 pwm_AO_ab: pwm@7000 { 1538 compatible = "amlogic,meson-axg-ao-pwm"; 1539 reg = <0x0 0x07000 0x0 0x20>; 1540 #pwm-cells = <3>; 1541 status = "disabled"; 1542 }; 1543 1544 ir: ir@8000 { 1545 compatible = "amlogic,meson-gxbb-ir"; 1546 reg = <0x0 0x8000 0x0 0x20>; 1547 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1548 status = "disabled"; 1549 }; 1550 1551 saradc: adc@9000 { 1552 compatible = "amlogic,meson-axg-saradc", 1553 "amlogic,meson-saradc"; 1554 reg = <0x0 0x9000 0x0 0x38>; 1555 #io-channel-cells = <1>; 1556 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1557 clocks = <&xtal>, 1558 <&clkc_AO CLKID_AO_SAR_ADC>, 1559 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1560 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1561 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1562 status = "disabled"; 1563 }; 1564 }; 1565 1566 gic: interrupt-controller@ffc01000 { 1567 compatible = "arm,gic-400"; 1568 reg = <0x0 0xffc01000 0 0x1000>, 1569 <0x0 0xffc02000 0 0x2000>, 1570 <0x0 0xffc04000 0 0x2000>, 1571 <0x0 0xffc06000 0 0x2000>; 1572 interrupt-controller; 1573 interrupts = <GIC_PPI 9 1574 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1575 #interrupt-cells = <3>; 1576 #address-cells = <0>; 1577 }; 1578 1579 cbus: bus@ffd00000 { 1580 compatible = "simple-bus"; 1581 reg = <0x0 0xffd00000 0x0 0x25000>; 1582 #address-cells = <2>; 1583 #size-cells = <2>; 1584 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1585 1586 reset: reset-controller@1004 { 1587 compatible = "amlogic,meson-axg-reset"; 1588 reg = <0x0 0x01004 0x0 0x9c>; 1589 #reset-cells = <1>; 1590 }; 1591 1592 gpio_intc: interrupt-controller@f080 { 1593 compatible = "amlogic,meson-axg-gpio-intc", 1594 "amlogic,meson-gpio-intc"; 1595 reg = <0x0 0xf080 0x0 0x10>; 1596 interrupt-controller; 1597 #interrupt-cells = <2>; 1598 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1599 }; 1600 1601 watchdog@f0d0 { 1602 compatible = "amlogic,meson-gxbb-wdt"; 1603 reg = <0x0 0xf0d0 0x0 0x10>; 1604 clocks = <&xtal>; 1605 }; 1606 1607 pwm_ab: pwm@1b000 { 1608 compatible = "amlogic,meson-axg-ee-pwm"; 1609 reg = <0x0 0x1b000 0x0 0x20>; 1610 #pwm-cells = <3>; 1611 status = "disabled"; 1612 }; 1613 1614 pwm_cd: pwm@1a000 { 1615 compatible = "amlogic,meson-axg-ee-pwm"; 1616 reg = <0x0 0x1a000 0x0 0x20>; 1617 #pwm-cells = <3>; 1618 status = "disabled"; 1619 }; 1620 1621 spicc0: spi@13000 { 1622 compatible = "amlogic,meson-axg-spicc"; 1623 reg = <0x0 0x13000 0x0 0x3c>; 1624 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1625 clocks = <&clkc CLKID_SPICC0>; 1626 clock-names = "core"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 spicc1: spi@15000 { 1633 compatible = "amlogic,meson-axg-spicc"; 1634 reg = <0x0 0x15000 0x0 0x3c>; 1635 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1636 clocks = <&clkc CLKID_SPICC1>; 1637 clock-names = "core"; 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 status = "disabled"; 1641 }; 1642 1643 clk_msr: clock-measure@18000 { 1644 compatible = "amlogic,meson-axg-clk-measure"; 1645 reg = <0x0 0x18000 0x0 0x10>; 1646 }; 1647 1648 i2c3: i2c@1c000 { 1649 compatible = "amlogic,meson-axg-i2c"; 1650 reg = <0x0 0x1c000 0x0 0x20>; 1651 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1652 clocks = <&clkc CLKID_I2C>; 1653 #address-cells = <1>; 1654 #size-cells = <0>; 1655 status = "disabled"; 1656 }; 1657 1658 i2c2: i2c@1d000 { 1659 compatible = "amlogic,meson-axg-i2c"; 1660 reg = <0x0 0x1d000 0x0 0x20>; 1661 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1662 clocks = <&clkc CLKID_I2C>; 1663 #address-cells = <1>; 1664 #size-cells = <0>; 1665 status = "disabled"; 1666 }; 1667 1668 i2c1: i2c@1e000 { 1669 compatible = "amlogic,meson-axg-i2c"; 1670 reg = <0x0 0x1e000 0x0 0x20>; 1671 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1672 clocks = <&clkc CLKID_I2C>; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 status = "disabled"; 1676 }; 1677 1678 i2c0: i2c@1f000 { 1679 compatible = "amlogic,meson-axg-i2c"; 1680 reg = <0x0 0x1f000 0x0 0x20>; 1681 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1682 clocks = <&clkc CLKID_I2C>; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 status = "disabled"; 1686 }; 1687 1688 uart_B: serial@23000 { 1689 compatible = "amlogic,meson-gx-uart"; 1690 reg = <0x0 0x23000 0x0 0x18>; 1691 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1692 status = "disabled"; 1693 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1694 clock-names = "xtal", "pclk", "baud"; 1695 }; 1696 1697 uart_A: serial@24000 { 1698 compatible = "amlogic,meson-gx-uart"; 1699 reg = <0x0 0x24000 0x0 0x18>; 1700 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1701 status = "disabled"; 1702 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1703 clock-names = "xtal", "pclk", "baud"; 1704 }; 1705 }; 1706 1707 apb: bus@ffe00000 { 1708 compatible = "simple-bus"; 1709 reg = <0x0 0xffe00000 0x0 0x200000>; 1710 #address-cells = <2>; 1711 #size-cells = <2>; 1712 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1713 1714 sd_emmc_b: sd@5000 { 1715 compatible = "amlogic,meson-axg-mmc"; 1716 reg = <0x0 0x5000 0x0 0x800>; 1717 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1718 status = "disabled"; 1719 clocks = <&clkc CLKID_SD_EMMC_B>, 1720 <&clkc CLKID_SD_EMMC_B_CLK0>, 1721 <&clkc CLKID_FCLK_DIV2>; 1722 clock-names = "core", "clkin0", "clkin1"; 1723 resets = <&reset RESET_SD_EMMC_B>; 1724 }; 1725 1726 sd_emmc_c: mmc@7000 { 1727 compatible = "amlogic,meson-axg-mmc"; 1728 reg = <0x0 0x7000 0x0 0x800>; 1729 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1730 status = "disabled"; 1731 clocks = <&clkc CLKID_SD_EMMC_C>, 1732 <&clkc CLKID_SD_EMMC_C_CLK0>, 1733 <&clkc CLKID_FCLK_DIV2>; 1734 clock-names = "core", "clkin0", "clkin1"; 1735 resets = <&reset RESET_SD_EMMC_C>; 1736 }; 1737 }; 1738 1739 sram: sram@fffc0000 { 1740 compatible = "mmio-sram"; 1741 reg = <0x0 0xfffc0000 0x0 0x20000>; 1742 #address-cells = <1>; 1743 #size-cells = <1>; 1744 ranges = <0 0x0 0xfffc0000 0x20000>; 1745 1746 cpu_scp_lpri: scp-sram@13000 { 1747 compatible = "amlogic,meson-axg-scp-shmem"; 1748 reg = <0x13000 0x400>; 1749 }; 1750 1751 cpu_scp_hpri: scp-sram@13400 { 1752 compatible = "amlogic,meson-axg-scp-shmem"; 1753 reg = <0x13400 0x400>; 1754 }; 1755 }; 1756 }; 1757 1758 timer { 1759 compatible = "arm,armv8-timer"; 1760 interrupts = <GIC_PPI 13 1761 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1762 <GIC_PPI 14 1763 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1764 <GIC_PPI 11 1765 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1766 <GIC_PPI 10 1767 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1768 }; 1769 1770 xtal: xtal-clk { 1771 compatible = "fixed-clock"; 1772 clock-frequency = <24000000>; 1773 clock-output-names = "xtal"; 1774 #clock-cells = <0>; 1775 }; 1776}; 1777