1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2/*
3 * Copyright (C) 2020 Marcin Sloniewski <marcin.sloniewski@gmail.com>
4 */
5
6#include <dt-bindings/clock/stm32mp1-clksrc.h>
7#include "stm32mp15-u-boot.dtsi"
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11	config {
12		u-boot,boot-led = "heartbeat";
13	};
14};
15
16&clk_hse {
17	st,digbypass;
18};
19
20&i2c2 {
21	u-boot,dm-pre-reloc;
22};
23
24&i2c2_pins_a {
25	u-boot,dm-pre-reloc;
26	pins {
27		u-boot,dm-pre-reloc;
28	};
29};
30
31&pmic {
32	u-boot,dm-pre-reloc;
33};
34
35&rcc {
36	st,clksrc = <
37		CLK_MPU_PLL1P
38		CLK_AXI_PLL2P
39		CLK_MCU_PLL3P
40		CLK_PLL12_HSE
41		CLK_PLL3_HSE
42		CLK_PLL4_HSE
43		CLK_RTC_LSE
44		CLK_MCO1_DISABLED
45		CLK_MCO2_DISABLED
46	>;
47
48	st,clkdiv = <
49		1 /*MPU*/
50		0 /*AXI*/
51		0 /*MCU*/
52		1 /*APB1*/
53		1 /*APB2*/
54		1 /*APB3*/
55		1 /*APB4*/
56		2 /*APB5*/
57		23 /*RTC*/
58		0 /*MCO1*/
59		0 /*MCO2*/
60	>;
61
62	st,pkcs = <
63		CLK_CKPER_HSE
64		CLK_FMC_ACLK
65		CLK_QSPI_ACLK
66		CLK_ETH_DISABLED
67		CLK_SDMMC12_PLL4P
68		CLK_DSI_DSIPLL
69		CLK_STGEN_HSE
70		CLK_USBPHY_HSE
71		CLK_SPI2S1_PLL3Q
72		CLK_SPI2S23_PLL3Q
73		CLK_SPI45_HSI
74		CLK_SPI6_HSI
75		CLK_I2C46_HSI
76		CLK_SDMMC3_PLL4P
77		CLK_USBO_USBPHY
78		CLK_ADC_CKPER
79		CLK_CEC_LSE
80		CLK_I2C12_HSI
81		CLK_I2C35_HSI
82		CLK_UART1_HSI
83		CLK_UART24_HSI
84		CLK_UART35_HSI
85		CLK_UART6_HSI
86		CLK_UART78_HSI
87		CLK_SPDIF_PLL4P
88		CLK_FDCAN_PLL4R
89		CLK_SAI1_PLL3Q
90		CLK_SAI2_PLL3Q
91		CLK_SAI3_PLL3Q
92		CLK_SAI4_PLL3Q
93		CLK_RNG1_LSI
94		CLK_RNG2_LSI
95		CLK_LPTIM1_PCLK1
96		CLK_LPTIM23_PCLK3
97		CLK_LPTIM45_LSE
98	>;
99
100	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
101	pll2: st,pll@1 {
102		compatible = "st,stm32mp1-pll";
103		reg = <1>;
104		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
105		frac = < 0x1400 >;
106		u-boot,dm-pre-reloc;
107	};
108
109	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
110	pll3: st,pll@2 {
111		compatible = "st,stm32mp1-pll";
112		reg = <2>;
113		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
114		frac = < 0x1a04 >;
115		u-boot,dm-pre-reloc;
116	};
117
118	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
119	pll4: st,pll@3 {
120		compatible = "st,stm32mp1-pll";
121		reg = <3>;
122		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
123		u-boot,dm-pre-reloc;
124	};
125};
126