1 #ifndef __DMC_H__
2 #define __DMC_H__
3 
4 #ifndef __ASSEMBLY__
5 struct exynos4_dmc {
6 	unsigned int concontrol;
7 	unsigned int memcontrol;
8 	unsigned int memconfig0;
9 	unsigned int memconfig1;
10 	unsigned int directcmd;
11 	unsigned int prechconfig;
12 	unsigned int phycontrol0;
13 	unsigned int phycontrol1;
14 	unsigned int phycontrol2;
15 	unsigned int phycontrol3;
16 	unsigned int pwrdnconfig;
17 	unsigned char res1[0x4];
18 	unsigned int timingref;
19 	unsigned int timingrow;
20 	unsigned int timingdata;
21 	unsigned int timingpower;
22 	unsigned int phystatus;
23 	unsigned int phyzqcontrol;
24 	unsigned int chip0status;
25 	unsigned int chip1status;
26 	unsigned int arefstatus;
27 	unsigned int mrstatus;
28 	unsigned int phytest0;
29 	unsigned int phytest1;
30 	unsigned int qoscontrol0;
31 	unsigned int qosconfig0;
32 	unsigned int qoscontrol1;
33 	unsigned int qosconfig1;
34 	unsigned int qoscontrol2;
35 	unsigned int qosconfig2;
36 	unsigned int qoscontrol3;
37 	unsigned int qosconfig3;
38 	unsigned int qoscontrol4;
39 	unsigned int qosconfig4;
40 	unsigned int qoscontrol5;
41 	unsigned int qosconfig5;
42 	unsigned int qoscontrol6;
43 	unsigned int qosconfig6;
44 	unsigned int qoscontrol7;
45 	unsigned int qosconfig7;
46 	unsigned int qoscontrol8;
47 	unsigned int qosconfig8;
48 	unsigned int qoscontrol9;
49 	unsigned int qosconfig9;
50 	unsigned int qoscontrol10;
51 	unsigned int qosconfig10;
52 	unsigned int qoscontrol11;
53 	unsigned int qosconfig11;
54 	unsigned int qoscontrol12;
55 	unsigned int qosconfig12;
56 	unsigned int qoscontrol13;
57 	unsigned int qosconfig13;
58 	unsigned int qoscontrol14;
59 	unsigned int qosconfig14;
60 	unsigned int qoscontrol15;
61 	unsigned int qosconfig15;
62 	unsigned int qostimeout0;
63 	unsigned int qostimeout1;
64 	unsigned char res2[0x8];
65 	unsigned int ivcontrol;
66 	unsigned char res3[0x8];
67 	unsigned int perevconfig;
68 	unsigned char res4[0xDF00];
69 	unsigned int pmnc_ppc_a;
70 	unsigned char res5[0xC];
71 	unsigned int cntens_ppc_a;
72 	unsigned char res6[0xC];
73 	unsigned int cntenc_ppc_a;
74 	unsigned char res7[0xC];
75 	unsigned int intens_ppc_a;
76 	unsigned char res8[0xC];
77 	unsigned int intenc_ppc_a;
78 	unsigned char res9[0xC];
79 	unsigned int flag_ppc_a;
80 	unsigned char res10[0xAC];
81 	unsigned int ccnt_ppc_a;
82 	unsigned char res11[0xC];
83 	unsigned int pmcnt0_ppc_a;
84 	unsigned char res12[0xC];
85 	unsigned int pmcnt1_ppc_a;
86 	unsigned char res13[0xC];
87 	unsigned int pmcnt2_ppc_a;
88 	unsigned char res14[0xC];
89 	unsigned int pmcnt3_ppc_a;
90 	unsigned char res15[0xEBC];
91 	unsigned int pmnc_ppc_m;
92 	unsigned char res16[0xC];
93 	unsigned int cntens_ppc_m;
94 	unsigned char res17[0xC];
95 	unsigned int cntenc_ppc_m;
96 	unsigned char res18[0xC];
97 	unsigned int intens_ppc_m;
98 	unsigned char res19[0xC];
99 	unsigned int intenc_ppc_m;
100 	unsigned char res20[0xC];
101 	unsigned int flag_ppc_m;
102 	unsigned char res21[0xAC];
103 	unsigned int ccnt_ppc_m;
104 	unsigned char res22[0xC];
105 	unsigned int pmcnt0_ppc_m;
106 	unsigned char res23[0xC];
107 	unsigned int pmcnt1_ppc_m;
108 	unsigned char res24[0xC];
109 	unsigned int pmcnt2_ppc_m;
110 	unsigned char res25[0xC];
111 	unsigned int pmcnt3_ppc_m;
112 };
113 
114 struct exynos5_dmc {
115 	unsigned int concontrol;
116 	unsigned int memcontrol;
117 	unsigned int memconfig0;
118 	unsigned int memconfig1;
119 	unsigned int directcmd;
120 	unsigned int prechconfig;
121 	unsigned int phycontrol0;
122 	unsigned char res1[0xc];
123 	unsigned int pwrdnconfig;
124 	unsigned int timingpzq;
125 	unsigned int timingref;
126 	unsigned int timingrow;
127 	unsigned int timingdata;
128 	unsigned int timingpower;
129 	unsigned int phystatus;
130 	unsigned char res2[0x4];
131 	unsigned int chipstatus_ch0;
132 	unsigned int chipstatus_ch1;
133 	unsigned char res3[0x4];
134 	unsigned int mrstatus;
135 	unsigned char res4[0x8];
136 	unsigned int qoscontrol0;
137 	unsigned char resr5[0x4];
138 	unsigned int qoscontrol1;
139 	unsigned char res6[0x4];
140 	unsigned int qoscontrol2;
141 	unsigned char res7[0x4];
142 	unsigned int qoscontrol3;
143 	unsigned char res8[0x4];
144 	unsigned int qoscontrol4;
145 	unsigned char res9[0x4];
146 	unsigned int qoscontrol5;
147 	unsigned char res10[0x4];
148 	unsigned int qoscontrol6;
149 	unsigned char res11[0x4];
150 	unsigned int qoscontrol7;
151 	unsigned char res12[0x4];
152 	unsigned int qoscontrol8;
153 	unsigned char res13[0x4];
154 	unsigned int qoscontrol9;
155 	unsigned char res14[0x4];
156 	unsigned int qoscontrol10;
157 	unsigned char res15[0x4];
158 	unsigned int qoscontrol11;
159 	unsigned char res16[0x4];
160 	unsigned int qoscontrol12;
161 	unsigned char res17[0x4];
162 	unsigned int qoscontrol13;
163 	unsigned char res18[0x4];
164 	unsigned int qoscontrol14;
165 	unsigned char res19[0x4];
166 	unsigned int qoscontrol15;
167 	unsigned char res20[0x14];
168 	unsigned int ivcontrol;
169 	unsigned int wrtra_config;
170 	unsigned int rdlvl_config;
171 	unsigned char res21[0x8];
172 	unsigned int brbrsvconfig;
173 	unsigned int brbqosconfig;
174 	unsigned int membaseconfig0;
175 	unsigned int membaseconfig1;
176 	unsigned char res22[0xc];
177 	unsigned int wrlvl_config;
178 	unsigned char res23[0xc];
179 	unsigned int perevcontrol;
180 	unsigned int perev0config;
181 	unsigned int perev1config;
182 	unsigned int perev2config;
183 	unsigned int perev3config;
184 	unsigned char res24[0xdebc];
185 	unsigned int pmnc_ppc_a;
186 	unsigned char res25[0xc];
187 	unsigned int cntens_ppc_a;
188 	unsigned char res26[0xc];
189 	unsigned int cntenc_ppc_a;
190 	unsigned char res27[0xc];
191 	unsigned int intens_ppc_a;
192 	unsigned char res28[0xc];
193 	unsigned int intenc_ppc_a;
194 	unsigned char res29[0xc];
195 	unsigned int flag_ppc_a;
196 	unsigned char res30[0xac];
197 	unsigned int ccnt_ppc_a;
198 	unsigned char res31[0xc];
199 	unsigned int pmcnt0_ppc_a;
200 	unsigned char res32[0xc];
201 	unsigned int pmcnt1_ppc_a;
202 	unsigned char res33[0xc];
203 	unsigned int pmcnt2_ppc_a;
204 	unsigned char res34[0xc];
205 	unsigned int pmcnt3_ppc_a;
206 };
207 
208 struct exynos5420_dmc {
209 	unsigned int concontrol;
210 	unsigned int memcontrol;
211 	unsigned int cgcontrol;
212 	unsigned char res500[0x4];
213 	unsigned int directcmd;
214 	unsigned int prechconfig0;
215 	unsigned int phycontrol0;
216 	unsigned int prechconfig1;
217 	unsigned char res1[0x8];
218 	unsigned int pwrdnconfig;
219 	unsigned int timingpzq;
220 	unsigned int timingref;
221 	unsigned int timingrow0;
222 	unsigned int timingdata0;
223 	unsigned int timingpower0;
224 	unsigned int phystatus;
225 	unsigned int etctiming;
226 	unsigned int chipstatus;
227 	unsigned char res3[0x8];
228 	unsigned int mrstatus;
229 	unsigned char res4[0x8];
230 	unsigned int qoscontrol0;
231 	unsigned char resr5[0x4];
232 	unsigned int qoscontrol1;
233 	unsigned char res6[0x4];
234 	unsigned int qoscontrol2;
235 	unsigned char res7[0x4];
236 	unsigned int qoscontrol3;
237 	unsigned char res8[0x4];
238 	unsigned int qoscontrol4;
239 	unsigned char res9[0x4];
240 	unsigned int qoscontrol5;
241 	unsigned char res10[0x4];
242 	unsigned int qoscontrol6;
243 	unsigned char res11[0x4];
244 	unsigned int qoscontrol7;
245 	unsigned char res12[0x4];
246 	unsigned int qoscontrol8;
247 	unsigned char res13[0x4];
248 	unsigned int qoscontrol9;
249 	unsigned char res14[0x4];
250 	unsigned int qoscontrol10;
251 	unsigned char res15[0x4];
252 	unsigned int qoscontrol11;
253 	unsigned char res16[0x4];
254 	unsigned int qoscontrol12;
255 	unsigned char res17[0x4];
256 	unsigned int qoscontrol13;
257 	unsigned char res18[0x4];
258 	unsigned int qoscontrol14;
259 	unsigned char res19[0x4];
260 	unsigned int qoscontrol15;
261 	unsigned char res20[0x4];
262 	unsigned int timing_set_sw;
263 	unsigned int timingrow1;
264 	unsigned int timingdata1;
265 	unsigned int timingpower1;
266 	unsigned char res300[0x4];
267 	unsigned int wrtra_config;
268 	unsigned int rdlvl_config;
269 	unsigned char res21[0x4];
270 	unsigned int brbrsvcontrol;
271 	unsigned int brbrsvconfig;
272 	unsigned int brbqosconfig;
273 	unsigned char res301[0x14];
274 	unsigned int wrlvl_config0;
275 	unsigned int wrlvl_config1;
276 	unsigned int wrlvl_status;
277 	unsigned char res23[0x4];
278 	unsigned int ppcclockon;
279 	unsigned int perevconfig0;
280 	unsigned int perevconfig1;
281 	unsigned int perevconfig2;
282 	unsigned int perevconfig3;
283 	unsigned char res24[0xc];
284 	unsigned int control_io_rdata;
285 	unsigned char res240[0xc];
286 	unsigned int cacal_config0;
287 	unsigned int cacal_config1;
288 	unsigned int cacal_status;
289 	unsigned char res302[0xa4];
290 	unsigned int bp_control0;
291 	unsigned int bp_config0_r;
292 	unsigned int bp_config0_w;
293 	unsigned char res303[0x4];
294 	unsigned int bp_control1;
295 	unsigned int bp_config1_r;
296 	unsigned int bp_config1_w;
297 	unsigned char res304[0x4];
298 	unsigned int bp_control2;
299 	unsigned int bp_config2_r;
300 	unsigned int bp_config2_w;
301 	unsigned char res305[0x4];
302 	unsigned int bp_control3;
303 	unsigned int bp_config3_r;
304 	unsigned int bp_config3_w;
305 	unsigned char res306[0xddb4];
306 	unsigned int pmnc_ppc;
307 	unsigned char res25[0xc];
308 	unsigned int cntens_ppc;
309 	unsigned char res26[0xc];
310 	unsigned int cntenc_ppc;
311 	unsigned char res27[0xc];
312 	unsigned int intens_ppc;
313 	unsigned char res28[0xc];
314 	unsigned int intenc_ppc;
315 	unsigned char res29[0xc];
316 	unsigned int flag_ppc;
317 	unsigned char res30[0xac];
318 	unsigned int ccnt_ppc;
319 	unsigned char res31[0xc];
320 	unsigned int pmcnt0_ppc;
321 	unsigned char res32[0xc];
322 	unsigned int pmcnt1_ppc;
323 	unsigned char res33[0xc];
324 	unsigned int pmcnt2_ppc;
325 	unsigned char res34[0xc];
326 	unsigned int pmcnt3_ppc;
327 };
328 
329 struct exynos5_phy_control {
330 	unsigned int phy_con0;
331 	unsigned int phy_con1;
332 	unsigned int phy_con2;
333 	unsigned int phy_con3;
334 	unsigned int phy_con4;
335 	unsigned char res1[4];
336 	unsigned int phy_con6;
337 	unsigned char res2[4];
338 	unsigned int phy_con8;
339 	unsigned int phy_con9;
340 	unsigned int phy_con10;
341 	unsigned char res3[4];
342 	unsigned int phy_con12;
343 	unsigned int phy_con13;
344 	unsigned int phy_con14;
345 	unsigned int phy_con15;
346 	unsigned int phy_con16;
347 	unsigned char res4[4];
348 	unsigned int phy_con17;
349 	unsigned int phy_con18;
350 	unsigned int phy_con19;
351 	unsigned int phy_con20;
352 	unsigned int phy_con21;
353 	unsigned int phy_con22;
354 	unsigned int phy_con23;
355 	unsigned int phy_con24;
356 	unsigned int phy_con25;
357 	unsigned int phy_con26;
358 	unsigned int phy_con27;
359 	unsigned int phy_con28;
360 	unsigned int phy_con29;
361 	unsigned int phy_con30;
362 	unsigned int phy_con31;
363 	unsigned int phy_con32;
364 	unsigned int phy_con33;
365 	unsigned int phy_con34;
366 	unsigned int phy_con35;
367 	unsigned int phy_con36;
368 	unsigned int phy_con37;
369 	unsigned int phy_con38;
370 	unsigned int phy_con39;
371 	unsigned int phy_con40;
372 	unsigned int phy_con41;
373 	unsigned int phy_con42;
374 };
375 
376 struct exynos5420_phy_control {
377 	unsigned int phy_con0;
378 	unsigned int phy_con1;
379 	unsigned int phy_con2;
380 	unsigned int phy_con3;
381 	unsigned int phy_con4;
382 	unsigned int phy_con5;
383 	unsigned int phy_con6;
384 	unsigned char res2[0x4];
385 	unsigned int phy_con8;
386 	unsigned char res5[0x4];
387 	unsigned int phy_con10;
388 	unsigned int phy_con11;
389 	unsigned int phy_con12;
390 	unsigned int phy_con13;
391 	unsigned int phy_con14;
392 	unsigned int phy_con15;
393 	unsigned int phy_con16;
394 	unsigned char res4[0x4];
395 	unsigned int phy_con17;
396 	unsigned int phy_con18;
397 	unsigned int phy_con19;
398 	unsigned int phy_con20;
399 	unsigned int phy_con21;
400 	unsigned int phy_con22;
401 	unsigned int phy_con23;
402 	unsigned int phy_con24;
403 	unsigned int phy_con25;
404 	unsigned int phy_con26;
405 	unsigned int phy_con27;
406 	unsigned int phy_con28;
407 	unsigned int phy_con29;
408 	unsigned int phy_con30;
409 	unsigned int phy_con31;
410 	unsigned int phy_con32;
411 	unsigned int phy_con33;
412 	unsigned int phy_con34;
413 	unsigned char res6[0x8];
414 	unsigned int phy_con37;
415 	unsigned char res7[0x4];
416 	unsigned int phy_con39;
417 	unsigned int phy_con40;
418 	unsigned int phy_con41;
419 	unsigned int phy_con42;
420 };
421 
422 struct exynos5420_tzasc {
423 	unsigned char res1[0xf00];
424 	unsigned int membaseconfig0;
425 	unsigned int membaseconfig1;
426 	unsigned char res2[0x8];
427 	unsigned int memconfig0;
428 	unsigned int memconfig1;
429 };
430 
431 enum ddr_mode {
432 	DDR_MODE_DDR2,
433 	DDR_MODE_DDR3,
434 	DDR_MODE_LPDDR2,
435 	DDR_MODE_LPDDR3,
436 
437 	DDR_MODE_COUNT,
438 };
439 
440 enum mem_manuf {
441 	MEM_MANUF_AUTODETECT,
442 	MEM_MANUF_ELPIDA,
443 	MEM_MANUF_SAMSUNG,
444 
445 	MEM_MANUF_COUNT,
446 };
447 
448 /* CONCONTROL register fields */
449 #define CONCONTROL_DFI_INIT_START_SHIFT	28
450 #define CONCONTROL_RD_FETCH_SHIFT	12
451 #define CONCONTROL_RD_FETCH_MASK	(0x7 << CONCONTROL_RD_FETCH_SHIFT)
452 #define CONCONTROL_AREF_EN_SHIFT	5
453 #define CONCONTROL_UPDATE_MODE		(1 << 3)
454 
455 /* PRECHCONFIG register field */
456 #define PRECHCONFIG_TP_CNT_SHIFT	24
457 
458 /* PWRDNCONFIG register field */
459 #define PWRDNCONFIG_DPWRDN_CYC_SHIFT	0
460 #define PWRDNCONFIG_DSREF_CYC_SHIFT	16
461 
462 /* PHY_CON0 register fields */
463 #define PHY_CON0_T_WRRDCMD_SHIFT	17
464 #define PHY_CON0_T_WRRDCMD_MASK		(0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
465 #define PHY_CON0_CTRL_DDR_MODE_SHIFT	11
466 #define PHY_CON0_CTRL_DDR_MODE_MASK	0x3
467 
468 /* PHY_CON1 register fields */
469 #define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT	0
470 
471 /* PHY_CON4 rgister fields */
472 #define PHY_CON10_CTRL_OFFSETR3		(1 << 24)
473 
474 /* PHY_CON12 register fields */
475 #define PHY_CON12_CTRL_START_POINT_SHIFT	24
476 #define PHY_CON12_CTRL_INC_SHIFT	16
477 #define PHY_CON12_CTRL_FORCE_SHIFT	8
478 #define PHY_CON12_CTRL_START_SHIFT	6
479 #define PHY_CON12_CTRL_START_MASK	(1 << PHY_CON12_CTRL_START_SHIFT)
480 #define PHY_CON12_CTRL_DLL_ON_SHIFT	5
481 #define PHY_CON12_CTRL_DLL_ON_MASK	(1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
482 #define PHY_CON12_CTRL_REF_SHIFT	1
483 
484 /* PHY_CON16 register fields */
485 #define PHY_CON16_ZQ_MODE_DDS_SHIFT	24
486 #define PHY_CON16_ZQ_MODE_DDS_MASK	(0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
487 
488 #define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
489 #define PHY_CON16_ZQ_MODE_TERM_MASK	(0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
490 
491 #define PHY_CON16_ZQ_MODE_NOTERM_MASK	(1 << 19)
492 
493 /* PHY_CON42 register fields */
494 #define PHY_CON42_CTRL_BSTLEN_SHIFT	8
495 #define PHY_CON42_CTRL_BSTLEN_MASK	(0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
496 
497 #define PHY_CON42_CTRL_RDLAT_SHIFT	0
498 #define PHY_CON42_CTRL_RDLAT_MASK	(0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
499 
500 #endif
501 #endif
502