1menu "MIPS architecture" 2 depends on MIPS 3 4config SYS_ARCH 5 default "mips" 6 7config SYS_CPU 8 default "mips32" if CPU_MIPS32 9 default "mips64" if CPU_MIPS64 10 11choice 12 prompt "Target select" 13 optional 14 15config TARGET_MALTA 16 bool "Support malta" 17 select DM 18 select DM_SERIAL 19 select DYNAMIC_IO_PORT_BASE 20 select MIPS_CM 21 select MIPS_INSERT_BOOT_CONFIG 22 select MIPS_L1_CACHE_SHIFT_6 23 select MIPS_L2_CACHE 24 select OF_CONTROL 25 select OF_ISA_BUS 26 select ROM_EXCEPTION_VECTORS 27 select SUPPORTS_BIG_ENDIAN 28 select SUPPORTS_CPU_MIPS32_R1 29 select SUPPORTS_CPU_MIPS32_R2 30 select SUPPORTS_CPU_MIPS32_R6 31 select SUPPORTS_CPU_MIPS64_R1 32 select SUPPORTS_CPU_MIPS64_R2 33 select SUPPORTS_CPU_MIPS64_R6 34 select SUPPORTS_LITTLE_ENDIAN 35 select SWAP_IO_SPACE 36 imply CMD_DM 37 38config TARGET_VCT 39 bool "Support vct" 40 select ROM_EXCEPTION_VECTORS 41 select SUPPORTS_BIG_ENDIAN 42 select SUPPORTS_CPU_MIPS32_R1 43 select SUPPORTS_CPU_MIPS32_R2 44 select SYS_MIPS_CACHE_INIT_RAM_LOAD 45 46config ARCH_ATH79 47 bool "Support QCA/Atheros ath79" 48 select DM 49 select OF_CONTROL 50 imply CMD_DM 51 52config ARCH_MSCC 53 bool "Support MSCC VCore-III" 54 select OF_CONTROL 55 select DM 56 57config ARCH_BMIPS 58 bool "Support BMIPS SoCs" 59 select CLK 60 select CPU 61 select DM 62 select OF_CONTROL 63 select RAM 64 select SYSRESET 65 imply CMD_DM 66 67config ARCH_MTMIPS 68 bool "Support MediaTek MIPS platforms" 69 select CLK 70 imply CMD_DM 71 select DISPLAY_CPUINFO 72 select DM 73 imply DM_ETH 74 imply DM_GPIO 75 select DM_RESET 76 select DM_SERIAL 77 select PINCTRL 78 select PINMUX 79 select PINCONF 80 select RESET_MTMIPS 81 imply DM_SPI 82 imply DM_SPI_FLASH 83 select LAST_STAGE_INIT 84 select MIPS_TUNE_24KC 85 select OF_CONTROL 86 select ROM_EXCEPTION_VECTORS 87 select SUPPORTS_CPU_MIPS32_R1 88 select SUPPORTS_CPU_MIPS32_R2 89 select SUPPORTS_LITTLE_ENDIAN 90 select SUPPORT_SPL 91 92config ARCH_JZ47XX 93 bool "Support Ingenic JZ47xx" 94 select SUPPORT_SPL 95 select OF_CONTROL 96 select DM 97 98config ARCH_OCTEON 99 bool "Support Marvell Octeon CN7xxx platforms" 100 select CPU_CAVIUM_OCTEON 101 select DISPLAY_CPUINFO 102 select DMA_ADDR_T_64BIT 103 select DM 104 select DM_ETH 105 select DM_GPIO 106 select DM_I2C 107 select DM_SERIAL 108 select DM_SPI 109 select MIPS_L2_CACHE 110 select MIPS_MACH_EARLY_INIT 111 select MIPS_TUNE_OCTEON3 112 select ROM_EXCEPTION_VECTORS 113 select SUPPORTS_BIG_ENDIAN 114 select SUPPORTS_CPU_MIPS64_OCTEON 115 select PHYS_64BIT 116 select OF_CONTROL 117 select OF_LIVE 118 imply CMD_DM 119 120config MACH_PIC32 121 bool "Support Microchip PIC32" 122 select DM 123 select OF_CONTROL 124 imply CMD_DM 125 126config TARGET_BOSTON 127 bool "Support Boston" 128 select DM 129 select DM_SERIAL 130 select MIPS_CM 131 select MIPS_L1_CACHE_SHIFT_6 132 select MIPS_L2_CACHE 133 select OF_BOARD_SETUP 134 select OF_CONTROL 135 select ROM_EXCEPTION_VECTORS 136 select SUPPORTS_BIG_ENDIAN 137 select SUPPORTS_CPU_MIPS32_R1 138 select SUPPORTS_CPU_MIPS32_R2 139 select SUPPORTS_CPU_MIPS32_R6 140 select SUPPORTS_CPU_MIPS64_R1 141 select SUPPORTS_CPU_MIPS64_R2 142 select SUPPORTS_CPU_MIPS64_R6 143 select SUPPORTS_LITTLE_ENDIAN 144 imply CMD_DM 145 146config TARGET_XILFPGA 147 bool "Support Imagination Xilfpga" 148 select DM 149 select DM_ETH 150 select DM_GPIO 151 select DM_SERIAL 152 select MIPS_L1_CACHE_SHIFT_4 153 select OF_CONTROL 154 select ROM_EXCEPTION_VECTORS 155 select SUPPORTS_CPU_MIPS32_R1 156 select SUPPORTS_CPU_MIPS32_R2 157 select SUPPORTS_LITTLE_ENDIAN 158 imply CMD_DM 159 help 160 This supports IMGTEC MIPSfpga platform 161 162endchoice 163 164source "board/imgtec/boston/Kconfig" 165source "board/imgtec/malta/Kconfig" 166source "board/imgtec/xilfpga/Kconfig" 167source "arch/mips/mach-ath79/Kconfig" 168source "arch/mips/mach-mscc/Kconfig" 169source "arch/mips/mach-bmips/Kconfig" 170source "arch/mips/mach-jz47xx/Kconfig" 171source "arch/mips/mach-pic32/Kconfig" 172source "arch/mips/mach-mtmips/Kconfig" 173source "arch/mips/mach-octeon/Kconfig" 174 175if MIPS 176 177choice 178 prompt "Endianness selection" 179 help 180 Some MIPS boards can be configured for either little or big endian 181 byte order. These modes require different U-Boot images. In general there 182 is one preferred byteorder for a particular system but some systems are 183 just as commonly used in the one or the other endianness. 184 185config SYS_BIG_ENDIAN 186 bool "Big endian" 187 depends on SUPPORTS_BIG_ENDIAN 188 189config SYS_LITTLE_ENDIAN 190 bool "Little endian" 191 depends on SUPPORTS_LITTLE_ENDIAN 192 193endchoice 194 195choice 196 prompt "CPU selection" 197 default CPU_MIPS32_R2 198 199config CPU_MIPS32_R1 200 bool "MIPS32 Release 1" 201 depends on SUPPORTS_CPU_MIPS32_R1 202 select 32BIT 203 help 204 Choose this option to build an U-Boot for release 1 through 5 of the 205 MIPS32 architecture. 206 207config CPU_MIPS32_R2 208 bool "MIPS32 Release 2" 209 depends on SUPPORTS_CPU_MIPS32_R2 210 select 32BIT 211 help 212 Choose this option to build an U-Boot for release 2 through 5 of the 213 MIPS32 architecture. 214 215config CPU_MIPS32_R6 216 bool "MIPS32 Release 6" 217 depends on SUPPORTS_CPU_MIPS32_R6 218 select 32BIT 219 help 220 Choose this option to build an U-Boot for release 6 or later of the 221 MIPS32 architecture. 222 223config CPU_MIPS64_R1 224 bool "MIPS64 Release 1" 225 depends on SUPPORTS_CPU_MIPS64_R1 226 select 64BIT 227 help 228 Choose this option to build a kernel for release 1 through 5 of the 229 MIPS64 architecture. 230 231config CPU_MIPS64_R2 232 bool "MIPS64 Release 2" 233 depends on SUPPORTS_CPU_MIPS64_R2 234 select 64BIT 235 help 236 Choose this option to build a kernel for release 2 through 5 of the 237 MIPS64 architecture. 238 239config CPU_MIPS64_R6 240 bool "MIPS64 Release 6" 241 depends on SUPPORTS_CPU_MIPS64_R6 242 select 64BIT 243 help 244 Choose this option to build a kernel for release 6 or later of the 245 MIPS64 architecture. 246 247config CPU_MIPS64_OCTEON 248 bool "Marvell Octeon series of CPUs" 249 depends on SUPPORTS_CPU_MIPS64_OCTEON 250 select 64BIT 251 help 252 Choose this option for Marvell Octeon CPUs. These CPUs are between 253 MIPS64 R5 and R6 with other extensions. 254 255endchoice 256 257menu "General setup" 258 259config ROM_EXCEPTION_VECTORS 260 bool "Build U-Boot image with exception vectors" 261 help 262 Enable this to include exception vectors in the U-Boot image. This is 263 required if the U-Boot entry point is equal to the address of the 264 CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, 265 U-Boot booted from parallel NOR flash). 266 Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). 267 In that case the image size will be reduced by 0x500 bytes. 268 269config MIPS_CM_BASE 270 hex "MIPS CM GCR Base Address" 271 depends on MIPS_CM 272 default 0x16100000 if TARGET_BOSTON 273 default 0x1fbf8000 274 help 275 The physical base address at which to map the MIPS Coherence Manager 276 Global Configuration Registers (GCRs). This should be set such that 277 the GCRs occupy a region of the physical address space which is 278 otherwise unused, or at minimum that software doesn't need to access. 279 280config MIPS_CACHE_INDEX_BASE 281 hex "Index base address for cache initialisation" 282 default 0x80000000 if CPU_MIPS32 283 default 0xffffffff80000000 if CPU_MIPS64 284 help 285 This is the base address for a memory block, which is used for 286 initialising the cache lines. This is also the base address of a memory 287 block which is used for loading and filling cache lines when 288 SYS_MIPS_CACHE_INIT_RAM_LOAD is selected. 289 Normally this is CKSEG0. If the MIPS system needs to move this block 290 to some SRAM or ScratchPad RAM, adapt this option accordingly. 291 292config MIPS_MACH_EARLY_INIT 293 bool "Enable mach specific very early init code" 294 help 295 Use this to enable the call to mips_mach_early_init() very early 296 from start.S. This function can be used e.g. to do some very early 297 CPU / SoC intitialization or image copying. Its called very early 298 and at this stage the PC might not match the linking address 299 (CONFIG_TEXT_BASE) - no absolute jump done until this call. 300 301config MIPS_CACHE_SETUP 302 bool "Allow generic start code to initialize and setup caches" 303 default n if SKIP_LOWLEVEL_INIT 304 default y 305 help 306 This allows the generic start code to invoke the generic initialization 307 of the CPU caches. Disabling this can be useful for RAM boot scenarios 308 (EJTAG, SPL payload) or for machines which don't need cache initialization 309 or which want to provide their own cache implementation. 310 311 If unsure, say yes. 312 313config MIPS_CACHE_DISABLE 314 bool "Allow generic start code to initially disable caches" 315 default n if SKIP_LOWLEVEL_INIT 316 default y 317 help 318 This allows the generic start code to initially disable the CPU caches 319 and run uncached until the caches are initialized and enabled. Disabling 320 this can be useful on machines which don't need cache initialization or 321 which want to provide their own cache implementation. 322 323 If unsure, say yes. 324 325config MIPS_RELOCATION_TABLE_SIZE 326 hex "Relocation table size" 327 range 0x100 0x10000 328 default "0x8000" 329 ---help--- 330 A table of relocation data will be appended to the U-Boot binary 331 and parsed in relocate_code() to fix up all offsets in the relocated 332 U-Boot. 333 334 This option allows the amount of space reserved for the table to be 335 adjusted in a range from 256 up to 64k. The default is 32k and should 336 be ok in most cases. Reduce this value to shrink the size of U-Boot 337 binary. 338 339 The build will fail and a valid size suggested if this is too small. 340 341 If unsure, leave at the default value. 342 343config RESTORE_EXCEPTION_VECTOR_BASE 344 bool "Restore exception vector base before booting linux kernel" 345 default n 346 help 347 In U-Boot the exception vector base will be moved to top of memory, 348 to be used to display register dump when exception occurs. 349 But some old linux kernel does not honor the base set in CP0_EBASE. 350 A modified exception vector base will cause kernel crash. 351 352 This option will restore the exception vector base to its previous 353 value. 354 355 If unsure, say N. 356 357config OVERRIDE_EXCEPTION_VECTOR_BASE 358 bool "Override the exception vector base to be restored" 359 depends on RESTORE_EXCEPTION_VECTOR_BASE 360 default n 361 help 362 Enable this option if you want to use a different exception vector 363 base rather than the previously saved one. 364 365config NEW_EXCEPTION_VECTOR_BASE 366 hex "New exception vector base" 367 depends on OVERRIDE_EXCEPTION_VECTOR_BASE 368 range 0x80000000 0xbffff000 369 default 0x80000000 370 help 371 The exception vector base to be restored before booting linux kernel 372 373config INIT_STACK_WITHOUT_MALLOC_F 374 bool "Do not reserve malloc space on initial stack" 375 default n 376 help 377 Enable this option if you don't want to reserve malloc space on 378 initial stack. This is useful if the initial stack can't hold large 379 malloc space. Platform should set the malloc_base later when DRAM is 380 ready to use. 381 382config SPL_INIT_STACK_WITHOUT_MALLOC_F 383 bool "Do not reserve malloc space on initial stack in SPL" 384 default n 385 help 386 Enable this option if you don't want to reserve malloc space on 387 initial stack. This is useful if the initial stack can't hold large 388 malloc space. Platform should set the malloc_base later when DRAM is 389 ready to use. 390 391config SPL_LOADER_SUPPORT 392 bool 393 default n 394 help 395 Enable this option if you want to use SPL loaders without DM enabled. 396 397endmenu 398 399menu "OS boot interface" 400 401config MIPS_BOOT_CMDLINE_LEGACY 402 bool "Hand over legacy command line to Linux kernel" 403 default y 404 help 405 Enable this option if you want U-Boot to hand over the Yamon-style 406 command line to the kernel. All bootargs will be prepared as argc/argv 407 compatible list. The argument count (argc) is stored in register $a0. 408 The address of the argument list (argv) is stored in register $a1. 409 410config MIPS_BOOT_ENV_LEGACY 411 bool "Hand over legacy environment to Linux kernel" 412 default y 413 help 414 Enable this option if you want U-Boot to hand over the Yamon-style 415 environment to the kernel. Information like memory size, initrd 416 address and size will be prepared as zero-terminated key/value list. 417 The address of the environment is stored in register $a2. 418 419config MIPS_BOOT_FDT 420 bool "Hand over a flattened device tree to Linux kernel" 421 default n 422 help 423 Enable this option if you want U-Boot to hand over a flattened 424 device tree to the kernel. According to UHI register $a0 will be set 425 to -2 and the FDT address is stored in $a1. 426 427endmenu 428 429config SUPPORTS_BIG_ENDIAN 430 bool 431 432config SUPPORTS_LITTLE_ENDIAN 433 bool 434 435config SUPPORTS_CPU_MIPS32_R1 436 bool 437 438config SUPPORTS_CPU_MIPS32_R2 439 bool 440 441config SUPPORTS_CPU_MIPS32_R6 442 bool 443 444config SUPPORTS_CPU_MIPS64_R1 445 bool 446 447config SUPPORTS_CPU_MIPS64_R2 448 bool 449 450config SUPPORTS_CPU_MIPS64_R6 451 bool 452 453config SUPPORTS_CPU_MIPS64_OCTEON 454 bool 455 456config CPU_CAVIUM_OCTEON 457 bool 458 459config CPU_MIPS32 460 bool 461 default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R6 462 463config CPU_MIPS64 464 bool 465 default y if CPU_MIPS64_R1 || CPU_MIPS64_R2 || CPU_MIPS64_R6 466 default y if CPU_MIPS64_OCTEON 467 468config MIPS_TUNE_4KC 469 bool 470 471config MIPS_TUNE_14KC 472 bool 473 474config MIPS_TUNE_24KC 475 bool 476 477config MIPS_TUNE_34KC 478 bool 479 480config MIPS_TUNE_74KC 481 bool 482 483config MIPS_TUNE_OCTEON3 484 bool 485 486config 32BIT 487 bool 488 489config 64BIT 490 bool 491 492config SWAP_IO_SPACE 493 bool 494 495config SYS_MIPS_CACHE_INIT_RAM_LOAD 496 bool 497 498config MIPS_INIT_STACK_IN_SRAM 499 bool 500 default n 501 help 502 Select this if the initial stack frame could be setup in SRAM. 503 Normally the initial stack frame is set up in DRAM which is often 504 only available after lowlevel_init. With this option the initial 505 stack frame and the early C environment is set up before 506 lowlevel_init. Thus lowlevel_init does not need to be implemented 507 in assembler. 508 509config MIPS_SRAM_INIT 510 bool 511 default n 512 depends on MIPS_INIT_STACK_IN_SRAM 513 help 514 Select this if the SRAM for initial stack needs to be initialized 515 before it can be used. If enabled, a function mips_sram_init() will 516 be called just before setup_stack_gd. 517 518config DMA_ADDR_T_64BIT 519 bool 520 help 521 Select this to enable 64-bit DMA addressing 522 523config SYS_DCACHE_SIZE 524 int 525 default 0 526 help 527 The total size of the L1 Dcache, if known at compile time. 528 529config SYS_DCACHE_LINE_SIZE 530 int 531 default 0 532 help 533 The size of L1 Dcache lines, if known at compile time. 534 535config SYS_ICACHE_SIZE 536 int 537 default 0 538 help 539 The total size of the L1 ICache, if known at compile time. 540 541config SYS_ICACHE_LINE_SIZE 542 int 543 default 0 544 help 545 The size of L1 Icache lines, if known at compile time. 546 547config SYS_SCACHE_LINE_SIZE 548 int 549 default 0 550 help 551 The size of L2 cache lines, if known at compile time. 552 553 554config SYS_CACHE_SIZE_AUTO 555 def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \ 556 SYS_DCACHE_LINE_SIZE = 0 && SYS_ICACHE_LINE_SIZE = 0 && \ 557 SYS_SCACHE_LINE_SIZE = 0 558 help 559 Select this (or let it be auto-selected by not defining any cache 560 sizes) in order to allow U-Boot to automatically detect the sizes 561 of caches at runtime. This has a small cost in code size & runtime 562 so if you know the cache configuration for your system at compile 563 time it would be beneficial to configure it. 564 565config MIPS_L1_CACHE_SHIFT_4 566 bool 567 568config MIPS_L1_CACHE_SHIFT_5 569 bool 570 571config MIPS_L1_CACHE_SHIFT_6 572 bool 573 574config MIPS_L1_CACHE_SHIFT_7 575 bool 576 577config MIPS_L1_CACHE_SHIFT 578 int 579 default "7" if MIPS_L1_CACHE_SHIFT_7 580 default "6" if MIPS_L1_CACHE_SHIFT_6 581 default "5" if MIPS_L1_CACHE_SHIFT_5 582 default "4" if MIPS_L1_CACHE_SHIFT_4 583 default "5" 584 585config MIPS_L2_CACHE 586 bool 587 help 588 Select this if your system includes an L2 cache and you want U-Boot 589 to initialise & maintain it. 590 591config DYNAMIC_IO_PORT_BASE 592 bool 593 594config MIPS_CM 595 bool 596 help 597 Select this if your system contains a MIPS Coherence Manager and you 598 wish U-Boot to configure it or make use of it to retrieve system 599 information such as cache configuration. 600 601config MIPS_INSERT_BOOT_CONFIG 602 bool 603 default n 604 help 605 Enable this to insert some board-specific boot configuration in 606 the U-Boot binary at offset 0x10. 607 608config MIPS_BOOT_CONFIG_WORD0 609 hex 610 depends on MIPS_INSERT_BOOT_CONFIG 611 default 0x420 if TARGET_MALTA 612 default 0x0 613 help 614 Value which is inserted as boot config word 0. 615 616config MIPS_BOOT_CONFIG_WORD1 617 hex 618 depends on MIPS_INSERT_BOOT_CONFIG 619 default 0x0 620 help 621 Value which is inserted as boot config word 1. 622 623endif 624 625endmenu 626