1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Timesys Corporation
4 * Copyright 2015 General Electric Company
5 * Copyright 2012 Freescale Semiconductor, Inc.
6 */
7
8 #include <image.h>
9 #include <init.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <env.h>
15 #include <asm/global_data.h>
16 #include <linux/delay.h>
17 #include <linux/errno.h>
18 #include <linux/libfdt.h>
19 #include <asm/gpio.h>
20 #include <asm/mach-imx/iomux-v3.h>
21 #include <asm/mach-imx/boot_mode.h>
22 #include <asm/mach-imx/video.h>
23 #include <mmc.h>
24 #include <fsl_esdhc_imx.h>
25 #include <miiphy.h>
26 #include <net.h>
27 #include <netdev.h>
28 #include <asm/arch/mxc_hdmi.h>
29 #include <asm/arch/crm_regs.h>
30 #include <asm/io.h>
31 #include <asm/arch/sys_proto.h>
32 #include <power/regulator.h>
33 #include <power/da9063_pmic.h>
34 #include <power/pmic.h>
35 #include <input.h>
36 #include <pwm.h>
37 #include <version.h>
38 #include <stdlib.h>
39 #include <dm/root.h>
40 #include "../common/ge_rtc.h"
41 #include "../common/vpd_reader.h"
42 #include "../../../drivers/net/e1000.h"
43 #include <pci.h>
44 #include <panel.h>
45
46 DECLARE_GLOBAL_DATA_PTR;
47
48 #define VPD_PRODUCT_B850 1
49 #define VPD_PRODUCT_B650 2
50 #define VPD_PRODUCT_B450 3
51
52 #define AR8033_DBG_REG_ADDR 0x1d
53 #define AR8033_DBG_REG_DATA 0x1e
54 #define AR8033_SERDES_REG 0x5
55
56 static int productid; /* Default to generic. */
57 static struct vpd_cache vpd;
58
59 #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
60 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
61 PAD_CTL_HYS)
62
dram_init(void)63 int dram_init(void)
64 {
65 gd->ram_size = imx_ddr_size();
66
67 return 0;
68 }
69
board_phy_config(struct phy_device * phydev)70 int board_phy_config(struct phy_device *phydev)
71 {
72 /*
73 * Set reserved bits to avoid board specific voltage peak issue. The
74 * value is a magic number provided directly by Qualcomm. Note, that
75 * PHY driver will take control of BIT(8) in this register to control
76 * TX clock delay, so we do not initialize that bit here.
77 */
78 phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG);
79 phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47);
80
81 if (phydev->drv->config)
82 phydev->drv->config(phydev);
83
84 return 0;
85 }
86
87 #if defined(CONFIG_VIDEO_IPUV3)
do_enable_backlight(struct display_info_t const * dev)88 static void do_enable_backlight(struct display_info_t const *dev)
89 {
90 struct udevice *panel;
91 int ret;
92
93 ret = uclass_get_device(UCLASS_PANEL, 0, &panel);
94 if (ret) {
95 printf("Could not find panel: %d\n", ret);
96 return;
97 }
98
99 panel_set_backlight(panel, 100);
100 panel_enable_backlight(panel);
101 }
102
do_enable_hdmi(struct display_info_t const * dev)103 static void do_enable_hdmi(struct display_info_t const *dev)
104 {
105 imx_enable_hdmi_phy();
106 }
107
is_b850v3(void)108 static int is_b850v3(void)
109 {
110 return productid == VPD_PRODUCT_B850;
111 }
112
detect_lcd(struct display_info_t const * dev)113 static int detect_lcd(struct display_info_t const *dev)
114 {
115 return !is_b850v3();
116 }
117
118 struct display_info_t const displays[] = {{
119 .bus = -1,
120 .addr = -1,
121 .pixfmt = IPU_PIX_FMT_RGB24,
122 .detect = detect_lcd,
123 .enable = do_enable_backlight,
124 .mode = {
125 .name = "G121X1-L03",
126 .refresh = 60,
127 .xres = 1024,
128 .yres = 768,
129 .pixclock = 15385,
130 .left_margin = 20,
131 .right_margin = 300,
132 .upper_margin = 30,
133 .lower_margin = 8,
134 .hsync_len = 1,
135 .vsync_len = 1,
136 .sync = FB_SYNC_EXT,
137 .vmode = FB_VMODE_NONINTERLACED
138 } }, {
139 .bus = -1,
140 .addr = 3,
141 .pixfmt = IPU_PIX_FMT_RGB24,
142 .detect = detect_hdmi,
143 .enable = do_enable_hdmi,
144 .mode = {
145 .name = "HDMI",
146 .refresh = 60,
147 .xres = 1024,
148 .yres = 768,
149 .pixclock = 15385,
150 .left_margin = 220,
151 .right_margin = 40,
152 .upper_margin = 21,
153 .lower_margin = 7,
154 .hsync_len = 60,
155 .vsync_len = 10,
156 .sync = FB_SYNC_EXT,
157 .vmode = FB_VMODE_NONINTERLACED
158 } } };
159 size_t display_count = ARRAY_SIZE(displays);
160
enable_videopll(void)161 static void enable_videopll(void)
162 {
163 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
164 s32 timeout = 100000;
165
166 setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
167
168 /* PLL_VIDEO 455MHz (24MHz * (37+11/12) / 2)
169 * |
170 * PLL5
171 * |
172 * CS2CDR[LDB_DI0_CLK_SEL]
173 * |
174 * +----> LDB_DI0_SERIAL_CLK_ROOT
175 * |
176 * +--> CSCMR2[LDB_DI0_IPU_DIV] --> LDB_DI0_IPU 455 / 7 = 65 MHz
177 */
178
179 clrsetbits_le32(&ccm->analog_pll_video,
180 BM_ANADIG_PLL_VIDEO_DIV_SELECT |
181 BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
182 BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
183 BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1));
184
185 writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
186 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
187
188 clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
189
190 while (timeout--)
191 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
192 break;
193
194 if (timeout < 0)
195 printf("Warning: video pll lock timeout!\n");
196
197 clrsetbits_le32(&ccm->analog_pll_video,
198 BM_ANADIG_PLL_VIDEO_BYPASS,
199 BM_ANADIG_PLL_VIDEO_ENABLE);
200 }
201
setup_display_b850v3(void)202 static void setup_display_b850v3(void)
203 {
204 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
205 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
206
207 enable_videopll();
208
209 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
210 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
211
212 imx_setup_hdmi();
213
214 /* Set LDB_DI0 as clock source for IPU_DI0 */
215 clrsetbits_le32(&mxc_ccm->chsccdr,
216 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
217 (CHSCCDR_CLK_SEL_LDB_DI0 <<
218 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
219
220 /* Turn on IPU LDB DI0 clocks */
221 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
222
223 enable_ipu_clock();
224
225 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
226 IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
227 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
228 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
229 IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
230 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
231 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
232 IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
233 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
234 IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
235 &iomux->gpr[2]);
236
237 clrbits_le32(&iomux->gpr[3],
238 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
239 IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
240 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
241 }
242
setup_display_bx50v3(void)243 static void setup_display_bx50v3(void)
244 {
245 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
246 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
247
248 enable_videopll();
249
250 /* When a reset/reboot is performed the display power needs to be turned
251 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
252 * an additional 200ms here. Unfortunately we use external PMIC for
253 * doing the reset, so can not differentiate between POR vs soft reset
254 */
255 mdelay(200);
256
257 /* IPU1 DI0 clock is 455MHz / 7 = 65MHz */
258 setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
259
260 /* Set LDB_DI0 as clock source for IPU_DI0 */
261 clrsetbits_le32(&mxc_ccm->chsccdr,
262 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
263 (CHSCCDR_CLK_SEL_LDB_DI0 <<
264 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
265
266 /* Turn on IPU LDB DI0 clocks */
267 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
268
269 enable_ipu_clock();
270
271 writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
272 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
273 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
274 IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
275 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
276 &iomux->gpr[2]);
277
278 clrsetbits_le32(&iomux->gpr[3],
279 IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
280 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
281 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
282 }
283 #endif /* CONFIG_VIDEO_IPUV3 */
284
285 /*
286 * Do not overwrite the console
287 * Use always serial for U-Boot console
288 */
overwrite_console(void)289 int overwrite_console(void)
290 {
291 return 1;
292 }
293
294 #define VPD_TYPE_INVALID 0x00
295 #define VPD_BLOCK_NETWORK 0x20
296 #define VPD_BLOCK_HWID 0x44
297 #define VPD_HAS_MAC1 0x1
298 #define VPD_HAS_MAC2 0x2
299 #define VPD_MAC_ADDRESS_LENGTH 6
300
301 struct vpd_cache {
302 bool is_read;
303 u8 product_id;
304 u8 has;
305 unsigned char mac1[VPD_MAC_ADDRESS_LENGTH];
306 unsigned char mac2[VPD_MAC_ADDRESS_LENGTH];
307 };
308
309 /*
310 * Extracts MAC and product information from the VPD.
311 */
vpd_callback(struct vpd_cache * vpd,u8 id,u8 version,u8 type,size_t size,u8 const * data)312 static int vpd_callback(struct vpd_cache *vpd, u8 id, u8 version, u8 type,
313 size_t size, u8 const *data)
314 {
315 if (id == VPD_BLOCK_HWID && version == 1 && type != VPD_TYPE_INVALID &&
316 size >= 1) {
317 vpd->product_id = data[0];
318 } else if (id == VPD_BLOCK_NETWORK && version == 1 &&
319 type != VPD_TYPE_INVALID) {
320 if (size >= 6) {
321 vpd->has |= VPD_HAS_MAC1;
322 memcpy(vpd->mac1, data, VPD_MAC_ADDRESS_LENGTH);
323 }
324 if (size >= 12) {
325 vpd->has |= VPD_HAS_MAC2;
326 memcpy(vpd->mac2, data + 6, VPD_MAC_ADDRESS_LENGTH);
327 }
328 }
329
330 return 0;
331 }
332
process_vpd(struct vpd_cache * vpd)333 static void process_vpd(struct vpd_cache *vpd)
334 {
335 int fec_index = 0;
336 int i210_index = -1;
337
338 if (!vpd->is_read) {
339 printf("VPD wasn't read");
340 return;
341 }
342
343 if (vpd->has & VPD_HAS_MAC1)
344 eth_env_set_enetaddr_by_index("eth", fec_index, vpd->mac1);
345
346 env_set("ethact", "eth0");
347
348 switch (vpd->product_id) {
349 case VPD_PRODUCT_B450:
350 i210_index = 1;
351 break;
352 case VPD_PRODUCT_B650:
353 i210_index = 1;
354 break;
355 case VPD_PRODUCT_B850:
356 i210_index = 2;
357 break;
358 }
359
360 if (i210_index >= 0 && (vpd->has & VPD_HAS_MAC2))
361 eth_env_set_enetaddr_by_index("eth", i210_index, vpd->mac2);
362 }
363
364 static iomux_v3_cfg_t const misc_pads[] = {
365 MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
366 MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
367 MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
368 MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
369 MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
370 MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
371 MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
372 MX6_PAD_GPIO_9__WDOG1_B | MUX_PAD_CTRL(NC_PAD_CTRL),
373 };
374 #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
375 #define PWGIN_IN IMX_GPIO_NR(4, 14)
376 #define WIFI_EN IMX_GPIO_NR(6, 14)
377
board_early_init_f(void)378 int board_early_init_f(void)
379 {
380 imx_iomux_v3_setup_multiple_pads(misc_pads,
381 ARRAY_SIZE(misc_pads));
382
383 #if defined(CONFIG_VIDEO_IPUV3)
384 /* Set LDB clock to Video PLL */
385 select_ldb_di_clock_source(MXC_PLL5_CLK);
386 #endif
387 return 0;
388 }
389
board_init(void)390 int board_init(void)
391 {
392 if (!read_i2c_vpd(&vpd, vpd_callback)) {
393 int ret, rescan;
394
395 vpd.is_read = true;
396 productid = vpd.product_id;
397
398 ret = fdtdec_resetup(&rescan);
399 if (!ret && rescan) {
400 dm_uninit();
401 dm_init_and_scan(false);
402 }
403 }
404
405 gpio_request(SUS_S3_OUT, "sus_s3_out");
406 gpio_direction_output(SUS_S3_OUT, 1);
407
408 gpio_request(PWGIN_IN, "pwgin_in");
409 gpio_direction_input(PWGIN_IN);
410
411 gpio_request(WIFI_EN, "wifi_en");
412 gpio_direction_output(WIFI_EN, 1);
413
414 #if defined(CONFIG_VIDEO_IPUV3)
415 if (is_b850v3())
416 setup_display_b850v3();
417 else
418 setup_display_bx50v3();
419 #endif
420
421 /* address of boot parameters */
422 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
423
424 return 0;
425 }
426
427 #ifdef CONFIG_CMD_BMODE
428 static const struct boot_mode board_boot_modes[] = {
429 /* 4 bit bus width */
430 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
431 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
432 {NULL, 0},
433 };
434 #endif
435
436
437 /*
438 * The SoM used by these boards has XTAL not connected despite datasheet
439 * suggesting connecting unused XTAL pins to ground. Without explicitly
440 * clearing the CRYSTAL bit the system runs unstable and sometimes reboots
441 * unexpectedly.
442 */
pmic_crystal_fix(void)443 static void pmic_crystal_fix(void)
444 {
445 struct udevice *pmic;
446 static const uint EN_32K_CRYSTAL = (1 << 3);
447
448 if (pmic_get("pmic@58", &pmic)) {
449 puts("failed to get device for PMIC\n");
450 return;
451 }
452
453 if (pmic_clrsetbits(pmic, DA9063_REG_EN_32K, EN_32K_CRYSTAL, 0) < 0) {
454 puts("failed to clear CRYSTAL bit\n");
455 return;
456 }
457 }
458
pmic_init(void)459 void pmic_init(void)
460 {
461 struct udevice *reg;
462 int ret, i;
463 static const char * const bucks[] = {
464 "bcore1",
465 "bcore2",
466 "bpro",
467 "bmem",
468 "bio",
469 "bperi",
470 };
471
472 pmic_crystal_fix();
473
474 for (i = 0; i < ARRAY_SIZE(bucks); i++) {
475 ret = regulator_get_by_devname(bucks[i], ®);
476 if (reg < 0) {
477 printf("%s(): Unable to get regulator %s: %d\n",
478 __func__, bucks[i], ret);
479 continue;
480 }
481 regulator_set_mode(reg, DA9063_BUCKMODE_SYNC);
482 }
483 }
484
detect_boot_cause(void)485 static void detect_boot_cause(void)
486 {
487 const char *cause = "POR";
488
489 if (is_b850v3())
490 if (!gpio_get_value(PWGIN_IN))
491 cause = "PM_WDOG";
492
493 env_set("bootcause", cause);
494 }
495
board_late_init(void)496 int board_late_init(void)
497 {
498 process_vpd(&vpd);
499
500 #ifdef CONFIG_CMD_BMODE
501 add_board_boot_modes(board_boot_modes);
502 #endif
503
504 if (is_b850v3())
505 env_set("videoargs", "video=DP-1:1024x768@60 video=HDMI-A-1:1024x768@60");
506 else
507 env_set("videoargs", "video=LVDS-1:1024x768@65");
508
509 detect_boot_cause();
510
511 /* board specific pmic init */
512 pmic_init();
513
514 check_time();
515
516 pci_init();
517
518 return 0;
519 }
520
521 /*
522 * Removes the 'eth[0-9]*addr' environment variable with the given index
523 *
524 * @param index [in] the index of the eth_device whose variable is to be removed
525 */
remove_ethaddr_env_var(int index)526 static void remove_ethaddr_env_var(int index)
527 {
528 char env_var_name[9];
529
530 sprintf(env_var_name, index == 0 ? "ethaddr" : "eth%daddr", index);
531 env_set(env_var_name, NULL);
532 }
533
last_stage_init(void)534 int last_stage_init(void)
535 {
536 int i;
537
538 /*
539 * Remove first three ethaddr which may have been created by
540 * function process_vpd().
541 */
542 for (i = 0; i < 3; ++i)
543 remove_ethaddr_env_var(i);
544
545 return 0;
546 }
547
checkboard(void)548 int checkboard(void)
549 {
550 printf("BOARD: %s\n", CONFIG_BOARD_NAME);
551 return 0;
552 }
553
554 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,struct bd_info * bd)555 int ft_board_setup(void *blob, struct bd_info *bd)
556 {
557 char *rtc_status = env_get("rtc_status");
558
559 fdt_setprop(blob, 0, "ge,boot-ver", version_string,
560 strlen(version_string) + 1);
561
562 fdt_setprop(blob, 0, "ge,rtc-status", rtc_status,
563 strlen(rtc_status) + 1);
564 return 0;
565 }
566 #endif
567
board_fit_config_name_match(const char * name)568 int board_fit_config_name_match(const char *name)
569 {
570 const char *machine = name;
571
572 if (!vpd.is_read)
573 return strcmp(name, "imx6q-bx50v3");
574
575 if (!strncmp(machine, "Boot ", 5))
576 machine += 5;
577 if (!strncmp(machine, "imx6q-", 6))
578 machine += 6;
579
580 switch (vpd.product_id) {
581 case VPD_PRODUCT_B450:
582 return strcasecmp(machine, "b450v3");
583 case VPD_PRODUCT_B650:
584 return strcasecmp(machine, "b650v3");
585 case VPD_PRODUCT_B850:
586 return strcasecmp(machine, "b850v3");
587 default:
588 return -1;
589 }
590 }
591
embedded_dtb_select(void)592 int embedded_dtb_select(void)
593 {
594 vpd.is_read = false;
595 return fdtdec_setup();
596 }
597