1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
4 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
5 * (C) Copyright 2008 Armadeus Systems nc
6 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
7 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
8 */
9
10 #include <common.h>
11 #include <cpu_func.h>
12 #include <dm.h>
13 #include <env.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <memalign.h>
17 #include <miiphy.h>
18 #include <net.h>
19 #include <netdev.h>
20 #include <asm/cache.h>
21 #include <asm/global_data.h>
22 #include <linux/delay.h>
23 #include <power/regulator.h>
24
25 #include <asm/io.h>
26 #include <linux/errno.h>
27 #include <linux/compiler.h>
28
29 #include <asm/arch/clock.h>
30 #include <asm/arch/imx-regs.h>
31 #include <asm/mach-imx/sys_proto.h>
32 #include <asm-generic/gpio.h>
33
34 #include "fec_mxc.h"
35 #include <eth_phy.h>
36
37 DECLARE_GLOBAL_DATA_PTR;
38
39 /*
40 * Timeout the transfer after 5 mS. This is usually a bit more, since
41 * the code in the tightloops this timeout is used in adds some overhead.
42 */
43 #define FEC_XFER_TIMEOUT 5000
44
45 /*
46 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
47 * 64-byte alignment in the DMA RX FEC buffer.
48 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
49 * satisfies the alignment on other SoCs (32-bytes)
50 */
51 #define FEC_DMA_RX_MINALIGN 64
52
53 #ifndef CONFIG_MII
54 #error "CONFIG_MII has to be defined!"
55 #endif
56
57 #ifndef CONFIG_FEC_XCV_TYPE
58 #define CONFIG_FEC_XCV_TYPE MII100
59 #endif
60
61 /*
62 * The i.MX28 operates with packets in big endian. We need to swap them before
63 * sending and after receiving.
64 */
65 #ifdef CONFIG_MX28
66 #define CONFIG_FEC_MXC_SWAP_PACKET
67 #endif
68
69 #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))
70
71 /* Check various alignment issues at compile time */
72 #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
73 #error "ARCH_DMA_MINALIGN must be multiple of 16!"
74 #endif
75
76 #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
77 (PKTALIGN % ARCH_DMA_MINALIGN != 0))
78 #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
79 #endif
80
81 #undef DEBUG
82
83 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
swap_packet(uint32_t * packet,int length)84 static void swap_packet(uint32_t *packet, int length)
85 {
86 int i;
87
88 for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
89 packet[i] = __swab32(packet[i]);
90 }
91 #endif
92
93 /* MII-interface related functions */
fec_mdio_read(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr)94 static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
95 uint8_t regaddr)
96 {
97 uint32_t reg; /* convenient holder for the PHY register */
98 uint32_t phy; /* convenient holder for the PHY */
99 uint32_t start;
100 int val;
101
102 /*
103 * reading from any PHY's register is done by properly
104 * programming the FEC's MII data register.
105 */
106 writel(FEC_IEVENT_MII, ð->ievent);
107 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
108 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
109
110 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
111 phy | reg, ð->mii_data);
112
113 /* wait for the related interrupt */
114 start = get_timer(0);
115 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
116 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
117 printf("Read MDIO failed...\n");
118 return -1;
119 }
120 }
121
122 /* clear mii interrupt bit */
123 writel(FEC_IEVENT_MII, ð->ievent);
124
125 /* it's now safe to read the PHY's register */
126 val = (unsigned short)readl(ð->mii_data);
127 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
128 regaddr, val);
129 return val;
130 }
131
132 #ifndef imx_get_fecclk
imx_get_fecclk(void)133 u32 __weak imx_get_fecclk(void)
134 {
135 return 0;
136 }
137 #endif
138
fec_get_clk_rate(void * udev,int idx)139 static int fec_get_clk_rate(void *udev, int idx)
140 {
141 struct fec_priv *fec;
142 struct udevice *dev;
143 int ret;
144
145 if (IS_ENABLED(CONFIG_IMX8) ||
146 CONFIG_IS_ENABLED(CLK_CCF)) {
147 dev = udev;
148 if (!dev) {
149 ret = uclass_get_device(UCLASS_ETH, idx, &dev);
150 if (ret < 0) {
151 debug("Can't get FEC udev: %d\n", ret);
152 return ret;
153 }
154 }
155
156 fec = dev_get_priv(dev);
157 if (fec)
158 return fec->clk_rate;
159
160 return -EINVAL;
161 } else {
162 return imx_get_fecclk();
163 }
164 }
165
fec_mii_setspeed(struct ethernet_regs * eth)166 static void fec_mii_setspeed(struct ethernet_regs *eth)
167 {
168 /*
169 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
170 * and do not drop the Preamble.
171 *
172 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
173 * MII_SPEED) register that defines the MDIO output hold time. Earlier
174 * versions are RAZ there, so just ignore the difference and write the
175 * register always.
176 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
177 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
178 * output.
179 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
180 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
181 * holdtime cannot result in a value greater than 3.
182 */
183 u32 pclk;
184 u32 speed;
185 u32 hold;
186 int ret;
187
188 ret = fec_get_clk_rate(NULL, 0);
189 if (ret < 0) {
190 printf("Can't find FEC0 clk rate: %d\n", ret);
191 return;
192 }
193 pclk = ret;
194 speed = DIV_ROUND_UP(pclk, 5000000);
195 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
196
197 #ifdef FEC_QUIRK_ENET_MAC
198 speed--;
199 #endif
200 writel(speed << 1 | hold << 8, ð->mii_speed);
201 debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
202 }
203
fec_mdio_write(struct ethernet_regs * eth,uint8_t phyaddr,uint8_t regaddr,uint16_t data)204 static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
205 uint8_t regaddr, uint16_t data)
206 {
207 uint32_t reg; /* convenient holder for the PHY register */
208 uint32_t phy; /* convenient holder for the PHY */
209 uint32_t start;
210
211 reg = regaddr << FEC_MII_DATA_RA_SHIFT;
212 phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
213
214 writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
215 FEC_MII_DATA_TA | phy | reg | data, ð->mii_data);
216
217 /* wait for the MII interrupt */
218 start = get_timer(0);
219 while (!(readl(ð->ievent) & FEC_IEVENT_MII)) {
220 if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
221 printf("Write MDIO failed...\n");
222 return -1;
223 }
224 }
225
226 /* clear MII interrupt bit */
227 writel(FEC_IEVENT_MII, ð->ievent);
228 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
229 regaddr, data);
230
231 return 0;
232 }
233
fec_phy_read(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr)234 static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
235 int regaddr)
236 {
237 return fec_mdio_read(bus->priv, phyaddr, regaddr);
238 }
239
fec_phy_write(struct mii_dev * bus,int phyaddr,int dev_addr,int regaddr,u16 data)240 static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
241 int regaddr, u16 data)
242 {
243 return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
244 }
245
246 #ifndef CONFIG_PHYLIB
miiphy_restart_aneg(struct eth_device * dev)247 static int miiphy_restart_aneg(struct eth_device *dev)
248 {
249 int ret = 0;
250 #if !defined(CONFIG_FEC_MXC_NO_ANEG)
251 struct fec_priv *fec = (struct fec_priv *)dev->priv;
252 struct ethernet_regs *eth = fec->bus->priv;
253
254 /*
255 * Wake up from sleep if necessary
256 * Reset PHY, then delay 300ns
257 */
258 #ifdef CONFIG_MX27
259 fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
260 #endif
261 fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
262 udelay(1000);
263
264 /* Set the auto-negotiation advertisement register bits */
265 fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
266 LPA_100FULL | LPA_100HALF | LPA_10FULL |
267 LPA_10HALF | PHY_ANLPAR_PSB_802_3);
268 fec_mdio_write(eth, fec->phy_id, MII_BMCR,
269 BMCR_ANENABLE | BMCR_ANRESTART);
270
271 if (fec->mii_postcall)
272 ret = fec->mii_postcall(fec->phy_id);
273
274 #endif
275 return ret;
276 }
277
278 #ifndef CONFIG_FEC_FIXED_SPEED
miiphy_wait_aneg(struct eth_device * dev)279 static int miiphy_wait_aneg(struct eth_device *dev)
280 {
281 uint32_t start;
282 int status;
283 struct fec_priv *fec = (struct fec_priv *)dev->priv;
284 struct ethernet_regs *eth = fec->bus->priv;
285
286 /* Wait for AN completion */
287 start = get_timer(0);
288 do {
289 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
290 printf("%s: Autonegotiation timeout\n", dev->name);
291 return -1;
292 }
293
294 status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
295 if (status < 0) {
296 printf("%s: Autonegotiation failed. status: %d\n",
297 dev->name, status);
298 return -1;
299 }
300 } while (!(status & BMSR_LSTATUS));
301
302 return 0;
303 }
304 #endif /* CONFIG_FEC_FIXED_SPEED */
305 #endif
306
fec_rx_task_enable(struct fec_priv * fec)307 static int fec_rx_task_enable(struct fec_priv *fec)
308 {
309 writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
310 return 0;
311 }
312
fec_rx_task_disable(struct fec_priv * fec)313 static int fec_rx_task_disable(struct fec_priv *fec)
314 {
315 return 0;
316 }
317
fec_tx_task_enable(struct fec_priv * fec)318 static int fec_tx_task_enable(struct fec_priv *fec)
319 {
320 writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
321 return 0;
322 }
323
fec_tx_task_disable(struct fec_priv * fec)324 static int fec_tx_task_disable(struct fec_priv *fec)
325 {
326 return 0;
327 }
328
329 /**
330 * Initialize receive task's buffer descriptors
331 * @param[in] fec all we know about the device yet
332 * @param[in] count receive buffer count to be allocated
333 * @param[in] dsize desired size of each receive buffer
334 * @return 0 on success
335 *
336 * Init all RX descriptors to default values.
337 */
fec_rbd_init(struct fec_priv * fec,int count,int dsize)338 static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
339 {
340 uint32_t size;
341 ulong data;
342 int i;
343
344 /*
345 * Reload the RX descriptors with default values and wipe
346 * the RX buffers.
347 */
348 size = roundup(dsize, ARCH_DMA_MINALIGN);
349 for (i = 0; i < count; i++) {
350 data = fec->rbd_base[i].data_pointer;
351 memset((void *)data, 0, dsize);
352 flush_dcache_range(data, data + size);
353
354 fec->rbd_base[i].status = FEC_RBD_EMPTY;
355 fec->rbd_base[i].data_length = 0;
356 }
357
358 /* Mark the last RBD to close the ring. */
359 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
360 fec->rbd_index = 0;
361
362 flush_dcache_range((ulong)fec->rbd_base,
363 (ulong)fec->rbd_base + size);
364 }
365
366 /**
367 * Initialize transmit task's buffer descriptors
368 * @param[in] fec all we know about the device yet
369 *
370 * Transmit buffers are created externally. We only have to init the BDs here.\n
371 * Note: There is a race condition in the hardware. When only one BD is in
372 * use it must be marked with the WRAP bit to use it for every transmitt.
373 * This bit in combination with the READY bit results into double transmit
374 * of each data buffer. It seems the state machine checks READY earlier then
375 * resetting it after the first transfer.
376 * Using two BDs solves this issue.
377 */
fec_tbd_init(struct fec_priv * fec)378 static void fec_tbd_init(struct fec_priv *fec)
379 {
380 ulong addr = (ulong)fec->tbd_base;
381 unsigned size = roundup(2 * sizeof(struct fec_bd),
382 ARCH_DMA_MINALIGN);
383
384 memset(fec->tbd_base, 0, size);
385 fec->tbd_base[0].status = 0;
386 fec->tbd_base[1].status = FEC_TBD_WRAP;
387 fec->tbd_index = 0;
388 flush_dcache_range(addr, addr + size);
389 }
390
391 /**
392 * Mark the given read buffer descriptor as free
393 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
394 * @param[in] prbd buffer descriptor to mark free again
395 */
fec_rbd_clean(int last,struct fec_bd * prbd)396 static void fec_rbd_clean(int last, struct fec_bd *prbd)
397 {
398 unsigned short flags = FEC_RBD_EMPTY;
399 if (last)
400 flags |= FEC_RBD_WRAP;
401 writew(flags, &prbd->status);
402 writew(0, &prbd->data_length);
403 }
404
fec_get_hwaddr(int dev_id,unsigned char * mac)405 static int fec_get_hwaddr(int dev_id, unsigned char *mac)
406 {
407 imx_get_mac_from_fuse(dev_id, mac);
408 return !is_valid_ethaddr(mac);
409 }
410
411 #ifdef CONFIG_DM_ETH
fecmxc_set_hwaddr(struct udevice * dev)412 static int fecmxc_set_hwaddr(struct udevice *dev)
413 #else
414 static int fec_set_hwaddr(struct eth_device *dev)
415 #endif
416 {
417 #ifdef CONFIG_DM_ETH
418 struct fec_priv *fec = dev_get_priv(dev);
419 struct eth_pdata *pdata = dev_get_plat(dev);
420 uchar *mac = pdata->enetaddr;
421 #else
422 uchar *mac = dev->enetaddr;
423 struct fec_priv *fec = (struct fec_priv *)dev->priv;
424 #endif
425
426 writel(0, &fec->eth->iaddr1);
427 writel(0, &fec->eth->iaddr2);
428 writel(0, &fec->eth->gaddr1);
429 writel(0, &fec->eth->gaddr2);
430
431 /* Set physical address */
432 writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
433 &fec->eth->paddr1);
434 writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);
435
436 return 0;
437 }
438
439 /* Do initial configuration of the FEC registers */
fec_reg_setup(struct fec_priv * fec)440 static void fec_reg_setup(struct fec_priv *fec)
441 {
442 uint32_t rcntrl;
443
444 /* Set interrupt mask register */
445 writel(0x00000000, &fec->eth->imask);
446
447 /* Clear FEC-Lite interrupt event register(IEVENT) */
448 writel(0xffffffff, &fec->eth->ievent);
449
450 /* Set FEC-Lite receive control register(R_CNTRL): */
451
452 /* Start with frame length = 1518, common for all modes. */
453 rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
454 if (fec->xcv_type != SEVENWIRE) /* xMII modes */
455 rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
456 if (fec->xcv_type == RGMII)
457 rcntrl |= FEC_RCNTRL_RGMII;
458 else if (fec->xcv_type == RMII)
459 rcntrl |= FEC_RCNTRL_RMII;
460
461 writel(rcntrl, &fec->eth->r_cntrl);
462 }
463
464 /**
465 * Start the FEC engine
466 * @param[in] dev Our device to handle
467 */
468 #ifdef CONFIG_DM_ETH
fec_open(struct udevice * dev)469 static int fec_open(struct udevice *dev)
470 #else
471 static int fec_open(struct eth_device *edev)
472 #endif
473 {
474 #ifdef CONFIG_DM_ETH
475 struct fec_priv *fec = dev_get_priv(dev);
476 #else
477 struct fec_priv *fec = (struct fec_priv *)edev->priv;
478 #endif
479 int speed;
480 ulong addr, size;
481 int i;
482
483 debug("fec_open: fec_open(dev)\n");
484 /* full-duplex, heartbeat disabled */
485 writel(1 << 2, &fec->eth->x_cntrl);
486 fec->rbd_index = 0;
487
488 /* Invalidate all descriptors */
489 for (i = 0; i < FEC_RBD_NUM - 1; i++)
490 fec_rbd_clean(0, &fec->rbd_base[i]);
491 fec_rbd_clean(1, &fec->rbd_base[i]);
492
493 /* Flush the descriptors into RAM */
494 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
495 ARCH_DMA_MINALIGN);
496 addr = (ulong)fec->rbd_base;
497 flush_dcache_range(addr, addr + size);
498
499 #ifdef FEC_QUIRK_ENET_MAC
500 /* Enable ENET HW endian SWAP */
501 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
502 &fec->eth->ecntrl);
503 /* Enable ENET store and forward mode */
504 writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
505 &fec->eth->x_wmrk);
506 #endif
507 /* Enable FEC-Lite controller */
508 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
509 &fec->eth->ecntrl);
510
511 #ifdef FEC_ENET_ENABLE_TXC_DELAY
512 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_TXC_DLY,
513 &fec->eth->ecntrl);
514 #endif
515
516 #ifdef FEC_ENET_ENABLE_RXC_DELAY
517 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RXC_DLY,
518 &fec->eth->ecntrl);
519 #endif
520
521 #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
522 udelay(100);
523
524 /* setup the MII gasket for RMII mode */
525 /* disable the gasket */
526 writew(0, &fec->eth->miigsk_enr);
527
528 /* wait for the gasket to be disabled */
529 while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
530 udelay(2);
531
532 /* configure gasket for RMII, 50 MHz, no loopback, and no echo */
533 writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);
534
535 /* re-enable the gasket */
536 writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);
537
538 /* wait until MII gasket is ready */
539 int max_loops = 10;
540 while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
541 if (--max_loops <= 0) {
542 printf("WAIT for MII Gasket ready timed out\n");
543 break;
544 }
545 }
546 #endif
547
548 #ifdef CONFIG_PHYLIB
549 {
550 /* Start up the PHY */
551 int ret = phy_startup(fec->phydev);
552
553 if (ret) {
554 printf("Could not initialize PHY %s\n",
555 fec->phydev->dev->name);
556 return ret;
557 }
558 speed = fec->phydev->speed;
559 }
560 #elif CONFIG_FEC_FIXED_SPEED
561 speed = CONFIG_FEC_FIXED_SPEED;
562 #else
563 miiphy_wait_aneg(edev);
564 speed = miiphy_speed(edev->name, fec->phy_id);
565 miiphy_duplex(edev->name, fec->phy_id);
566 #endif
567
568 #ifdef FEC_QUIRK_ENET_MAC
569 {
570 u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
571 u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
572 if (speed == _1000BASET)
573 ecr |= FEC_ECNTRL_SPEED;
574 else if (speed != _100BASET)
575 rcr |= FEC_RCNTRL_RMII_10T;
576 writel(ecr, &fec->eth->ecntrl);
577 writel(rcr, &fec->eth->r_cntrl);
578 }
579 #endif
580 debug("%s:Speed=%i\n", __func__, speed);
581
582 /* Enable SmartDMA receive task */
583 fec_rx_task_enable(fec);
584
585 udelay(100000);
586 return 0;
587 }
588
589 #ifdef CONFIG_DM_ETH
fecmxc_init(struct udevice * dev)590 static int fecmxc_init(struct udevice *dev)
591 #else
592 static int fec_init(struct eth_device *dev, struct bd_info *bd)
593 #endif
594 {
595 #ifdef CONFIG_DM_ETH
596 struct fec_priv *fec = dev_get_priv(dev);
597 #else
598 struct fec_priv *fec = (struct fec_priv *)dev->priv;
599 #endif
600 u8 *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
601 u8 *i;
602 ulong addr;
603
604 /* Initialize MAC address */
605 #ifdef CONFIG_DM_ETH
606 fecmxc_set_hwaddr(dev);
607 #else
608 fec_set_hwaddr(dev);
609 #endif
610
611 /* Setup transmit descriptors, there are two in total. */
612 fec_tbd_init(fec);
613
614 /* Setup receive descriptors. */
615 fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
616
617 fec_reg_setup(fec);
618
619 if (fec->xcv_type != SEVENWIRE)
620 fec_mii_setspeed(fec->bus->priv);
621
622 /* Set Opcode/Pause Duration Register */
623 writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */
624 writel(0x2, &fec->eth->x_wmrk);
625
626 /* Set multicast address filter */
627 writel(0x00000000, &fec->eth->gaddr1);
628 writel(0x00000000, &fec->eth->gaddr2);
629
630 /* Do not access reserved register */
631 if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
632 /* clear MIB RAM */
633 for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
634 writel(0, i);
635
636 /* FIFO receive start register */
637 writel(0x520, &fec->eth->r_fstart);
638 }
639
640 /* size and address of each buffer */
641 writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
642
643 addr = (ulong)fec->tbd_base;
644 writel((uint32_t)addr, &fec->eth->etdsr);
645
646 addr = (ulong)fec->rbd_base;
647 writel((uint32_t)addr, &fec->eth->erdsr);
648
649 #ifndef CONFIG_PHYLIB
650 if (fec->xcv_type != SEVENWIRE)
651 miiphy_restart_aneg(dev);
652 #endif
653 fec_open(dev);
654 return 0;
655 }
656
657 /**
658 * Halt the FEC engine
659 * @param[in] dev Our device to handle
660 */
661 #ifdef CONFIG_DM_ETH
fecmxc_halt(struct udevice * dev)662 static void fecmxc_halt(struct udevice *dev)
663 #else
664 static void fec_halt(struct eth_device *dev)
665 #endif
666 {
667 #ifdef CONFIG_DM_ETH
668 struct fec_priv *fec = dev_get_priv(dev);
669 #else
670 struct fec_priv *fec = (struct fec_priv *)dev->priv;
671 #endif
672 int counter = 0xffff;
673
674 /* issue graceful stop command to the FEC transmitter if necessary */
675 writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
676 &fec->eth->x_cntrl);
677
678 debug("eth_halt: wait for stop regs\n");
679 /* wait for graceful stop to register */
680 while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
681 udelay(1);
682
683 /* Disable SmartDMA tasks */
684 fec_tx_task_disable(fec);
685 fec_rx_task_disable(fec);
686
687 /*
688 * Disable the Ethernet Controller
689 * Note: this will also reset the BD index counter!
690 */
691 writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
692 &fec->eth->ecntrl);
693 fec->rbd_index = 0;
694 fec->tbd_index = 0;
695 debug("eth_halt: done\n");
696 }
697
698 /**
699 * Transmit one frame
700 * @param[in] dev Our ethernet device to handle
701 * @param[in] packet Pointer to the data to be transmitted
702 * @param[in] length Data count in bytes
703 * @return 0 on success
704 */
705 #ifdef CONFIG_DM_ETH
fecmxc_send(struct udevice * dev,void * packet,int length)706 static int fecmxc_send(struct udevice *dev, void *packet, int length)
707 #else
708 static int fec_send(struct eth_device *dev, void *packet, int length)
709 #endif
710 {
711 unsigned int status;
712 u32 size;
713 ulong addr, end;
714 int timeout = FEC_XFER_TIMEOUT;
715 int ret = 0;
716
717 /*
718 * This routine transmits one frame. This routine only accepts
719 * 6-byte Ethernet addresses.
720 */
721 #ifdef CONFIG_DM_ETH
722 struct fec_priv *fec = dev_get_priv(dev);
723 #else
724 struct fec_priv *fec = (struct fec_priv *)dev->priv;
725 #endif
726
727 /*
728 * Check for valid length of data.
729 */
730 if ((length > 1500) || (length <= 0)) {
731 printf("Payload (%d) too large\n", length);
732 return -1;
733 }
734
735 /*
736 * Setup the transmit buffer. We are always using the first buffer for
737 * transmission, the second will be empty and only used to stop the DMA
738 * engine. We also flush the packet to RAM here to avoid cache trouble.
739 */
740 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
741 swap_packet((uint32_t *)packet, length);
742 #endif
743
744 addr = (ulong)packet;
745 end = roundup(addr + length, ARCH_DMA_MINALIGN);
746 addr &= ~(ARCH_DMA_MINALIGN - 1);
747 flush_dcache_range(addr, end);
748
749 writew(length, &fec->tbd_base[fec->tbd_index].data_length);
750 writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
751
752 /*
753 * update BD's status now
754 * This block:
755 * - is always the last in a chain (means no chain)
756 * - should transmitt the CRC
757 * - might be the last BD in the list, so the address counter should
758 * wrap (-> keep the WRAP flag)
759 */
760 status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
761 status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
762 writew(status, &fec->tbd_base[fec->tbd_index].status);
763
764 /*
765 * Flush data cache. This code flushes both TX descriptors to RAM.
766 * After this code, the descriptors will be safely in RAM and we
767 * can start DMA.
768 */
769 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
770 addr = (ulong)fec->tbd_base;
771 flush_dcache_range(addr, addr + size);
772
773 /*
774 * Below we read the DMA descriptor's last four bytes back from the
775 * DRAM. This is important in order to make sure that all WRITE
776 * operations on the bus that were triggered by previous cache FLUSH
777 * have completed.
778 *
779 * Otherwise, on MX28, it is possible to observe a corruption of the
780 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
781 * for the bus structure of MX28. The scenario is as follows:
782 *
783 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
784 * to DRAM due to flush_dcache_range()
785 * 2) ARM core writes the FEC registers via AHB_ARB2
786 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
787 *
788 * Note that 2) does sometimes finish before 1) due to reordering of
789 * WRITE accesses on the AHB bus, therefore triggering 3) before the
790 * DMA descriptor is fully written into DRAM. This results in occasional
791 * corruption of the DMA descriptor.
792 */
793 readl(addr + size - 4);
794
795 /* Enable SmartDMA transmit task */
796 fec_tx_task_enable(fec);
797
798 /*
799 * Wait until frame is sent. On each turn of the wait cycle, we must
800 * invalidate data cache to see what's really in RAM. Also, we need
801 * barrier here.
802 */
803 while (--timeout) {
804 if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
805 break;
806 }
807
808 if (!timeout) {
809 ret = -EINVAL;
810 goto out;
811 }
812
813 /*
814 * The TDAR bit is cleared when the descriptors are all out from TX
815 * but on mx6solox we noticed that the READY bit is still not cleared
816 * right after TDAR.
817 * These are two distinct signals, and in IC simulation, we found that
818 * TDAR always gets cleared prior than the READY bit of last BD becomes
819 * cleared.
820 * In mx6solox, we use a later version of FEC IP. It looks like that
821 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
822 * version.
823 *
824 * Fix this by polling the READY bit of BD after the TDAR polling,
825 * which covers the mx6solox case and does not harm the other SoCs.
826 */
827 timeout = FEC_XFER_TIMEOUT;
828 while (--timeout) {
829 invalidate_dcache_range(addr, addr + size);
830 if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
831 FEC_TBD_READY))
832 break;
833 }
834
835 if (!timeout)
836 ret = -EINVAL;
837
838 out:
839 debug("fec_send: status 0x%x index %d ret %i\n",
840 readw(&fec->tbd_base[fec->tbd_index].status),
841 fec->tbd_index, ret);
842 /* for next transmission use the other buffer */
843 if (fec->tbd_index)
844 fec->tbd_index = 0;
845 else
846 fec->tbd_index = 1;
847
848 return ret;
849 }
850
851 /**
852 * Pull one frame from the card
853 * @param[in] dev Our ethernet device to handle
854 * @return Length of packet read
855 */
856 #ifdef CONFIG_DM_ETH
fecmxc_recv(struct udevice * dev,int flags,uchar ** packetp)857 static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
858 #else
859 static int fec_recv(struct eth_device *dev)
860 #endif
861 {
862 #ifdef CONFIG_DM_ETH
863 struct fec_priv *fec = dev_get_priv(dev);
864 #else
865 struct fec_priv *fec = (struct fec_priv *)dev->priv;
866 #endif
867 struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
868 unsigned long ievent;
869 int frame_length, len = 0;
870 uint16_t bd_status;
871 ulong addr, size, end;
872 int i;
873
874 #ifdef CONFIG_DM_ETH
875 *packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
876 if (*packetp == 0) {
877 printf("%s: error allocating packetp\n", __func__);
878 return -ENOMEM;
879 }
880 #else
881 ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
882 #endif
883
884 /* Check if any critical events have happened */
885 ievent = readl(&fec->eth->ievent);
886 writel(ievent, &fec->eth->ievent);
887 debug("fec_recv: ievent 0x%lx\n", ievent);
888 if (ievent & FEC_IEVENT_BABR) {
889 #ifdef CONFIG_DM_ETH
890 fecmxc_halt(dev);
891 fecmxc_init(dev);
892 #else
893 fec_halt(dev);
894 fec_init(dev, fec->bd);
895 #endif
896 printf("some error: 0x%08lx\n", ievent);
897 return 0;
898 }
899 if (ievent & FEC_IEVENT_HBERR) {
900 /* Heartbeat error */
901 writel(0x00000001 | readl(&fec->eth->x_cntrl),
902 &fec->eth->x_cntrl);
903 }
904 if (ievent & FEC_IEVENT_GRA) {
905 /* Graceful stop complete */
906 if (readl(&fec->eth->x_cntrl) & 0x00000001) {
907 #ifdef CONFIG_DM_ETH
908 fecmxc_halt(dev);
909 #else
910 fec_halt(dev);
911 #endif
912 writel(~0x00000001 & readl(&fec->eth->x_cntrl),
913 &fec->eth->x_cntrl);
914 #ifdef CONFIG_DM_ETH
915 fecmxc_init(dev);
916 #else
917 fec_init(dev, fec->bd);
918 #endif
919 }
920 }
921
922 /*
923 * Read the buffer status. Before the status can be read, the data cache
924 * must be invalidated, because the data in RAM might have been changed
925 * by DMA. The descriptors are properly aligned to cachelines so there's
926 * no need to worry they'd overlap.
927 *
928 * WARNING: By invalidating the descriptor here, we also invalidate
929 * the descriptors surrounding this one. Therefore we can NOT change the
930 * contents of this descriptor nor the surrounding ones. The problem is
931 * that in order to mark the descriptor as processed, we need to change
932 * the descriptor. The solution is to mark the whole cache line when all
933 * descriptors in the cache line are processed.
934 */
935 addr = (ulong)rbd;
936 addr &= ~(ARCH_DMA_MINALIGN - 1);
937 size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
938 invalidate_dcache_range(addr, addr + size);
939
940 bd_status = readw(&rbd->status);
941 debug("fec_recv: status 0x%x\n", bd_status);
942
943 if (!(bd_status & FEC_RBD_EMPTY)) {
944 if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
945 ((readw(&rbd->data_length) - 4) > 14)) {
946 /* Get buffer address and size */
947 addr = readl(&rbd->data_pointer);
948 frame_length = readw(&rbd->data_length) - 4;
949 /* Invalidate data cache over the buffer */
950 end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
951 addr &= ~(ARCH_DMA_MINALIGN - 1);
952 invalidate_dcache_range(addr, end);
953
954 /* Fill the buffer and pass it to upper layers */
955 #ifdef CONFIG_FEC_MXC_SWAP_PACKET
956 swap_packet((uint32_t *)addr, frame_length);
957 #endif
958
959 #ifdef CONFIG_DM_ETH
960 memcpy(*packetp, (char *)addr, frame_length);
961 #else
962 memcpy(buff, (char *)addr, frame_length);
963 net_process_received_packet(buff, frame_length);
964 #endif
965 len = frame_length;
966 } else {
967 if (bd_status & FEC_RBD_ERR)
968 debug("error frame: 0x%08lx 0x%08x\n",
969 addr, bd_status);
970 }
971
972 /*
973 * Free the current buffer, restart the engine and move forward
974 * to the next buffer. Here we check if the whole cacheline of
975 * descriptors was already processed and if so, we mark it free
976 * as whole.
977 */
978 size = RXDESC_PER_CACHELINE - 1;
979 if ((fec->rbd_index & size) == size) {
980 i = fec->rbd_index - size;
981 addr = (ulong)&fec->rbd_base[i];
982 for (; i <= fec->rbd_index ; i++) {
983 fec_rbd_clean(i == (FEC_RBD_NUM - 1),
984 &fec->rbd_base[i]);
985 }
986 flush_dcache_range(addr,
987 addr + ARCH_DMA_MINALIGN);
988 }
989
990 fec_rx_task_enable(fec);
991 fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM;
992 }
993 debug("fec_recv: stop\n");
994
995 return len;
996 }
997
fec_set_dev_name(char * dest,int dev_id)998 static void fec_set_dev_name(char *dest, int dev_id)
999 {
1000 sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
1001 }
1002
fec_alloc_descs(struct fec_priv * fec)1003 static int fec_alloc_descs(struct fec_priv *fec)
1004 {
1005 unsigned int size;
1006 int i;
1007 uint8_t *data;
1008 ulong addr;
1009
1010 /* Allocate TX descriptors. */
1011 size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1012 fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size);
1013 if (!fec->tbd_base)
1014 goto err_tx;
1015
1016 /* Allocate RX descriptors. */
1017 size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
1018 fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size);
1019 if (!fec->rbd_base)
1020 goto err_rx;
1021
1022 memset(fec->rbd_base, 0, size);
1023
1024 /* Allocate RX buffers. */
1025
1026 /* Maximum RX buffer size. */
1027 size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN);
1028 for (i = 0; i < FEC_RBD_NUM; i++) {
1029 data = memalign(FEC_DMA_RX_MINALIGN, size);
1030 if (!data) {
1031 printf("%s: error allocating rxbuf %d\n", __func__, i);
1032 goto err_ring;
1033 }
1034
1035 memset(data, 0, size);
1036
1037 addr = (ulong)data;
1038 fec->rbd_base[i].data_pointer = (uint32_t)addr;
1039 fec->rbd_base[i].status = FEC_RBD_EMPTY;
1040 fec->rbd_base[i].data_length = 0;
1041 /* Flush the buffer to memory. */
1042 flush_dcache_range(addr, addr + size);
1043 }
1044
1045 /* Mark the last RBD to close the ring. */
1046 fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
1047
1048 fec->rbd_index = 0;
1049 fec->tbd_index = 0;
1050
1051 return 0;
1052
1053 err_ring:
1054 for (; i >= 0; i--) {
1055 addr = fec->rbd_base[i].data_pointer;
1056 free((void *)addr);
1057 }
1058 free(fec->rbd_base);
1059 err_rx:
1060 free(fec->tbd_base);
1061 err_tx:
1062 return -ENOMEM;
1063 }
1064
fec_free_descs(struct fec_priv * fec)1065 static void fec_free_descs(struct fec_priv *fec)
1066 {
1067 int i;
1068 ulong addr;
1069
1070 for (i = 0; i < FEC_RBD_NUM; i++) {
1071 addr = fec->rbd_base[i].data_pointer;
1072 free((void *)addr);
1073 }
1074 free(fec->rbd_base);
1075 free(fec->tbd_base);
1076 }
1077
fec_get_miibus(ulong base_addr,int dev_id)1078 struct mii_dev *fec_get_miibus(ulong base_addr, int dev_id)
1079 {
1080 struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
1081 struct mii_dev *bus;
1082 int ret;
1083
1084 bus = mdio_alloc();
1085 if (!bus) {
1086 printf("mdio_alloc failed\n");
1087 return NULL;
1088 }
1089 bus->read = fec_phy_read;
1090 bus->write = fec_phy_write;
1091 bus->priv = eth;
1092 fec_set_dev_name(bus->name, dev_id);
1093
1094 ret = mdio_register(bus);
1095 if (ret) {
1096 printf("mdio_register failed\n");
1097 free(bus);
1098 return NULL;
1099 }
1100 fec_mii_setspeed(eth);
1101 return bus;
1102 }
1103
1104 #ifndef CONFIG_DM_ETH
1105 #ifdef CONFIG_PHYLIB
fec_probe(struct bd_info * bd,int dev_id,uint32_t base_addr,struct mii_dev * bus,struct phy_device * phydev)1106 int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
1107 struct mii_dev *bus, struct phy_device *phydev)
1108 #else
1109 static int fec_probe(struct bd_info *bd, int dev_id, uint32_t base_addr,
1110 struct mii_dev *bus, int phy_id)
1111 #endif
1112 {
1113 struct eth_device *edev;
1114 struct fec_priv *fec;
1115 unsigned char ethaddr[6];
1116 char mac[16];
1117 uint32_t start;
1118 int ret = 0;
1119
1120 /* create and fill edev struct */
1121 edev = (struct eth_device *)malloc(sizeof(struct eth_device));
1122 if (!edev) {
1123 puts("fec_mxc: not enough malloc memory for eth_device\n");
1124 ret = -ENOMEM;
1125 goto err1;
1126 }
1127
1128 fec = (struct fec_priv *)malloc(sizeof(struct fec_priv));
1129 if (!fec) {
1130 puts("fec_mxc: not enough malloc memory for fec_priv\n");
1131 ret = -ENOMEM;
1132 goto err2;
1133 }
1134
1135 memset(edev, 0, sizeof(*edev));
1136 memset(fec, 0, sizeof(*fec));
1137
1138 ret = fec_alloc_descs(fec);
1139 if (ret)
1140 goto err3;
1141
1142 edev->priv = fec;
1143 edev->init = fec_init;
1144 edev->send = fec_send;
1145 edev->recv = fec_recv;
1146 edev->halt = fec_halt;
1147 edev->write_hwaddr = fec_set_hwaddr;
1148
1149 fec->eth = (struct ethernet_regs *)(ulong)base_addr;
1150 fec->bd = bd;
1151
1152 fec->xcv_type = CONFIG_FEC_XCV_TYPE;
1153
1154 /* Reset chip. */
1155 writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl);
1156 start = get_timer(0);
1157 while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) {
1158 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1159 printf("FEC MXC: Timeout resetting chip\n");
1160 goto err4;
1161 }
1162 udelay(10);
1163 }
1164
1165 fec_reg_setup(fec);
1166 fec_set_dev_name(edev->name, dev_id);
1167 fec->dev_id = (dev_id == -1) ? 0 : dev_id;
1168 fec->bus = bus;
1169 fec_mii_setspeed(bus->priv);
1170 #ifdef CONFIG_PHYLIB
1171 fec->phydev = phydev;
1172 phy_connect_dev(phydev, edev);
1173 /* Configure phy */
1174 phy_config(phydev);
1175 #else
1176 fec->phy_id = phy_id;
1177 #endif
1178 eth_register(edev);
1179 /* only support one eth device, the index number pointed by dev_id */
1180 edev->index = fec->dev_id;
1181
1182 if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) {
1183 debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr);
1184 memcpy(edev->enetaddr, ethaddr, 6);
1185 if (fec->dev_id)
1186 sprintf(mac, "eth%daddr", fec->dev_id);
1187 else
1188 strcpy(mac, "ethaddr");
1189 if (!env_get(mac))
1190 eth_env_set_enetaddr(mac, ethaddr);
1191 }
1192 return ret;
1193 err4:
1194 fec_free_descs(fec);
1195 err3:
1196 free(fec);
1197 err2:
1198 free(edev);
1199 err1:
1200 return ret;
1201 }
1202
fecmxc_initialize_multi(struct bd_info * bd,int dev_id,int phy_id,uint32_t addr)1203 int fecmxc_initialize_multi(struct bd_info *bd, int dev_id, int phy_id,
1204 uint32_t addr)
1205 {
1206 uint32_t base_mii;
1207 struct mii_dev *bus = NULL;
1208 #ifdef CONFIG_PHYLIB
1209 struct phy_device *phydev = NULL;
1210 #endif
1211 int ret;
1212
1213 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1214 if (enet_fused((ulong)addr)) {
1215 printf("SoC fuse indicates Ethernet@0x%x is unavailable.\n", addr);
1216 return -ENODEV;
1217 }
1218 }
1219
1220 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1221 /*
1222 * The i.MX28 has two ethernet interfaces, but they are not equal.
1223 * Only the first one can access the MDIO bus.
1224 */
1225 base_mii = CONFIG_FEC_MXC_MDIO_BASE;
1226 #else
1227 base_mii = addr;
1228 #endif
1229 debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
1230 bus = fec_get_miibus(base_mii, dev_id);
1231 if (!bus)
1232 return -ENOMEM;
1233 #ifdef CONFIG_PHYLIB
1234 phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
1235 if (!phydev) {
1236 mdio_unregister(bus);
1237 free(bus);
1238 return -ENOMEM;
1239 }
1240 ret = fec_probe(bd, dev_id, addr, bus, phydev);
1241 #else
1242 ret = fec_probe(bd, dev_id, addr, bus, phy_id);
1243 #endif
1244 if (ret) {
1245 #ifdef CONFIG_PHYLIB
1246 free(phydev);
1247 #endif
1248 mdio_unregister(bus);
1249 free(bus);
1250 }
1251 return ret;
1252 }
1253
1254 #ifdef CONFIG_FEC_MXC_PHYADDR
fecmxc_initialize(struct bd_info * bd)1255 int fecmxc_initialize(struct bd_info *bd)
1256 {
1257 return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
1258 IMX_FEC_BASE);
1259 }
1260 #endif
1261
1262 #ifndef CONFIG_PHYLIB
fecmxc_register_mii_postcall(struct eth_device * dev,int (* cb)(int))1263 int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
1264 {
1265 struct fec_priv *fec = (struct fec_priv *)dev->priv;
1266 fec->mii_postcall = cb;
1267 return 0;
1268 }
1269 #endif
1270
1271 #else
1272
fecmxc_read_rom_hwaddr(struct udevice * dev)1273 static int fecmxc_read_rom_hwaddr(struct udevice *dev)
1274 {
1275 struct fec_priv *priv = dev_get_priv(dev);
1276 struct eth_pdata *pdata = dev_get_plat(dev);
1277
1278 return fec_get_hwaddr(priv->dev_id, pdata->enetaddr);
1279 }
1280
fecmxc_free_pkt(struct udevice * dev,uchar * packet,int length)1281 static int fecmxc_free_pkt(struct udevice *dev, uchar *packet, int length)
1282 {
1283 if (packet)
1284 free(packet);
1285
1286 return 0;
1287 }
1288
1289 static const struct eth_ops fecmxc_ops = {
1290 .start = fecmxc_init,
1291 .send = fecmxc_send,
1292 .recv = fecmxc_recv,
1293 .free_pkt = fecmxc_free_pkt,
1294 .stop = fecmxc_halt,
1295 .write_hwaddr = fecmxc_set_hwaddr,
1296 .read_rom_hwaddr = fecmxc_read_rom_hwaddr,
1297 };
1298
device_get_phy_addr(struct fec_priv * priv,struct udevice * dev)1299 static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
1300 {
1301 struct ofnode_phandle_args phandle_args;
1302 int reg, ret;
1303
1304 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
1305 &phandle_args);
1306 if (ret) {
1307 debug("Failed to find phy-handle (err = %d\n)", ret);
1308 return ret;
1309 }
1310
1311 if (!ofnode_is_available(phandle_args.node))
1312 return -ENOENT;
1313
1314 priv->phy_of_node = phandle_args.node;
1315 reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
1316
1317 return reg;
1318 }
1319
fec_phy_init(struct fec_priv * priv,struct udevice * dev)1320 static int fec_phy_init(struct fec_priv *priv, struct udevice *dev)
1321 {
1322 struct phy_device *phydev;
1323 int addr;
1324
1325 addr = device_get_phy_addr(priv, dev);
1326 #ifdef CONFIG_FEC_MXC_PHYADDR
1327 addr = CONFIG_FEC_MXC_PHYADDR;
1328 #endif
1329
1330 phydev = phy_connect(priv->bus, addr, dev, priv->interface);
1331 if (!phydev)
1332 return -ENODEV;
1333
1334 priv->phydev = phydev;
1335 priv->phydev->node = priv->phy_of_node;
1336 phy_config(phydev);
1337
1338 return 0;
1339 }
1340
1341 #if CONFIG_IS_ENABLED(DM_GPIO)
1342 /* FEC GPIO reset */
fec_gpio_reset(struct fec_priv * priv)1343 static void fec_gpio_reset(struct fec_priv *priv)
1344 {
1345 debug("fec_gpio_reset: fec_gpio_reset(dev)\n");
1346 if (dm_gpio_is_valid(&priv->phy_reset_gpio)) {
1347 dm_gpio_set_value(&priv->phy_reset_gpio, 1);
1348 mdelay(priv->reset_delay);
1349 dm_gpio_set_value(&priv->phy_reset_gpio, 0);
1350 if (priv->reset_post_delay)
1351 mdelay(priv->reset_post_delay);
1352 }
1353 }
1354 #endif
1355
fecmxc_probe(struct udevice * dev)1356 static int fecmxc_probe(struct udevice *dev)
1357 {
1358 bool dm_mii_bus = true;
1359 struct eth_pdata *pdata = dev_get_plat(dev);
1360 struct fec_priv *priv = dev_get_priv(dev);
1361 struct mii_dev *bus = NULL;
1362 uint32_t start;
1363 int ret;
1364
1365 if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
1366 if (enet_fused((ulong)priv->eth)) {
1367 printf("SoC fuse indicates Ethernet@0x%lx is unavailable.\n", (ulong)priv->eth);
1368 return -ENODEV;
1369 }
1370 }
1371
1372 if (IS_ENABLED(CONFIG_IMX8)) {
1373 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1374 if (ret < 0) {
1375 debug("Can't get FEC ipg clk: %d\n", ret);
1376 return ret;
1377 }
1378 ret = clk_enable(&priv->ipg_clk);
1379 if (ret < 0) {
1380 debug("Can't enable FEC ipg clk: %d\n", ret);
1381 return ret;
1382 }
1383
1384 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1385 } else if (CONFIG_IS_ENABLED(CLK_CCF)) {
1386 ret = clk_get_by_name(dev, "ipg", &priv->ipg_clk);
1387 if (ret < 0) {
1388 debug("Can't get FEC ipg clk: %d\n", ret);
1389 return ret;
1390 }
1391 ret = clk_enable(&priv->ipg_clk);
1392 if(ret)
1393 return ret;
1394
1395 ret = clk_get_by_name(dev, "ahb", &priv->ahb_clk);
1396 if (ret < 0) {
1397 debug("Can't get FEC ahb clk: %d\n", ret);
1398 return ret;
1399 }
1400 ret = clk_enable(&priv->ahb_clk);
1401 if (ret)
1402 return ret;
1403
1404 ret = clk_get_by_name(dev, "enet_out", &priv->clk_enet_out);
1405 if (!ret) {
1406 ret = clk_enable(&priv->clk_enet_out);
1407 if (ret)
1408 return ret;
1409 }
1410
1411 ret = clk_get_by_name(dev, "enet_clk_ref", &priv->clk_ref);
1412 if (!ret) {
1413 ret = clk_enable(&priv->clk_ref);
1414 if (ret)
1415 return ret;
1416 }
1417
1418 ret = clk_get_by_name(dev, "ptp", &priv->clk_ptp);
1419 if (!ret) {
1420 ret = clk_enable(&priv->clk_ptp);
1421 if (ret)
1422 return ret;
1423 }
1424
1425 priv->clk_rate = clk_get_rate(&priv->ipg_clk);
1426 }
1427
1428 ret = fec_alloc_descs(priv);
1429 if (ret)
1430 return ret;
1431
1432 #ifdef CONFIG_DM_REGULATOR
1433 if (priv->phy_supply) {
1434 ret = regulator_set_enable(priv->phy_supply, true);
1435 if (ret) {
1436 printf("%s: Error enabling phy supply\n", dev->name);
1437 return ret;
1438 }
1439 }
1440 #endif
1441
1442 #if CONFIG_IS_ENABLED(DM_GPIO)
1443 fec_gpio_reset(priv);
1444 #endif
1445 /* Reset chip. */
1446 writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET,
1447 &priv->eth->ecntrl);
1448 start = get_timer(0);
1449 while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) {
1450 if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
1451 printf("FEC MXC: Timeout reseting chip\n");
1452 goto err_timeout;
1453 }
1454 udelay(10);
1455 }
1456
1457 fec_reg_setup(priv);
1458
1459 priv->dev_id = dev_seq(dev);
1460
1461 #ifdef CONFIG_DM_ETH_PHY
1462 bus = eth_phy_get_mdio_bus(dev);
1463 #endif
1464
1465 if (!bus) {
1466 dm_mii_bus = false;
1467 #ifdef CONFIG_FEC_MXC_MDIO_BASE
1468 bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
1469 dev_seq(dev));
1470 #else
1471 bus = fec_get_miibus((ulong)priv->eth, dev_seq(dev));
1472 #endif
1473 }
1474 if (!bus) {
1475 ret = -ENOMEM;
1476 goto err_mii;
1477 }
1478
1479 #ifdef CONFIG_DM_ETH_PHY
1480 eth_phy_set_mdio_bus(dev, bus);
1481 #endif
1482
1483 priv->bus = bus;
1484 priv->interface = pdata->phy_interface;
1485 switch (priv->interface) {
1486 case PHY_INTERFACE_MODE_MII:
1487 priv->xcv_type = MII100;
1488 break;
1489 case PHY_INTERFACE_MODE_RMII:
1490 priv->xcv_type = RMII;
1491 break;
1492 case PHY_INTERFACE_MODE_RGMII:
1493 case PHY_INTERFACE_MODE_RGMII_ID:
1494 case PHY_INTERFACE_MODE_RGMII_RXID:
1495 case PHY_INTERFACE_MODE_RGMII_TXID:
1496 priv->xcv_type = RGMII;
1497 break;
1498 default:
1499 priv->xcv_type = CONFIG_FEC_XCV_TYPE;
1500 printf("Unsupported interface type %d defaulting to %d\n",
1501 priv->interface, priv->xcv_type);
1502 break;
1503 }
1504
1505 ret = fec_phy_init(priv, dev);
1506 if (ret)
1507 goto err_phy;
1508
1509 return 0;
1510
1511 err_phy:
1512 if (!dm_mii_bus) {
1513 mdio_unregister(bus);
1514 free(bus);
1515 }
1516 err_mii:
1517 err_timeout:
1518 fec_free_descs(priv);
1519 return ret;
1520 }
1521
fecmxc_remove(struct udevice * dev)1522 static int fecmxc_remove(struct udevice *dev)
1523 {
1524 struct fec_priv *priv = dev_get_priv(dev);
1525
1526 free(priv->phydev);
1527 fec_free_descs(priv);
1528 mdio_unregister(priv->bus);
1529 mdio_free(priv->bus);
1530
1531 #ifdef CONFIG_DM_REGULATOR
1532 if (priv->phy_supply)
1533 regulator_set_enable(priv->phy_supply, false);
1534 #endif
1535
1536 return 0;
1537 }
1538
fecmxc_of_to_plat(struct udevice * dev)1539 static int fecmxc_of_to_plat(struct udevice *dev)
1540 {
1541 int ret = 0;
1542 struct eth_pdata *pdata = dev_get_plat(dev);
1543 struct fec_priv *priv = dev_get_priv(dev);
1544 const char *phy_mode;
1545
1546 pdata->iobase = dev_read_addr(dev);
1547 priv->eth = (struct ethernet_regs *)pdata->iobase;
1548
1549 pdata->phy_interface = -1;
1550 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
1551 NULL);
1552 if (phy_mode)
1553 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
1554 if (pdata->phy_interface == -1) {
1555 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
1556 return -EINVAL;
1557 }
1558
1559 #ifdef CONFIG_DM_REGULATOR
1560 device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
1561 #endif
1562
1563 #if CONFIG_IS_ENABLED(DM_GPIO)
1564 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1565 &priv->phy_reset_gpio, GPIOD_IS_OUT);
1566 if (ret < 0)
1567 return 0; /* property is optional, don't return error! */
1568
1569 priv->reset_delay = dev_read_u32_default(dev, "phy-reset-duration", 1);
1570 if (priv->reset_delay > 1000) {
1571 printf("FEC MXC: phy reset duration should be <= 1000ms\n");
1572 /* property value wrong, use default value */
1573 priv->reset_delay = 1;
1574 }
1575
1576 priv->reset_post_delay = dev_read_u32_default(dev,
1577 "phy-reset-post-delay",
1578 0);
1579 if (priv->reset_post_delay > 1000) {
1580 printf("FEC MXC: phy reset post delay should be <= 1000ms\n");
1581 /* property value wrong, use default value */
1582 priv->reset_post_delay = 0;
1583 }
1584 #endif
1585
1586 return 0;
1587 }
1588
1589 static const struct udevice_id fecmxc_ids[] = {
1590 { .compatible = "fsl,imx28-fec" },
1591 { .compatible = "fsl,imx6q-fec" },
1592 { .compatible = "fsl,imx6sl-fec" },
1593 { .compatible = "fsl,imx6sx-fec" },
1594 { .compatible = "fsl,imx6ul-fec" },
1595 { .compatible = "fsl,imx53-fec" },
1596 { .compatible = "fsl,imx7d-fec" },
1597 { .compatible = "fsl,mvf600-fec" },
1598 { }
1599 };
1600
1601 U_BOOT_DRIVER(fecmxc_gem) = {
1602 .name = "fecmxc",
1603 .id = UCLASS_ETH,
1604 .of_match = fecmxc_ids,
1605 .of_to_plat = fecmxc_of_to_plat,
1606 .probe = fecmxc_probe,
1607 .remove = fecmxc_remove,
1608 .ops = &fecmxc_ops,
1609 .priv_auto = sizeof(struct fec_priv),
1610 .plat_auto = sizeof(struct eth_pdata),
1611 };
1612 #endif
1613