1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright 2017-2018 NXP 4 */ 5 6/dts-v1/; 7 8#include "fsl-imx8qm.dtsi" 9#include "fsl-imx8qm-mek-u-boot.dtsi" 10 11/ { 12 model = "Freescale i.MX8QM MEK"; 13 compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; 14 15 chosen { 16 bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; 17 stdout-path = &lpuart0; 18 }; 19 20 reg_usdhc2_vmmc: usdhc2_vmmc { 21 compatible = "regulator-fixed"; 22 regulator-name = "sw-3p3-sd1"; 23 regulator-min-microvolt = <3300000>; 24 regulator-max-microvolt = <3300000>; 25 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; 26 off-on-delay = <4800>; 27 enable-active-high; 28 }; 29}; 30 31&iomuxc { 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pinctrl_hog>; 34 35 imx8qm-mek { 36 pinctrl_hog: hoggrp { 37 fsl,pins = < 38 SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c 39 SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c 40 SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c 41 >; 42 }; 43 44 pinctrl_fec1: fec1grp { 45 fsl,pins = < 46 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 47 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 48 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 49 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 50 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 51 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 52 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 53 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 54 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 55 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 56 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 57 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 58 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 59 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 60 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 61 >; 62 }; 63 64 pinctrl_fec2: fec2grp { 65 fsl,pins = < 66 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 67 SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 68 SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 69 SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 70 SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 71 SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 72 SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 73 SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 74 SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 75 SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 76 SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 77 SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 78 SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 79 >; 80 }; 81 82 pinctrl_lpuart0: lpuart0grp { 83 fsl,pins = < 84 SC_P_UART0_RX_DMA_UART0_RX 0x06000020 85 SC_P_UART0_TX_DMA_UART0_TX 0x06000020 86 >; 87 }; 88 89 pinctrl_usdhc1: usdhc1grp { 90 fsl,pins = < 91 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 92 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 93 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 94 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 95 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 96 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 97 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 98 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 99 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 100 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 101 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 102 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 103 >; 104 }; 105 106 pinctrl_usdhc2_gpio: usdhc2grpgpio { 107 fsl,pins = < 108 SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 109 SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 110 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 111 >; 112 }; 113 114 pinctrl_usdhc2: usdhc2grp { 115 fsl,pins = < 116 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 117 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 118 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 119 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 120 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 121 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 122 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 123 >; 124 }; 125 }; 126}; 127 128&usdhc1 { 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_usdhc1>; 131 bus-width = <8>; 132 non-removable; 133 status = "okay"; 134}; 135 136&usdhc2 { 137 pinctrl-names = "default"; 138 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 139 bus-width = <4>; 140 cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; 141 wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; 142 vmmc-supply = <®_usdhc2_vmmc>; 143 status = "okay"; 144}; 145 146&fec1 { 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_fec1>; 149 phy-mode = "rgmii-txid"; 150 phy-handle = <ðphy0>; 151 fsl,magic-packet; 152 fsl,rgmii_rxc_dly; 153 status = "okay"; 154 155 mdio { 156 #address-cells = <1>; 157 #size-cells = <0>; 158 159 ethphy0: ethernet-phy@0 { 160 compatible = "ethernet-phy-ieee802.3-c22"; 161 reg = <0>; 162 at803x,eee-disabled; 163 at803x,vddio-1p8v; 164 }; 165 166 ethphy1: ethernet-phy@1 { 167 compatible = "ethernet-phy-ieee802.3-c22"; 168 reg = <1>; 169 at803x,eee-disabled; 170 at803x,vddio-1p8v; 171 status = "disabled"; 172 }; 173 }; 174}; 175 176&lpuart0 { /* console */ 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_lpuart0>; 179 status = "okay"; 180}; 181 182&gpio1 { 183 status = "okay"; 184}; 185