1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200-som-p0.dtsi" 9#include "k3-j7200-ddr-evm-lp4-1600.dtsi" 10#include "k3-j721e-ddr.dtsi" 11 12/ { 13 aliases { 14 remoteproc0 = &sysctrler; 15 remoteproc1 = &a72_0; 16 }; 17 18 chosen { 19 stdout-path = &main_uart0; 20 tick-timer = &timer1; 21 firmware-loader = &fs_loader0; 22 }; 23 24 fs_loader0: fs_loader@0 { 25 u-boot,dm-pre-reloc; 26 compatible = "u-boot,fs-loader"; 27 }; 28 29 a72_0: a72@0 { 30 compatible = "ti,am654-rproc"; 31 reg = <0x0 0x00a90000 0x0 0x10>; 32 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>, 33 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>; 34 resets = <&k3_reset 202 0>; 35 clocks = <&k3_clks 61 1>; 36 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>; 37 assigned-clock-rates = <2000000000>, <200000000>; 38 ti,sci = <&dmsc>; 39 ti,sci-proc-id = <32>; 40 ti,sci-host-id = <10>; 41 u-boot,dm-spl; 42 }; 43 44 clk_200mhz: dummy_clock_200mhz { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <200000000>; 48 u-boot,dm-spl; 49 }; 50 51 clk_19_2mhz: dummy_clock_19_2mhz { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 clock-frequency = <19200000>; 55 u-boot,dm-spl; 56 }; 57}; 58 59&memorycontroller { 60 power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>, 61 <&k3_pds 90 TI_SCI_PD_SHARED>; 62 clocks = <&k3_clks 8 5>, <&k3_clks 30 9>; 63}; 64 65&cbass_mcu_wakeup { 66 mcu_secproxy: secproxy@2a380000 { 67 u-boot,dm-spl; 68 compatible = "ti,am654-secure-proxy"; 69 reg = <0x0 0x2a380000 0x0 0x80000>, 70 <0x0 0x2a400000 0x0 0x80000>, 71 <0x0 0x2a480000 0x0 0x80000>; 72 reg-names = "rt", "scfg", "target_data"; 73 #mbox-cells = <1>; 74 }; 75 76 sysctrler: sysctrler { 77 u-boot,dm-spl; 78 compatible = "ti,am654-system-controller"; 79 mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>; 80 mbox-names = "tx", "rx"; 81 }; 82}; 83 84&dmsc { 85 mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>; 86 mbox-names = "tx", "rx", "notify"; 87 ti,host-id = <4>; 88 ti,secure-host; 89}; 90 91&wkup_pmx0 { 92 u-boot,dm-spl; 93 wkup_uart0_pins_default: wkup_uart0_pins_default { 94 u-boot,dm-spl; 95 pinctrl-single,pins = < 96 J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */ 97 J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */ 98 >; 99 }; 100 101 mcu_uart0_pins_default: mcu_uart0_pins_default { 102 u-boot,dm-spl; 103 pinctrl-single,pins = < 104 J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */ 105 J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */ 106 J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */ 107 J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */ 108 >; 109 }; 110 111 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 112 pinctrl-single,pins = < 113 J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */ 114 J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */ 115 >; 116 }; 117 118 mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default { 119 pinctrl-single,pins = < 120 J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */ 121 J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */ 122 J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */ 123 J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */ 124 J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */ 125 J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */ 126 J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */ 127 J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */ 128 J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */ 129 J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */ 130 J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */ 131 J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */ 132 J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */ 133 J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */ 134 >; 135 }; 136 137 wkup_gpio_pins_default: wkup-gpio-pins-default { 138 pinctrl-single,pins = < 139 J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */ 140 >; 141 }; 142}; 143 144&main_pmx0 { 145 u-boot,dm-spl; 146 147 main_uart0_pins_default: main_uart0_pins_default { 148 u-boot,dm-spl; 149 pinctrl-single,pins = < 150 J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ 151 J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ 152 J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */ 153 J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */ 154 >; 155 }; 156 157 main_i2c0_pins_default: main-i2c0-pins-default { 158 u-boot,dm-spl; 159 pinctrl-single,pins = < 160 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ 161 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ 162 >; 163 }; 164 165 main_mmc1_pins_default: main_mmc1_pins_default { 166 pinctrl-single,pins = < 167 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ 168 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ 169 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 170 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ 171 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ 172 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ 173 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ 174 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ 175 >; 176 }; 177 178 main_usbss0_pins_default: main_usbss0_pins_default { 179 pinctrl-single,pins = < 180 J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ 181 >; 182 }; 183}; 184 185&wkup_uart0 { 186 u-boot,dm-spl; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&wkup_uart0_pins_default>; 189 status = "okay"; 190}; 191 192&mcu_uart0 { 193 /delete-property/ power-domains; 194 /delete-property/ clocks; 195 /delete-property/ clock-names; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&mcu_uart0_pins_default>; 198 status = "okay"; 199 clock-frequency = <96000000>; 200}; 201 202&main_uart0 { 203 status = "okay"; 204 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 205 pinctrl-names = "default"; 206 pinctrl-0 = <&main_uart0_pins_default>; 207 status = "okay"; 208}; 209 210&main_sdhci0 { 211 /delete-property/ power-domains; 212 /delete-property/ assigned-clocks; 213 /delete-property/ assigned-clock-parents; 214 pinctrl-0 = <&main_mmc1_pins_default>; 215 pinctrl-names = "default"; 216 clock-names = "clk_xin"; 217 clocks = <&clk_200mhz>; 218 ti,driver-strength-ohm = <50>; 219 non-removable; 220 bus-width = <8>; 221}; 222 223&main_sdhci1 { 224 /delete-property/ power-domains; 225 /delete-property/ assigned-clocks; 226 /delete-property/ assigned-clock-parents; 227 clock-names = "clk_xin"; 228 clocks = <&clk_200mhz>; 229 ti,driver-strength-ohm = <50>; 230}; 231 232&main_i2c0 { 233 pinctrl-names = "default"; 234 pinctrl-0 = <&main_i2c0_pins_default>; 235 clock-frequency = <400000>; 236 237 exp1: gpio@20 { 238 compatible = "ti,tca6416"; 239 reg = <0x20>; 240 gpio-controller; 241 #gpio-cells = <2>; 242 }; 243 244 exp2: gpio@22 { 245 compatible = "ti,tca6424"; 246 reg = <0x22>; 247 gpio-controller; 248 #gpio-cells = <2>; 249 }; 250}; 251 252&usbss0 { 253 pinctrl-names = "default"; 254 pinctrl-0 = <&main_usbss0_pins_default>; 255 ti,vbus-divider; 256 ti,usb2-only; 257}; 258 259&usb0 { 260 dr_mode = "otg"; 261 maximum-speed = "high-speed"; 262}; 263 264&hbmc { 265 status = "okay"; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&mcu_fss0_hpb0_pins_default>; 268 reg = <0x0 0x47040000 0x0 0x100>, 269 <0x0 0x50000000 0x0 0x8000000>; 270 ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */ 271 <0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */ 272 273 flash@0,0 { 274 compatible = "cypress,hyperflash", "cfi-flash"; 275 reg = <0x0 0x0 0x4000000>; 276 }; 277}; 278 279#include "k3-j7200-common-proc-board-u-boot.dtsi" 280